3 # Specific modes implementations for SPARC Architecture 2011. There
4 # is T4 dependency though, an ASI value that is not specified in the
5 # Architecture Manual. But as SPARC universe is rather monocultural,
6 # we imply that processor capable of executing crypto instructions
7 # can handle the ASI in question as well. This means that we ought to
8 # keep eyes open when new processors emerge...
10 # As for above mentioned ASI. It's so called "block initializing
11 # store" which cancels "read" in "read-update-write" on cache lines.
12 # This is "cooperative" optimization, as it reduces overall pressure
13 # on memory interface. Benefits can't be observed/quantified with
14 # usual benchmarks, on the contrary you can notice that single-thread
15 # performance for parallelizable modes is ~1.5% worse for largest
16 # block sizes [though few percent better for not so long ones]. All
17 # this based on suggestions from David Miller.
19 sub asm_init { # to be called with @ARGV as argument
20 for (@_) { $::abibits=64 if (/\-m64/ || /\-xarch\=v9/); }
21 if ($::abibits==64) { $::bias=2047; $::frame=192; $::size_t_cc="%xcc"; }
22 else { $::bias=0; $::frame=112; $::size_t_cc="%icc"; }
26 my ($inp,$out,$len,$key,$ivec)=map("%i$_",(0..5));
28 my ($ileft,$iright,$ooff,$omask,$ivoff,$blk_init)=map("%l$_",(0..7));
30 sub alg_cbc_encrypt_implement {
34 .globl ${alg}${bits}_t4_cbc_encrypt
36 ${alg}${bits}_t4_cbc_encrypt:
37 save %sp, -$::frame, %sp
39 be,pn $::size_t_cc, .L${bits}_cbc_enc_abort
40 sub $inp, $out, $blk_init ! $inp!=$out
42 $::code.=<<___ if (!$::evp);
43 andcc $ivec, 7, $ivoff
44 alignaddr $ivec, %g0, $ivec
46 ldd [$ivec + 0], %f0 ! load ivec
50 faligndata %f0, %f2, %f0
51 faligndata %f2, %f4, %f2
54 $::code.=<<___ if ($::evp);
62 prefetch [$inp + 63], 20
63 call _${alg}${bits}_load_enckey
69 sub $iright, $ileft, $iright
72 movrnz $ooff, 0, $blk_init ! if ( $out&7 ||
73 movleu $::size_t_cc, 0, $blk_init ! $len<128 ||
74 brnz,pn $blk_init, .L${bits}cbc_enc_blk ! $inp==$out)
75 srl $omask, $ooff, $omask
77 alignaddrl $out, %g0, $out
81 .L${bits}_cbc_enc_loop:
88 srlx %o1, $iright, %g1
91 srlx %o2, $iright, %o2
94 xor %g4, %o0, %o0 ! ^= rk[0]
99 fxor %f12, %f0, %f0 ! ^= ivec
101 prefetch [$out + 63], 22
102 prefetch [$inp + 16+63], 20
103 call _${alg}${bits}_encrypt_1x
111 brnz,pt $len, .L${bits}_cbc_enc_loop
114 $::code.=<<___ if ($::evp);
120 $::code.=<<___ if (!$::evp);
124 std %f0, [$ivec + 0] ! write out ivec
128 .L${bits}_cbc_enc_abort:
133 2: ldxa [$inp]0x82, %o0 ! avoid read-after-write hazard
134 ! and ~3x deterioration
136 faligndata %f0, %f0, %f4 ! handle unaligned output
137 faligndata %f0, %f2, %f6
138 faligndata %f2, %f2, %f8
140 stda %f4, [$out + $omask]0xc0 ! partial store
143 orn %g0, $omask, $omask
144 stda %f8, [$out + $omask]0xc0 ! partial store
146 brnz,pt $len, .L${bits}_cbc_enc_loop+4
147 orn %g0, $omask, $omask
149 $::code.=<<___ if ($::evp);
155 $::code.=<<___ if (!$::evp);
159 std %f0, [$ivec + 0] ! write out ivec
165 3: alignaddrl $ivec, $ivoff, %g0 ! handle unaligned ivec
167 srl $omask, $ivoff, $omask
168 faligndata %f0, %f0, %f4
169 faligndata %f0, %f2, %f6
170 faligndata %f2, %f2, %f8
171 stda %f4, [$ivec + $omask]0xc0
174 orn %g0, $omask, $omask
175 stda %f8, [$ivec + $omask]0xc0
181 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
183 .L${bits}cbc_enc_blk:
184 add $out, $len, $blk_init
185 and $blk_init, 63, $blk_init ! tail
186 sub $len, $blk_init, $len
187 add $blk_init, 15, $blk_init ! round up to 16n
189 srl $blk_init, 4, $blk_init
191 .L${bits}_cbc_enc_blk_loop:
197 sllx %o0, $ileft, %o0
198 srlx %o1, $iright, %g1
199 sllx %o1, $ileft, %o1
201 srlx %o2, $iright, %o2
204 xor %g4, %o0, %o0 ! ^= rk[0]
209 fxor %f12, %f0, %f0 ! ^= ivec
211 prefetch [$inp + 16+63], 20
212 call _${alg}${bits}_encrypt_1x
216 stda %f0, [$out]0xe2 ! ASI_BLK_INIT, T4-specific
218 stda %f2, [$out]0xe2 ! ASI_BLK_INIT, T4-specific
219 brnz,pt $len, .L${bits}_cbc_enc_blk_loop
222 membar #StoreLoad|#StoreStore
223 brnz,pt $blk_init, .L${bits}_cbc_enc_loop
226 $::code.=<<___ if ($::evp);
232 $::code.=<<___ if (!$::evp);
236 std %f0, [$ivec + 0] ! write out ivec
242 .type ${alg}${bits}_t4_cbc_encrypt,#function
243 .size ${alg}${bits}_t4_cbc_encrypt,.-${alg}${bits}_t4_cbc_encrypt
247 sub alg_cbc_decrypt_implement {
248 my ($alg,$bits) = @_;
251 .globl ${alg}${bits}_t4_cbc_decrypt
253 ${alg}${bits}_t4_cbc_decrypt:
254 save %sp, -$::frame, %sp
256 be,pn $::size_t_cc, .L${bits}_cbc_dec_abort
257 sub $inp, $out, $blk_init ! $inp!=$out
259 $::code.=<<___ if (!$::evp);
260 andcc $ivec, 7, $ivoff
261 alignaddr $ivec, %g0, $ivec
263 ldd [$ivec + 0], %f12 ! load ivec
265 ldd [$ivec + 8], %f14
266 ldd [$ivec + 16], %f0
267 faligndata %f12, %f14, %f12
268 faligndata %f14, %f0, %f14
271 $::code.=<<___ if ($::evp);
272 ld [$ivec + 0], %f12 ! load ivec
275 ld [$ivec + 12], %f15
279 prefetch [$inp + 63], 20
280 call _${alg}${bits}_load_deckey
283 sll $ileft, 3, $ileft
286 sub $iright, $ileft, $iright
289 movrnz $ooff, 0, $blk_init ! if ( $out&7 ||
290 movleu $::size_t_cc, 0, $blk_init ! $len<256 ||
291 brnz,pn $blk_init, .L${bits}cbc_dec_blk ! $inp==$out)
292 srl $omask, $ooff, $omask
294 andcc $len, 16, %g0 ! is number of blocks even?
296 alignaddrl $out, %g0, $out
297 bz %icc, .L${bits}_cbc_dec_loop2x
299 .L${bits}_cbc_dec_loop:
305 sllx %o0, $ileft, %o0
306 srlx %o1, $iright, %g1
307 sllx %o1, $ileft, %o1
309 srlx %o2, $iright, %o2
312 xor %g4, %o0, %o2 ! ^= rk[0]
317 prefetch [$out + 63], 22
318 prefetch [$inp + 16+63], 20
319 call _${alg}${bits}_decrypt_1x
322 fxor %f12, %f0, %f0 ! ^= ivec
332 brnz,pt $len, .L${bits}_cbc_dec_loop2x
335 $::code.=<<___ if ($::evp);
339 st %f15, [$ivec + 12]
341 $::code.=<<___ if (!$::evp);
342 brnz,pn $ivoff, .L${bits}_cbc_dec_unaligned_ivec
345 std %f12, [$ivec + 0] ! write out ivec
346 std %f14, [$ivec + 8]
349 .L${bits}_cbc_dec_abort:
354 2: ldxa [$inp]0x82, %o0 ! avoid read-after-write hazard
355 ! and ~3x deterioration
357 faligndata %f0, %f0, %f4 ! handle unaligned output
358 faligndata %f0, %f2, %f6
359 faligndata %f2, %f2, %f8
361 stda %f4, [$out + $omask]0xc0 ! partial store
364 orn %g0, $omask, $omask
365 stda %f8, [$out + $omask]0xc0 ! partial store
367 brnz,pt $len, .L${bits}_cbc_dec_loop2x+4
368 orn %g0, $omask, $omask
370 $::code.=<<___ if ($::evp);
374 st %f15, [$ivec + 12]
376 $::code.=<<___ if (!$::evp);
377 brnz,pn $ivoff, .L${bits}_cbc_dec_unaligned_ivec
380 std %f12, [$ivec + 0] ! write out ivec
381 std %f14, [$ivec + 8]
387 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
389 .L${bits}_cbc_dec_loop2x:
397 sllx %o0, $ileft, %o0
398 srlx %o1, $iright, %g1
400 sllx %o1, $ileft, %o1
401 srlx %o2, $iright, %g1
403 sllx %o2, $ileft, %o2
404 srlx %o3, $iright, %g1
406 sllx %o3, $ileft, %o3
407 srlx %o4, $iright, %o4
410 xor %g4, %o0, %o4 ! ^= rk[0]
419 prefetch [$out + 63], 22
420 prefetch [$inp + 32+63], 20
421 call _${alg}${bits}_decrypt_2x
426 fxor %f12, %f0, %f0 ! ^= ivec
440 brnz,pt $len, .L${bits}_cbc_dec_loop2x
443 $::code.=<<___ if ($::evp);
447 st %f15, [$ivec + 12]
449 $::code.=<<___ if (!$::evp);
450 brnz,pn $ivoff, .L${bits}_cbc_dec_unaligned_ivec
453 std %f12, [$ivec + 0] ! write out ivec
454 std %f14, [$ivec + 8]
461 2: ldxa [$inp]0x82, %o0 ! avoid read-after-write hazard
462 ! and ~3x deterioration
464 faligndata %f0, %f0, %f8 ! handle unaligned output
465 faligndata %f0, %f2, %f0
466 faligndata %f2, %f4, %f2
467 faligndata %f4, %f6, %f4
468 faligndata %f6, %f6, %f6
469 stda %f8, [$out + $omask]0xc0 ! partial store
474 orn %g0, $omask, $omask
475 stda %f6, [$out + $omask]0xc0 ! partial store
477 brnz,pt $len, .L${bits}_cbc_dec_loop2x+4
478 orn %g0, $omask, $omask
480 $::code.=<<___ if ($::evp);
484 st %f15, [$ivec + 12]
486 $::code.=<<___ if (!$::evp);
487 brnz,pn $ivoff, .L${bits}_cbc_dec_unaligned_ivec
490 std %f12, [$ivec + 0] ! write out ivec
491 std %f14, [$ivec + 8]
496 .L${bits}_cbc_dec_unaligned_ivec:
497 alignaddrl $ivec, $ivoff, %g0 ! handle unaligned ivec
499 srl $omask, $ivoff, $omask
500 faligndata %f12, %f12, %f0
501 faligndata %f12, %f14, %f2
502 faligndata %f14, %f14, %f4
503 stda %f0, [$ivec + $omask]0xc0
506 orn %g0, $omask, $omask
507 stda %f4, [$ivec + $omask]0xc0
513 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
515 .L${bits}cbc_dec_blk:
516 add $out, $len, $blk_init
517 and $blk_init, 63, $blk_init ! tail
518 sub $len, $blk_init, $len
519 add $blk_init, 15, $blk_init ! round up to 16n
521 srl $blk_init, 4, $blk_init
523 add $blk_init, 1, $blk_init
525 .L${bits}_cbc_dec_blk_loop2x:
533 sllx %o0, $ileft, %o0
534 srlx %o1, $iright, %g1
536 sllx %o1, $ileft, %o1
537 srlx %o2, $iright, %g1
539 sllx %o2, $ileft, %o2
540 srlx %o3, $iright, %g1
542 sllx %o3, $ileft, %o3
543 srlx %o4, $iright, %o4
546 xor %g4, %o0, %o4 ! ^= rk[0]
555 prefetch [$inp + 32+63], 20
556 call _${alg}${bits}_decrypt_2x
562 fxor %f12, %f0, %f0 ! ^= ivec
569 stda %f0, [$out]0xe2 ! ASI_BLK_INIT, T4-specific
571 stda %f2, [$out]0xe2 ! ASI_BLK_INIT, T4-specific
573 stda %f4, [$out]0xe2 ! ASI_BLK_INIT, T4-specific
575 stda %f6, [$out]0xe2 ! ASI_BLK_INIT, T4-specific
576 bgu,pt $::size_t_cc, .L${bits}_cbc_dec_blk_loop2x
579 add $blk_init, $len, $len
580 andcc $len, 1, %g0 ! is number of blocks even?
581 membar #StoreLoad|#StoreStore
582 bnz,pt %icc, .L${bits}_cbc_dec_loop
584 brnz,pn $len, .L${bits}_cbc_dec_loop2x
587 $::code.=<<___ if ($::evp);
588 st %f12, [$ivec + 0] ! write out ivec
591 st %f15, [$ivec + 12]
593 $::code.=<<___ if (!$::evp);
597 std %f12, [$ivec + 0] ! write out ivec
598 std %f14, [$ivec + 8]
603 .type ${alg}${bits}_t4_cbc_decrypt,#function
604 .size ${alg}${bits}_t4_cbc_decrypt,.-${alg}${bits}_t4_cbc_decrypt
608 sub alg_ctr32_implement {
609 my ($alg,$bits) = @_;
612 .globl ${alg}${bits}_t4_ctr32_encrypt
614 ${alg}${bits}_t4_ctr32_encrypt:
615 save %sp, -$::frame, %sp
618 prefetch [$inp + 63], 20
619 call _${alg}${bits}_load_enckey
622 ld [$ivec + 0], %l4 ! counter
630 xor %o5, %g4, %g4 ! ^= rk[0]
632 movxtod %g4, %f14 ! most significant 64 bits
634 sub $inp, $out, $blk_init ! $inp!=$out
637 sll $ileft, 3, $ileft
640 sub $iright, $ileft, $iright
643 movrnz $ooff, 0, $blk_init ! if ( $out&7 ||
644 movleu $::size_t_cc, 0, $blk_init ! $len<256 ||
645 brnz,pn $blk_init, .L${bits}_ctr32_blk ! $inp==$out)
646 srl $omask, $ooff, $omask
648 andcc $len, 16, %g0 ! is number of blocks even?
649 alignaddrl $out, %g0, $out
650 bz %icc, .L${bits}_ctr32_loop2x
652 .L${bits}_ctr32_loop:
658 sllx %o0, $ileft, %o0
659 srlx %o1, $iright, %g1
660 sllx %o1, $ileft, %o1
662 srlx %o2, $iright, %o2
665 xor %g5, %l7, %g1 ! ^= rk[0]
668 srl %l7, 0, %l7 ! clruw
669 prefetch [$out + 63], 22
670 prefetch [$inp + 16+63], 20
672 $::code.=<<___ if ($alg eq "aes");
673 aes_eround01 %f16, %f14, %f2, %f4
674 aes_eround23 %f18, %f14, %f2, %f2
676 $::code.=<<___ if ($alg eq "cmll");
677 camellia_f %f16, %f2, %f14, %f2
678 camellia_f %f18, %f14, %f2, %f0
681 call _${alg}${bits}_encrypt_1x+8
686 fxor %f10, %f0, %f0 ! ^= inp
694 brnz,pt $len, .L${bits}_ctr32_loop2x
701 2: ldxa [$inp]0x82, %o0 ! avoid read-after-write hazard
702 ! and ~3x deterioration
704 faligndata %f0, %f0, %f4 ! handle unaligned output
705 faligndata %f0, %f2, %f6
706 faligndata %f2, %f2, %f8
707 stda %f4, [$out + $omask]0xc0 ! partial store
710 orn %g0, $omask, $omask
711 stda %f8, [$out + $omask]0xc0 ! partial store
713 brnz,pt $len, .L${bits}_ctr32_loop2x+4
714 orn %g0, $omask, $omask
719 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
721 .L${bits}_ctr32_loop2x:
729 sllx %o0, $ileft, %o0
730 srlx %o1, $iright, %g1
732 sllx %o1, $ileft, %o1
733 srlx %o2, $iright, %g1
735 sllx %o2, $ileft, %o2
736 srlx %o3, $iright, %g1
738 sllx %o3, $ileft, %o3
739 srlx %o4, $iright, %o4
742 xor %g5, %l7, %g1 ! ^= rk[0]
745 srl %l7, 0, %l7 ! clruw
749 srl %l7, 0, %l7 ! clruw
750 prefetch [$out + 63], 22
751 prefetch [$inp + 32+63], 20
753 $::code.=<<___ if ($alg eq "aes");
754 aes_eround01 %f16, %f14, %f2, %f8
755 aes_eround23 %f18, %f14, %f2, %f2
756 aes_eround01 %f16, %f14, %f6, %f10
757 aes_eround23 %f18, %f14, %f6, %f6
759 $::code.=<<___ if ($alg eq "cmll");
760 camellia_f %f16, %f2, %f14, %f2
761 camellia_f %f16, %f6, %f14, %f6
762 camellia_f %f18, %f14, %f2, %f0
763 camellia_f %f18, %f14, %f6, %f4
766 call _${alg}${bits}_encrypt_2x+16
772 fxor %f8, %f0, %f0 ! ^= inp
785 brnz,pt $len, .L${bits}_ctr32_loop2x
792 2: ldxa [$inp]0x82, %o0 ! avoid read-after-write hazard
793 ! and ~3x deterioration
795 faligndata %f0, %f0, %f8 ! handle unaligned output
796 faligndata %f0, %f2, %f0
797 faligndata %f2, %f4, %f2
798 faligndata %f4, %f6, %f4
799 faligndata %f6, %f6, %f6
801 stda %f8, [$out + $omask]0xc0 ! partial store
806 orn %g0, $omask, $omask
807 stda %f6, [$out + $omask]0xc0 ! partial store
809 brnz,pt $len, .L${bits}_ctr32_loop2x+4
810 orn %g0, $omask, $omask
815 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
818 add $out, $len, $blk_init
819 and $blk_init, 63, $blk_init ! tail
820 sub $len, $blk_init, $len
821 add $blk_init, 15, $blk_init ! round up to 16n
823 srl $blk_init, 4, $blk_init
825 add $blk_init, 1, $blk_init
827 .L${bits}_ctr32_blk_loop2x:
835 sllx %o0, $ileft, %o0
836 srlx %o1, $iright, %g1
838 sllx %o1, $ileft, %o1
839 srlx %o2, $iright, %g1
841 sllx %o2, $ileft, %o2
842 srlx %o3, $iright, %g1
844 sllx %o3, $ileft, %o3
845 srlx %o4, $iright, %o4
848 xor %g5, %l7, %g1 ! ^= rk[0]
851 srl %l7, 0, %l7 ! clruw
855 srl %l7, 0, %l7 ! clruw
856 prefetch [$inp + 32+63], 20
858 $::code.=<<___ if ($alg eq "aes");
859 aes_eround01 %f16, %f14, %f2, %f8
860 aes_eround23 %f18, %f14, %f2, %f2
861 aes_eround01 %f16, %f14, %f6, %f10
862 aes_eround23 %f18, %f14, %f6, %f6
864 $::code.=<<___ if ($alg eq "cmll");
865 camellia_f %f16, %f2, %f14, %f2
866 camellia_f %f16, %f6, %f14, %f6
867 camellia_f %f18, %f14, %f2, %f0
868 camellia_f %f18, %f14, %f6, %f4
871 call _${alg}${bits}_encrypt_2x+16
878 fxor %f8, %f0, %f0 ! ^= inp
884 stda %f0, [$out]0xe2 ! ASI_BLK_INIT, T4-specific
886 stda %f2, [$out]0xe2 ! ASI_BLK_INIT, T4-specific
888 stda %f4, [$out]0xe2 ! ASI_BLK_INIT, T4-specific
890 stda %f6, [$out]0xe2 ! ASI_BLK_INIT, T4-specific
891 bgu,pt $::size_t_cc, .L${bits}_ctr32_blk_loop2x
894 add $blk_init, $len, $len
895 andcc $len, 1, %g0 ! is number of blocks even?
896 membar #StoreLoad|#StoreStore
897 bnz,pt %icc, .L${bits}_ctr32_loop
899 brnz,pn $len, .L${bits}_ctr32_loop2x
904 .type ${alg}${bits}_t4_ctr32_encrypt,#function
905 .size ${alg}${bits}_t4_ctr32_encrypt,.-${alg}${bits}_t4_ctr32_encrypt
909 sub alg_xts_implement {
910 my ($alg,$bits,$dir) = @_;
911 my ($inp,$out,$len,$key1,$key2,$ivec)=map("%i$_",(0..5));
915 .globl ${alg}${bits}_t4_xts_${dir}crypt
917 ${alg}${bits}_t4_xts_${dir}crypt:
918 save %sp, -$::frame-16, %sp
921 add %fp, $::bias-16, %o1
922 call ${alg}_t4_encrypt
925 add %fp, $::bias-16, %l7
927 add %fp, $::bias-8, %l7
928 ldxa [%l7]0x88, %g3 ! %g3:%g2 is tweak
930 sethi %hi(0x76543210), %l7
931 or %l7, %lo(0x76543210), %l7
932 bmask %l7, %g0, %g0 ! byte swap mask
935 prefetch [$inp + 63], 20
936 call _${alg}${bits}_load_${dir}ckey
940 $code.=<<___ if ($dir eq "de");
947 sub $inp, $out, $blk_init ! $inp!=$out
950 sll $ileft, 3, $ileft
953 sub $iright, $ileft, $iright
956 movrnz $ooff, 0, $blk_init ! if ( $out&7 ||
957 movleu $::size_t_cc, 0, $blk_init ! $len<256 ||
958 brnz,pn $blk_init, .L${bits}_xts_${dir}blk ! $inp==$out)
959 srl $omask, $ooff, $omask
961 andcc $len, 16, %g0 ! is number of blocks even?
963 $code.=<<___ if ($dir eq "de");
964 brz,pn $len, .L${bits}_xts_${dir}steal
967 alignaddrl $out, %g0, $out
968 bz %icc, .L${bits}_xts_${dir}loop2x
970 .L${bits}_xts_${dir}loop:
976 sllx %o0, $ileft, %o0
977 srlx %o1, $iright, %g1
978 sllx %o1, $ileft, %o1
980 srlx %o2, $iright, %o2
985 bshuffle %f12, %f12, %f12
986 bshuffle %f14, %f14, %f14
988 xor %g4, %o0, %o0 ! ^= rk[0]
993 fxor %f12, %f0, %f0 ! ^= tweak[0]
996 prefetch [$out + 63], 22
997 prefetch [$inp + 16+63], 20
998 call _${alg}${bits}_${dir}crypt_1x
1001 fxor %f12, %f0, %f0 ! ^= tweak[0]
1004 srax %g3, 63, %l7 ! next tweak value
1015 brnz,pt $len, .L${bits}_xts_${dir}loop2x
1018 brnz,pn $rem, .L${bits}_xts_${dir}steal
1025 2: ldxa [$inp]0x82, %o0 ! avoid read-after-write hazard
1026 ! and ~3x deterioration
1028 faligndata %f0, %f0, %f4 ! handle unaligned output
1029 faligndata %f0, %f2, %f6
1030 faligndata %f2, %f2, %f8
1031 stda %f4, [$out + $omask]0xc0 ! partial store
1034 orn %g0, $omask, $omask
1035 stda %f8, [$out + $omask]0xc0 ! partial store
1037 brnz,pt $len, .L${bits}_xts_${dir}loop2x+4
1038 orn %g0, $omask, $omask
1040 brnz,pn $rem, .L${bits}_xts_${dir}steal
1046 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1048 .L${bits}_xts_${dir}loop2x:
1051 ldx [$inp + 16], %o2
1053 ldx [$inp + 24], %o3
1055 ldx [$inp + 32], %o4
1056 sllx %o0, $ileft, %o0
1057 srlx %o1, $iright, %g1
1059 sllx %o1, $ileft, %o1
1060 srlx %o2, $iright, %g1
1062 sllx %o2, $ileft, %o2
1063 srlx %o3, $iright, %g1
1065 sllx %o3, $ileft, %o3
1066 srlx %o4, $iright, %o4
1071 bshuffle %f12, %f12, %f12
1072 bshuffle %f14, %f14, %f14
1074 srax %g3, 63, %l7 ! next tweak value
1082 bshuffle %f8, %f8, %f8
1083 bshuffle %f10, %f10, %f10
1085 xor %g4, %o0, %o0 ! ^= rk[0]
1087 xor %g4, %o2, %o2 ! ^= rk[0]
1094 fxor %f12, %f0, %f0 ! ^= tweak[0]
1096 fxor %f8, %f4, %f4 ! ^= tweak[0]
1099 prefetch [$out + 63], 22
1100 prefetch [$inp + 32+63], 20
1101 call _${alg}${bits}_${dir}crypt_2x
1107 srax %g3, 63, %l7 ! next tweak value
1113 bshuffle %f8, %f8, %f8
1114 bshuffle %f10, %f10, %f10
1116 fxor %f12, %f0, %f0 ! ^= tweak[0]
1126 std %f4, [$out + 16]
1127 std %f6, [$out + 24]
1128 brnz,pt $len, .L${bits}_xts_${dir}loop2x
1133 brnz,pn $rem, .L${bits}_xts_${dir}steal
1140 2: ldxa [$inp]0x82, %o0 ! avoid read-after-write hazard
1141 ! and ~3x deterioration
1143 faligndata %f0, %f0, %f8 ! handle unaligned output
1144 faligndata %f0, %f2, %f10
1145 faligndata %f2, %f4, %f12
1146 faligndata %f4, %f6, %f14
1147 faligndata %f6, %f6, %f0
1149 stda %f8, [$out + $omask]0xc0 ! partial store
1150 std %f10, [$out + 8]
1151 std %f12, [$out + 16]
1152 std %f14, [$out + 24]
1154 orn %g0, $omask, $omask
1155 stda %f0, [$out + $omask]0xc0 ! partial store
1157 brnz,pt $len, .L${bits}_xts_${dir}loop2x+4
1158 orn %g0, $omask, $omask
1162 brnz,pn $rem, .L${bits}_xts_${dir}steal
1168 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1170 .L${bits}_xts_${dir}blk:
1171 add $out, $len, $blk_init
1172 and $blk_init, 63, $blk_init ! tail
1173 sub $len, $blk_init, $len
1174 add $blk_init, 15, $blk_init ! round up to 16n
1176 srl $blk_init, 4, $blk_init
1178 add $blk_init, 1, $blk_init
1180 .L${bits}_xts_${dir}blk2x:
1183 ldx [$inp + 16], %o2
1185 ldx [$inp + 24], %o3
1187 ldx [$inp + 32], %o4
1188 sllx %o0, $ileft, %o0
1189 srlx %o1, $iright, %g1
1191 sllx %o1, $ileft, %o1
1192 srlx %o2, $iright, %g1
1194 sllx %o2, $ileft, %o2
1195 srlx %o3, $iright, %g1
1197 sllx %o3, $ileft, %o3
1198 srlx %o4, $iright, %o4
1203 bshuffle %f12, %f12, %f12
1204 bshuffle %f14, %f14, %f14
1206 srax %g3, 63, %l7 ! next tweak value
1214 bshuffle %f8, %f8, %f8
1215 bshuffle %f10, %f10, %f10
1217 xor %g4, %o0, %o0 ! ^= rk[0]
1219 xor %g4, %o2, %o2 ! ^= rk[0]
1226 fxor %f12, %f0, %f0 ! ^= tweak[0]
1228 fxor %f8, %f4, %f4 ! ^= tweak[0]
1231 prefetch [$inp + 32+63], 20
1232 call _${alg}${bits}_${dir}crypt_2x
1238 srax %g3, 63, %l7 ! next tweak value
1244 bshuffle %f8, %f8, %f8
1245 bshuffle %f10, %f10, %f10
1247 fxor %f12, %f0, %f0 ! ^= tweak[0]
1253 stda %f0, [$out]0xe2 ! ASI_BLK_INIT, T4-specific
1255 stda %f2, [$out]0xe2 ! ASI_BLK_INIT, T4-specific
1257 stda %f4, [$out]0xe2 ! ASI_BLK_INIT, T4-specific
1259 stda %f6, [$out]0xe2 ! ASI_BLK_INIT, T4-specific
1260 bgu,pt $::size_t_cc, .L${bits}_xts_${dir}blk2x
1263 add $blk_init, $len, $len
1264 andcc $len, 1, %g0 ! is number of blocks even?
1265 membar #StoreLoad|#StoreStore
1266 bnz,pt %icc, .L${bits}_xts_${dir}loop
1268 brnz,pn $len, .L${bits}_xts_${dir}loop2x
1273 brnz,pn $rem, .L${bits}_xts_${dir}steal
1278 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1280 $code.=<<___ if ($dir eq "en");
1282 .L${bits}_xts_${dir}steal:
1283 std %f0, [%fp + $::bias-16] ! copy of output
1284 std %f2, [%fp + $::bias-8]
1286 srl $ileft, 3, $ileft
1287 add %fp, $::bias-16, %l7
1288 add $inp, $ileft, $inp ! original $inp+$len&-15
1289 add $out, $ooff, $out ! original $out+$len&-15
1293 .L${bits}_xts_${dir}stealing:
1294 ldub [$inp + $ileft], %o0
1295 ldub [%l7 + $ileft], %o1
1297 stb %o0, [%l7 + $ileft]
1298 stb %o1, [$out + $ileft]
1299 brnz $rem, .L${bits}_xts_${dir}stealing
1305 sub $out, $ooff, $out
1306 ba .L${bits}_xts_${dir}loop ! one more time
1307 mov 1, $len ! $rem is 0
1309 $code.=<<___ if ($dir eq "de");
1311 .L${bits}_xts_${dir}steal:
1316 ldx [$inp + 16], %o2
1317 sllx %o0, $ileft, %o0
1318 srlx %o1, $iright, %g1
1319 sllx %o1, $ileft, %o1
1321 srlx %o2, $iright, %o2
1324 srax %g3, 63, %l7 ! next tweak value
1332 bshuffle %f12, %f12, %f12
1333 bshuffle %f14, %f14, %f14
1335 xor %g4, %o0, %o0 ! ^= rk[0]
1340 fxor %f12, %f0, %f0 ! ^= tweak[0]
1343 call _${alg}${bits}_${dir}crypt_1x
1346 fxor %f12, %f0, %f0 ! ^= tweak[0]
1349 std %f0, [%fp + $::bias-16]
1350 std %f2, [%fp + $::bias-8]
1352 srl $ileft, 3, $ileft
1353 add %fp, $::bias-16, %l7
1354 add $inp, $ileft, $inp ! original $inp+$len&-15
1355 add $out, $ooff, $out ! original $out+$len&-15
1360 .L${bits}_xts_${dir}stealing:
1361 ldub [$inp + $ileft], %o0
1362 ldub [%l7 + $ileft], %o1
1364 stb %o0, [%l7 + $ileft]
1365 stb %o1, [$out + $ileft]
1366 brnz $rem, .L${bits}_xts_${dir}stealing
1372 sub $out, $ooff, $out
1373 ba .L${bits}_xts_${dir}loop ! one more time
1374 mov 1, $len ! $rem is 0
1379 .type ${alg}${bits}_t4_xts_${dir}crypt,#function
1380 .size ${alg}${bits}_t4_xts_${dir}crypt,.-${alg}${bits}_t4_xts_${dir}crypt
1384 # Purpose of these subroutines is to explicitly encode VIS instructions,
1385 # so that one can compile the module without having to specify VIS
1386 # extensions on compiler command line, e.g. -xarch=v9 vs. -xarch=v9a.
1387 # Idea is to reserve for option to produce "universal" binary and let
1388 # programmer detect if current CPU is VIS capable at run-time.
1390 my ($mnemonic,$rs1,$rs2,$rd)=@_;
1392 my %visopf = ( "faligndata" => 0x048,
1393 "bshuffle" => 0x04c,
1398 $ref = "$mnemonic\t$rs1,$rs2,$rd";
1400 if ($opf=$visopf{$mnemonic}) {
1401 foreach ($rs1,$rs2,$rd) {
1402 return $ref if (!/%f([0-9]{1,2})/);
1405 return $ref if ($1&1);
1406 # re-encode for upper double register addressing
1411 return sprintf ".word\t0x%08x !%s",
1412 0x81b00000|$rd<<25|$rs1<<14|$opf<<5|$rs2,
1420 my ($mnemonic,$rs1,$rs2,$rd)=@_;
1421 my %bias = ( "g" => 0, "o" => 8, "l" => 16, "i" => 24 );
1423 my %visopf = ( "addxc" => 0x011,
1426 "alignaddr" => 0x018,
1428 "alignaddrl" => 0x01a );
1430 $ref = "$mnemonic\t$rs1,$rs2,$rd";
1432 if ($opf=$visopf{$mnemonic}) {
1433 foreach ($rs1,$rs2,$rd) {
1434 return $ref if (!/%([goli])([0-9])/);
1438 return sprintf ".word\t0x%08x !%s",
1439 0x81b00000|$rd<<25|$rs1<<14|$opf<<5|$rs2,
1446 sub unaes_round { # 4-argument instructions
1447 my ($mnemonic,$rs1,$rs2,$rs3,$rd)=@_;
1449 my %aesopf = ( "aes_eround01" => 0,
1450 "aes_eround23" => 1,
1451 "aes_dround01" => 2,
1452 "aes_dround23" => 3,
1453 "aes_eround01_l"=> 4,
1454 "aes_eround23_l"=> 5,
1455 "aes_dround01_l"=> 6,
1456 "aes_dround23_l"=> 7,
1457 "aes_kexpand1" => 8 );
1459 $ref = "$mnemonic\t$rs1,$rs2,$rs3,$rd";
1461 if (defined($opf=$aesopf{$mnemonic})) {
1462 $rs3 = ($rs3 =~ /%f([0-6]*[02468])/) ? (($1|$1>>5)&31) : $rs3;
1463 foreach ($rs1,$rs2,$rd) {
1464 return $ref if (!/%f([0-9]{1,2})/);
1467 return $ref if ($1&1);
1468 # re-encode for upper double register addressing
1473 return sprintf ".word\t0x%08x !%s",
1474 2<<30|$rd<<25|0x19<<19|$rs1<<14|$rs3<<9|$opf<<5|$rs2,
1481 sub unaes_kexpand { # 3-argument instructions
1482 my ($mnemonic,$rs1,$rs2,$rd)=@_;
1484 my %aesopf = ( "aes_kexpand0" => 0x130,
1485 "aes_kexpand2" => 0x131 );
1487 $ref = "$mnemonic\t$rs1,$rs2,$rd";
1489 if (defined($opf=$aesopf{$mnemonic})) {
1490 foreach ($rs1,$rs2,$rd) {
1491 return $ref if (!/%f([0-9]{1,2})/);
1494 return $ref if ($1&1);
1495 # re-encode for upper double register addressing
1500 return sprintf ".word\t0x%08x !%s",
1501 2<<30|$rd<<25|0x36<<19|$rs1<<14|$opf<<5|$rs2,
1508 sub uncamellia_f { # 4-argument instructions
1509 my ($mnemonic,$rs1,$rs2,$rs3,$rd)=@_;
1512 $ref = "$mnemonic\t$rs1,$rs2,$rs3,$rd";
1515 $rs3 = ($rs3 =~ /%f([0-6]*[02468])/) ? (($1|$1>>5)&31) : $rs3;
1516 foreach ($rs1,$rs2,$rd) {
1517 return $ref if (!/%f([0-9]{1,2})/);
1520 return $ref if ($1&1);
1521 # re-encode for upper double register addressing
1526 return sprintf ".word\t0x%08x !%s",
1527 2<<30|$rd<<25|0x19<<19|$rs1<<14|$rs3<<9|0xc<<5|$rs2,
1534 sub uncamellia3 { # 3-argument instructions
1535 my ($mnemonic,$rs1,$rs2,$rd)=@_;
1537 my %cmllopf = ( "camellia_fl" => 0x13c,
1538 "camellia_fli" => 0x13d );
1540 $ref = "$mnemonic\t$rs1,$rs2,$rd";
1542 if (defined($opf=$cmllopf{$mnemonic})) {
1543 foreach ($rs1,$rs2,$rd) {
1544 return $ref if (!/%f([0-9]{1,2})/);
1547 return $ref if ($1&1);
1548 # re-encode for upper double register addressing
1553 return sprintf ".word\t0x%08x !%s",
1554 2<<30|$rd<<25|0x36<<19|$rs1<<14|$opf<<5|$rs2,
1561 sub unmovxtox { # 2-argument instructions
1562 my ($mnemonic,$rs,$rd)=@_;
1563 my %bias = ( "g" => 0, "o" => 8, "l" => 16, "i" => 24, "f" => 0 );
1565 my %movxopf = ( "movdtox" => 0x110,
1566 "movstouw" => 0x111,
1567 "movstosw" => 0x113,
1569 "movwtos" => 0x119 );
1571 $ref = "$mnemonic\t$rs,$rd";
1573 if (defined($opf=$movxopf{$mnemonic})) {
1575 return $ref if (!/%([fgoli])([0-9]{1,2})/);
1578 return $ref if ($2&1);
1579 # re-encode for upper double register addressing
1584 return sprintf ".word\t0x%08x !%s",
1585 2<<30|$rd<<25|0x36<<19|$opf<<5|$rs,
1593 my ($mnemonic)=shift;
1596 my %desopf = ( "des_round" => 0b1001,
1597 "des_ip" => 0b100110100,
1598 "des_iip" => 0b100110101,
1599 "des_kexpand" => 0b100110110 );
1601 $ref = "$mnemonic\t".join(",",@_);
1603 if (defined($opf=$desopf{$mnemonic})) { # 4-arg
1604 if ($mnemonic eq "des_round") {
1605 foreach (@args[0..3]) {
1606 return $ref if (!/%f([0-9]{1,2})/);
1609 return $ref if ($1&1);
1610 # re-encode for upper double register addressing
1614 return sprintf ".word\t0x%08x !%s",
1615 2<<30|0b011001<<19|$opf<<5|$args[0]<<14|$args[1]|$args[2]<<9|$args[3]<<25,
1617 } elsif ($mnemonic eq "des_kexpand") { # 3-arg
1618 foreach (@args[0..2]) {
1619 return $ref if (!/(%f)?([0-9]{1,2})/);
1622 return $ref if ($2&1);
1623 # re-encode for upper double register addressing
1627 return sprintf ".word\t0x%08x !%s",
1628 2<<30|0b110110<<19|$opf<<5|$args[0]<<14|$args[1]|$args[2]<<25,
1631 foreach (@args[0..1]) {
1632 return $ref if (!/%f([0-9]{1,2})/);
1635 return $ref if ($2&1);
1636 # re-encode for upper double register addressing
1640 return sprintf ".word\t0x%08x !%s",
1641 2<<30|0b110110<<19|$opf<<5|$args[0]<<14|$args[1]<<25,
1649 sub emit_assembler {
1650 foreach (split("\n",$::code)) {
1651 s/\`([^\`]*)\`/eval $1/ge;
1653 s/\b(f[a-z]+2[sd]*)\s+(%f[0-9]{1,2}),\s*(%f[0-9]{1,2})\s*$/$1\t%f0,$2,$3/go;
1655 s/\b(aes_[edk][^\s]*)\s+(%f[0-9]{1,2}),\s*(%f[0-9]{1,2}),\s*([%fx0-9]+),\s*(%f[0-9]{1,2})/
1656 &unaes_round($1,$2,$3,$4,$5)
1658 s/\b(aes_kexpand[02])\s+(%f[0-9]{1,2}),\s*(%f[0-9]{1,2}),\s*(%f[0-9]{1,2})/
1659 &unaes_kexpand($1,$2,$3,$4)
1661 s/\b(camellia_f)\s+(%f[0-9]{1,2}),\s*(%f[0-9]{1,2}),\s*([%fx0-9]+),\s*(%f[0-9]{1,2})/
1662 &uncamellia_f($1,$2,$3,$4,$5)
1664 s/\b(camellia_[^s]+)\s+(%f[0-9]{1,2}),\s*(%f[0-9]{1,2}),\s*(%f[0-9]{1,2})/
1665 &uncamellia3($1,$2,$3,$4)
1667 s/\b(des_\w+)\s+(%f[0-9]{1,2}),\s*([%fx0-9]+)(?:,\s*(%f[0-9]{1,2})(?:,\s*(%f[0-9]{1,2}))?)?/
1668 &undes($1,$2,$3,$4,$5)
1670 s/\b(mov[ds]to\w+)\s+(%f[0-9]{1,2}),\s*(%[goli][0-7])/
1671 &unmovxtox($1,$2,$3)
1673 s/\b(mov[xw]to[ds])\s+(%[goli][0-7]),\s*(%f[0-9]{1,2})/
1674 &unmovxtox($1,$2,$3)
1676 s/\b([fb][^\s]*)\s+(%f[0-9]{1,2}),\s*(%f[0-9]{1,2}),\s*(%f[0-9]{1,2})/
1679 s/\b(umulxhi|bmask|addxc[c]{0,2}|alignaddr[l]*)\s+(%[goli][0-7]),\s*(%[goli][0-7]),\s*(%[goli][0-7])/
1680 &unvis3($1,$2,$3,$4)