Apply the AES-GCM unroll8 optimisation to Microsoft Azure Cobalt 100
authorTom Cosgrove <tom.cosgrove@arm.com>
Wed, 21 Feb 2024 09:11:20 +0000 (09:11 +0000)
committerTomas Mraz <tomas@openssl.org>
Thu, 22 Feb 2024 15:07:02 +0000 (16:07 +0100)
Performance improvements range from 18% to 32%.

Change-Id: Ifb89eeac3c0625a582a25ff07cf7f9c9ec8f5ba6

Reviewed-by: Hugo Landau <hlandau@openssl.org>
Reviewed-by: Neil Horman <nhorman@openssl.org>
Reviewed-by: Tomas Mraz <tomas@openssl.org>
(Merged from https://github.com/openssl/openssl/pull/23651)

crypto/arm_arch.h
crypto/armcap.c

index b76981f48b81f7dc200dc2983d0ee22485152b62..da999b5f6d22b37831ba134fd03696611626b37e 100644 (file)
@@ -103,6 +103,7 @@ extern unsigned int OPENSSL_armv8_rsa_neonized;
 # define ARM_CPU_IMP_ARM           0x41
 # define HISI_CPU_IMP              0x48
 # define ARM_CPU_IMP_APPLE         0x61
+# define ARM_CPU_IMP_MICROSOFT     0x6D
 
 # define ARM_CPU_PART_CORTEX_A72   0xD08
 # define ARM_CPU_PART_N1           0xD0C
@@ -124,6 +125,8 @@ extern unsigned int OPENSSL_armv8_rsa_neonized;
 # define APPLE_CPU_PART_M2_BLIZZARD_MAX     0x038
 # define APPLE_CPU_PART_M2_AVALANCHE_MAX    0x039
 
+# define MICROSOFT_CPU_PART_COBALT_100      0xD49
+
 # define MIDR_PARTNUM_SHIFT       4
 # define MIDR_PARTNUM_MASK        (0xfffU << MIDR_PARTNUM_SHIFT)
 # define MIDR_PARTNUM(midr)       \
index adb8b6a188dcbeb1b9091451f9edc150bb8821e7..bbb9f454fc623d4b0d42a0fe87ac48183bf6e2b4 100644 (file)
@@ -418,6 +418,7 @@ void OPENSSL_cpuid_setup(void)
     }
     if ((MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_V1) ||
          MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_N2) ||
+         MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_MICROSOFT, MICROSOFT_CPU_PART_COBALT_100) ||
          MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_V2)) &&
         (OPENSSL_armcap_P & ARMV8_SHA3))
         OPENSSL_armcap_P |= ARMV8_UNROLL8_EOR3;