crypto/bn/asm/ia64.S

   1 .explicit
   2 .text
   3 .asciz  "ia64.S, Version 1.0"
   4 .asciz  "IA-64 ISA artwork by Andy Polyakov <appro@fy.chalmers.se>"
   5
   6 //
   7 // ====================================================================
   8 // Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
   9 // project.
  10 //
  11 // Rights for redistribution and usage in source and binary forms are
  12 // granted according to the OpenSSL license. Warranty of any kind is
  13 // disclaimed.
  14 // ====================================================================
  15 //
  16
  17 // Q.   How much faster does it get?
  18 // A.   Here is the output from 'openssl speed rsa dsa' for vanilla
  19 //      0.9.6a compiled with gcc version 2.96 20000731 (Red Hat
  20 //      Linux 7.1 2.96-81):
  21 //
  22 //                        sign    verify    sign/s verify/s
  23 //      rsa  512 bits   0.0036s   0.0003s    275.3   2999.2
  24 //      rsa 1024 bits   0.0203s   0.0011s     49.3    894.1
  25 //      rsa 2048 bits   0.1331s   0.0040s      7.5    250.9
  26 //      rsa 4096 bits   0.9270s   0.0147s      1.1     68.1
  27 //                        sign    verify    sign/s verify/s
  28 //      dsa  512 bits   0.0035s   0.0043s    288.3    234.8
  29 //      dsa 1024 bits   0.0111s   0.0135s     90.0     74.2
  30 //
  31 //      And here is similar output but for this assembler
  32 //      implementation:-)
  33 //
  34 //                        sign    verify    sign/s verify/s
  35 //      rsa  512 bits   0.0021s   0.0001s    549.4   9638.5
  36 //      rsa 1024 bits   0.0055s   0.0002s    183.8   4481.1
  37 //      rsa 2048 bits   0.0244s   0.0006s     41.4   1726.3
  38 //      rsa 4096 bits   0.1295s   0.0018s      7.7    561.5
  39 //                        sign    verify    sign/s verify/s
  40 //      dsa  512 bits   0.0012s   0.0013s    891.9    756.6
  41 //      dsa 1024 bits   0.0023s   0.0028s    440.4    376.2
  42 //
  43 //      Yes, you may argue that it's not fair comparison as it's
  44 //      possible to craft the C implementation with BN_UMULT_HIGH
  45 //      inline assembler macro. But of course! Here is the output
  46 //      with the macro:
  47 //
  48 //                        sign    verify    sign/s verify/s
  49 //      rsa  512 bits   0.0020s   0.0002s    495.0   6561.0
  50 //      rsa 1024 bits   0.0086s   0.0004s    116.2   2235.7
  51 //      rsa 2048 bits   0.0519s   0.0015s     19.3    667.3
  52 //      rsa 4096 bits   0.3464s   0.0053s      2.9    187.7
  53 //                        sign    verify    sign/s verify/s
  54 //      dsa  512 bits   0.0016s   0.0020s    613.1    510.5
  55 //      dsa 1024 bits   0.0045s   0.0054s    221.0    183.9
  56 //
  57 //      My code is still way faster, huh:-) And I believe that even
  58 //      higher performance can be achieved. Note that as keys get
  59 //      longer, performance gain is larger. Why? According to the
  60 //      profiler there is another player in the field, namely
  61 //      BN_from_montgomery consuming larger and larger portion of CPU
  62 //      time as keysize decreases. I therefore consider putting effort
  63 //      to assembler implementation of the following routine:
  64 //
  65 //      void bn_mul_add_mont (BN_ULONG *rp,BN_ULONG *np,int nl,BN_ULONG n0)
  66 //      {
  67 //      int      i,j;
  68 //      BN_ULONG v;
  69 //
  70 //      for (i=0; i<nl; i++)
  71 //              {
  72 //              v=bn_mul_add_words(rp,np,nl,(rp[0]*n0)&BN_MASK2);
  73 //              nrp++;
  74 //              rp++;
  75 //              if (((nrp[-1]+=v)&BN_MASK2) < v)
  76 //                      for (j=0; ((++nrp[j])&BN_MASK2) == 0; j++) ;
  77 //              }
  78 //      }
  79 //
  80 //      It might as well be beneficial to implement even combaX
  81 //      variants, as it appears as it can literally unleash the
  82 //      performance (see comment section to bn_mul_comba8 below).
  83 //
  84 //      And finally for your reference the output for 0.9.6a compiled
  85 //      with SGIcc version 0.01.0-12 (keep in mind that for the moment
  86 //      of this writing it's not possible to convince SGIcc to use
  87 //      BN_UMULT_HIGH inline assembler macro, yet the code is fast,
  88 //      i.e. for a compiler generated one:-):
  89 //
  90 //                        sign    verify    sign/s verify/s
  91 //      rsa  512 bits   0.0022s   0.0002s    452.7   5894.3
  92 //      rsa 1024 bits   0.0097s   0.0005s    102.7   2002.9
  93 //      rsa 2048 bits   0.0578s   0.0017s     17.3    600.2
  94 //      rsa 4096 bits   0.3838s   0.0061s      2.6    164.5
  95 //                        sign    verify    sign/s verify/s
  96 //      dsa  512 bits   0.0018s   0.0022s    547.3    459.6
  97 //      dsa 1024 bits   0.0051s   0.0062s    196.6    161.3
  98 //
  99 //      Oh! Benchmarks were performed on 733MHz Lion-class Itanium
 100 //      system running Redhat Linux 7.1 (very special thanks to Ray
 101 //      McCaffity of Williams Communications for providing an account).
 102 //
 103 // Q.   What's the heck with 'rum 1<<5' at the end of every function?
 104 // A.   Well, by clearing the "upper FP registers written" bit of the
 105 //      User Mask I want to excuse the kernel from preserving upper
 106 //      (f32-f128) FP register bank over process context switch, thus
 107 //      minimizing bus bandwidth consumption during the switch (i.e.
 108 //      after PKI opration completes and the program is off doing
 109 //      something else like bulk symmetric encryption). Having said
 110 //      this, I also want to point out that it might be good idea
 111 //      to compile the whole toolkit (as well as majority of the
 112 //      programs for that matter) with -mfixed-range=f32-f127 command
 113 //      line option. No, it doesn't prevent the compiler from writing
 114 //      to upper bank, but at least discourages to do so. If you don't
 115 //      like the idea you have the option to compile the module with
 116 //      -Drum=nop.m in command line.
 117 //
 118
 119 #if 1
 120 //
 121 // bn_[add|sub]_words routines.
 122 //
 123 // Loops are spinning in 2*(n+5) ticks on Itanuim (provided that the
 124 // data reside in L1 cache, i.e. 2 ticks away). It's possible to
 125 // compress the epilogue and get down to 2*n+6, but at the cost of
 126 // scalability (the neat feature of this implementation is that it
 127 // shall automagically spin in n+5 on "wider" IA-64 implementations:-)
 128 // I consider that the epilogue is short enough as it is to trade tiny
 129 // performance loss on Itanium for scalability.
 130 //
 131 // BN_ULONG bn_add_words(BN_ULONG *rp, BN_ULONG *ap, BN_ULONG *bp,int num)
 132 //
 133 .global bn_add_words#
 134 .proc   bn_add_words#
 135 .align  64
 136 .space  32      // makes the loop body aligned at 64-byte boundary
 137 bn_add_words:
 138         .prologue
 139         .fframe 0
 140         .save   ar.pfs,r2
 141 { .mii  alloc           r2=ar.pfs,4,12,0,16
 142         cmp4.le         p6,p0=r35,r0    };;
 143 { .mfb  mov             r8=r0                   // return value
 144 (p6)    br.ret.spnt.many        b0      };;
 145
 146         .save   ar.lc,r3
 147 { .mib  sub             r10=r35,r0,1
 148         mov             r3=ar.lc
 149         brp.loop.imp    .L_bn_add_words_ctop,.L_bn_add_words_cend-16
 150                                         }
 151         .body
 152 { .mib  mov             r14=r32                 // rp
 153         mov             r9=pr           };;
 154 { .mii  mov             r15=r33                 // ap
 155         mov             ar.lc=r10
 156         mov             ar.ec=6         }
 157 { .mib  mov             r16=r34                 // bp
 158         mov             pr.rot=1<<16    }
 159
 160 .L_bn_add_words_ctop:   ;;
 161 { .mii  (p16)   ld8             r32=[r16],8       // b=*(bp++)
 162         (p18)   add             r39=r37,r34
 163         (p19)   cmp.ltu.unc     p56,p0=r40,r38  }
 164 { .mfb  (p0)    nop.m           0x0
 165         (p0)    nop.f           0x0
 166         (p0)    nop.b           0x0             }
 167 { .mii  (p16)   ld8             r35=[r15],8       // a=*(ap++)
 168         (p58)   cmp.eq.or       p57,p0=-1,r41     // (p20)
 169         (p58)   add             r41=1,r41       } // (p20)
 170 { .mfb  (p21)   st8             [r14]=r42,8       // *(rp++)=r
 171         (p0)    nop.f           0x0
 172         br.ctop.sptk    .L_bn_add_words_ctop    };;
 173 .L_bn_add_words_cend:
 174
 175 { .mii
 176 (p59)   add             r8=1,r8         // return value
 177         mov             pr=r9,-1
 178         mov             ar.lc=r3        }
 179 { .mbb  nop.b           0x0
 180         br.ret.sptk.many        b0      };;
 181 .endp   bn_add_words#
 182
 183 //
 184 // BN_ULONG bn_sub_words(BN_ULONG *rp, BN_ULONG *ap, BN_ULONG *bp,int num)
 185 //
 186 .global bn_sub_words#
 187 .proc   bn_sub_words#
 188 .align  64
 189 .space  32      // makes the loop body aligned at 64-byte boundary
 190 bn_sub_words:
 191         .prologue
 192         .fframe 0
 193         .save   ar.pfs,r2
 194 { .mii  alloc           r2=ar.pfs,4,12,0,16
 195         cmp4.le         p6,p0=r35,r0    };;
 196 { .mfb  mov             r8=r0                   // return value
 197 (p6)    br.ret.spnt.many        b0      };;
 198
 199         .save   ar.lc,r3
 200 { .mib  sub             r10=r35,r0,1
 201         mov             r3=ar.lc
 202         brp.loop.imp    .L_bn_sub_words_ctop,.L_bn_sub_words_cend-16
 203                                         }
 204         .body
 205 { .mib  mov             r14=r32                 // rp
 206         mov             r9=pr           };;
 207 { .mii  mov             r15=r33                 // ap
 208         mov             ar.lc=r10
 209         mov             ar.ec=6         }
 210 { .mib  mov             r16=r34                 // bp
 211         mov             pr.rot=1<<16    }
 212
 213 .L_bn_sub_words_ctop:   ;;
 214 { .mii  (p16)   ld8             r32=[r16],8       // b=*(bp++)
 215         (p18)   sub             r39=r37,r34
 216         (p19)   cmp.gtu.unc     p56,p0=r40,r38  }
 217 { .mfb  (p0)    nop.m           0x0
 218         (p0)    nop.f           0x0
 219         (p0)    nop.b           0x0             }
 220 { .mii  (p16)   ld8             r35=[r15],8       // a=*(ap++)
 221         (p58)   cmp.eq.or       p57,p0=0,r41      // (p20)
 222         (p58)   add             r41=-1,r41      } // (p20)
 223 { .mbb  (p21)   st8             [r14]=r42,8       // *(rp++)=r
 224         (p0)    nop.b           0x0
 225         br.ctop.sptk    .L_bn_sub_words_ctop    };;
 226 .L_bn_sub_words_cend:
 227
 228 { .mii
 229 (p59)   add             r8=1,r8         // return value
 230         mov             pr=r9,-1
 231         mov             ar.lc=r3        }
 232 { .mbb  nop.b           0x0
 233         br.ret.sptk.many        b0      };;
 234 .endp   bn_sub_words#
 235 #endif
 236
 237 #if 0
 238 #define XMA_TEMPTATION
 239 #endif
 240
 241 #if 1
 242 //
 243 // BN_ULONG bn_mul_words(BN_ULONG *rp, BN_ULONG *ap, int num, BN_ULONG w)
 244 //
 245 .global bn_mul_words#
 246 .proc   bn_mul_words#
 247 .align  64
 248 .space  32      // makes the loop body aligned at 64-byte boundary
 249 bn_mul_words:
 250         .prologue
 251         .fframe 0
 252         .save   ar.pfs,r2
 253 #ifdef XMA_TEMPTATION
 254 { .mfi  alloc           r2=ar.pfs,4,0,0,0       };;
 255 #else
 256 { .mfi  alloc           r2=ar.pfs,4,4,0,8       };;
 257 #endif
 258 { .mib  mov             r8=r0                   // return value
 259         cmp4.le         p6,p0=r34,r0
 260 (p6)    br.ret.spnt.many        b0              };;
 261
 262         .save   ar.lc,r3
 263 { .mii  sub     r10=r34,r0,1
 264         mov     r3=ar.lc
 265         mov     r9=pr                   };;
 266
 267         .body
 268 { .mib  setf.sig        f8=r35  // w
 269         mov             pr.rot=0x400001<<16
 270                         // ------^----- serves as (p48) at first (p26)
 271         brp.loop.imp    .L_bn_mul_words_ctop,.L_bn_mul_words_cend-16
 272                                         }
 273
 274 #ifndef XMA_TEMPTATION
 275
 276 { .mii  mov             r14=r32 // rp
 277         mov             r15=r33 // ap
 278         mov             ar.lc=r10       }
 279 { .mii  mov             r39=0   // serves as r33 at first (p26)
 280         mov             ar.ec=12        }
 281
 282 // This loop spins in 2*(n+11) ticks. It's scheduled for data in L2
 283 // cache (i.e. 9 ticks away) as floating point load/store instructions
 284 // bypass L1 cache and L2 latency is actually best-case scenario for
 285 // ldf8. The loop is not scalable and shall run in 2*(n+11) even on
 286 // "wider" IA-64 implementations. It's a trade-off here. n+22 loop
 287 // would give us ~5% in *overall* performance improvement on "wider"
 288 // IA-64, but would hurt Itanium for about same because of longer
 289 // epilogue. As it's a matter of few percents in either case I've
 290 // chosen to trade the scalability for development time (you can see
 291 // this very instruction sequence in bn_mul_add_words loop which in
 292 // turn is scalable).
 293 .L_bn_mul_words_ctop:   ;;
 294 { .mfi  (p25)   getf.sig        r36=f49                 // low
 295         (p21)   xmpy.lu         f45=f37,f8
 296         (p27)   cmp.ltu         p52,p48=r39,r38 }
 297 { .mfi  (p16)   ldf8            f32=[r15],8
 298         (p21)   xmpy.hu         f38=f37,f8
 299         (p0)    nop.i           0x0             };;
 300 { .mii  (p26)   getf.sig        r32=f43                 // high
 301         .pred.rel       "mutex",p48,p52
 302         (p48)   add             r38=r37,r33             // (p26)
 303         (p52)   add             r38=r37,r33,1   }       // (p26)
 304 { .mfb  (p27)   st8             [r14]=r39,8
 305         (p0)    nop.f           0x0
 306         br.ctop.sptk    .L_bn_mul_words_ctop    };;
 307 .L_bn_mul_words_cend:
 308
 309 { .mii  nop.m           0x0
 310 .pred.rel       "mutex",p49,p53
 311 (p49)   add             r8=r34,r0
 312 (p53)   add             r8=r34,r0,1     }
 313 { .mfb  nop.m   0x0
 314         nop.f   0x0
 315         nop.b   0x0                     }
 316
 317 #else   // XMA_TEMPTATION
 318
 319         setf.sig        f37=r0  // serves as carry at (p18) tick
 320         mov             ar.lc=r10
 321         mov             ar.ec=5
 322
 323 // Most of you examining this code very likely wonder why in the name
 324 // of Intel the following loop is commented out? Indeed, it looks so
 325 // neat that you find it hard to believe that it's something wrong
 326 // with it, right? The catch is that every iteration depends on the
 327 // result from previous one and the latter isn't available instantly.
 328 // The loop therefore spins at the latency of xma minus 1, or in other
 329 // words at 6*(n+4) ticks:-( Compare to the "production" loop above
 330 // that runs in 2*(n+11) where the low latency problem is worked around
 331 // by moving the dependency to one-tick latent interger ALU. Note that
 332 // "distance" between ldf8 and xma is not latency of ldf8, but the
 333 // *difference* between xma and ldf8 latencies.
 334 .L_bn_mul_words_ctop:   ;;
 335 { .mfi  (p16)   ldf8            f32=[r33],8
 336         (p18)   xma.hu          f38=f34,f8,f39  }
 337 { .mfb  (p20)   stf8            [r32]=f37,8
 338         (p18)   xma.lu          f35=f34,f8,f39
 339         br.ctop.sptk    .L_bn_mul_words_ctop    };;
 340 .L_bn_mul_words_cend:
 341
 342         getf.sig        r8=f41          // the return value
 343
 344 #endif  // XMA_TEMPTATION
 345
 346 { .mii  nop.m           0x0
 347         mov             pr=r9,-1
 348         mov             ar.lc=r3        }
 349 { .mfb  rum             1<<5            // clear um.mfh
 350         nop.f           0x0
 351         br.ret.sptk.many        b0      };;
 352 .endp   bn_mul_words#
 353 #endif
 354
 355 #if 1
 356 //
 357 // BN_ULONG bn_mul_add_words(BN_ULONG *rp, BN_ULONG *ap, int num, BN_ULONG w)
 358 //
 359 .global bn_mul_add_words#
 360 .proc   bn_mul_add_words#
 361 .align  64
 362 //.space        0       // makes the loop split at 64-byte boundary
 363 bn_mul_add_words:
 364         .prologue
 365         .fframe 0
 366         .save   ar.pfs,r2
 367 { .mii  alloc           r2=ar.pfs,4,12,0,16
 368         cmp4.le         p6,p0=r34,r0    };;
 369 { .mfb  mov             r8=r0                   // return value
 370 (p6)    br.ret.spnt.many        b0      };;
 371
 372         .save   ar.lc,r3
 373 { .mii  sub     r10=r34,r0,1
 374         mov     r3=ar.lc
 375         mov     r9=pr                   };;
 376
 377         .body
 378 { .mib  setf.sig        f8=r35  // w
 379         mov             pr.rot=0x400001<<16
 380                         // ------^----- serves as (p48) at first (p26)
 381         brp.loop.imp    .L_bn_mul_add_words_ctop,.L_bn_mul_add_words_cend-16
 382                                         }
 383 { .mii  mov             r14=r32 // rp
 384         mov             r15=r33 // ap
 385         mov             ar.lc=r10       }
 386 { .mii  mov             r39=0   // serves as r33 at first (p26)
 387         mov             r18=r32 // rp copy
 388         mov             ar.ec=14        }
 389
 390 // This loop spins in 3*(n+13) ticks on Itanium and should spin in
 391 // 2*(n+13) on "wider" IA-64 implementations (to be verified with new
 392 // µ-architecture manuals as they become available). As usual it's
 393 // possible to compress the epilogue, down to 10 in this case, at the
 394 // cost of scalability. Compressed (and therefore non-scalable) loop
 395 // running at 3*(n+10) would buy you ~10% on Itanium but take ~35%
 396 // from "wider" IA-64 so let it be scalable! Special attention was
 397 // paid for having the loop body split at 64-byte boundary. ld8 is
 398 // scheduled for L1 cache as the data is more than likely there.
 399 // Indeed, bn_mul_words has put it there a moment ago:-)
 400 .L_bn_mul_add_words_ctop:       ;;
 401 { .mfi  (p25)   getf.sig        r36=f49                 // low
 402         (p21)   xmpy.lu         f45=f37,f8
 403         (p27)   cmp.ltu         p52,p48=r39,r38 }
 404 { .mfi  (p16)   ldf8            f32=[r15],8
 405         (p21)   xmpy.hu         f38=f37,f8
 406         (p27)   add             r43=r43,r39     };;
 407 { .mii  (p26)   getf.sig        r32=f43                 // high
 408         .pred.rel       "mutex",p48,p52
 409         (p48)   add             r38=r37,r33             // (p26)
 410         (p52)   add             r38=r37,r33,1   }       // (p26)
 411 { .mfb  (p27)   cmp.ltu.unc     p56,p0=r43,r39
 412         (p0)    nop.f           0x0
 413         (p0)    nop.b           0x0             }
 414 { .mii  (p26)   ld8             r42=[r18],8
 415         (p58)   cmp.eq.or       p57,p0=-1,r44
 416         (p58)   add             r44=1,r44       }
 417 { .mfb  (p29)   st8             [r14]=r45,8
 418         (p0)    nop.f           0x0
 419         br.ctop.sptk    .L_bn_mul_add_words_ctop};;
 420 .L_bn_mul_add_words_cend:
 421
 422 { .mii  nop.m           0x0
 423 .pred.rel       "mutex",p51,p55
 424 (p51)   add             r8=r36,r0
 425 (p55)   add             r8=r36,r0,1     }
 426 { .mfb  nop.m   0x0
 427         nop.f   0x0
 428         nop.b   0x0                     };;
 429 { .mii
 430 (p59)   add             r8=1,r8
 431         mov             pr=r9,-1
 432         mov             ar.lc=r3        }
 433 { .mfb  rum             1<<5            // clear um.mfh
 434         nop.f           0x0
 435         br.ret.sptk.many        b0      };;
 436 .endp   bn_mul_add_words#
 437 #endif
 438
 439 #if 1
 440 //
 441 // void bn_sqr_words(BN_ULONG *rp, BN_ULONG *ap, int num)
 442 //
 443 .global bn_sqr_words#
 444 .proc   bn_sqr_words#
 445 .align  64
 446 .space  32      // makes the loop body aligned at 64-byte boundary
 447 bn_sqr_words:
 448         .prologue
 449         .fframe 0
 450         .save   ar.pfs,r2
 451 { .mii  alloc           r2=ar.pfs,3,0,0,0
 452         sxt4            r34=r34         };;
 453 { .mii  cmp.le          p6,p0=r34,r0
 454         mov             r8=r0           }       // return value
 455 { .mfb  nop.f           0x0
 456 (p6)    br.ret.spnt.many        b0      };;
 457
 458         .save   ar.lc,r3
 459 { .mii  sub     r10=r34,r0,1
 460         mov     r3=ar.lc
 461         mov     r9=pr                   };;
 462
 463         .body
 464 { .mib
 465         mov             pr.rot=1<<16
 466         brp.loop.imp    .L_bn_sqr_words_ctop,.L_bn_sqr_words_cend-16
 467                                         }
 468 { .mii  add             r34=8,r32
 469         mov             ar.lc=r10
 470         mov             ar.ec=18        }
 471
 472 // 2*(n+17) on Itanium, (n+17) on "wider" IA-64 implementations. It's
 473 // possible to compress the epilogue (I'm getting tired to write this
 474 // comment over and over) and get down to 2*n+16 at the cost of
 475 // scalability. The decision will very likely be reconsidered after the
 476 // benchmark program is profiled. I.e. if perfomance gain on Itanium
 477 // will appear larger than loss on "wider" IA-64, then the loop should
 478 // be explicitely split and the epilogue compressed.
 479 .L_bn_sqr_words_ctop:   ;;
 480 { .mfi  (p16)   ldf8            f32=[r33],8
 481         (p25)   xmpy.lu         f42=f41,f41
 482         (p0)    nop.i           0x0             }
 483 { .mib  (p33)   stf8            [r32]=f50,16
 484         (p0)    nop.i           0x0
 485         (p0)    nop.b           0x0             }
 486 { .mfi  (p0)    nop.m           0x0
 487         (p25)   xmpy.hu         f52=f41,f41
 488         (p0)    nop.i           0x0             }
 489 { .mib  (p33)   stf8            [r34]=f60,16
 490         (p0)    nop.i           0x0
 491         br.ctop.sptk    .L_bn_sqr_words_ctop    };;
 492 .L_bn_sqr_words_cend:
 493
 494 { .mii  nop.m           0x0
 495         mov             pr=r9,-1
 496         mov             ar.lc=r3        }
 497 { .mfb  rum             1<<5            // clear um.mfh
 498         nop.f           0x0
 499         br.ret.sptk.many        b0      };;
 500 .endp   bn_sqr_words#
 501 #endif
 502
 503 #if 1
 504 // Apparently we win nothing by implementing special bn_sqr_comba8.
 505 // Yes, it is possible to reduce the number of multiplications by
 506 // almost factor of two, but then the amount of additions would
 507 // increase by factor of two (as we would have to perform those
 508 // otherwise performed by xma ourselves). Normally we would trade
 509 // anyway as multiplications are way more expensive, but not this
 510 // time... Multiplication kernel is fully pipelined and as we drain
 511 // one 128-bit multiplication result per clock cycle multiplications
 512 // are effectively as inexpensive as additions. Special implementation
 513 // might become of interest for "wider" IA-64 implementation as you'll
 514 // be able to get through the multiplication phase faster (there won't
 515 // be any stall issues as discussed in the commentary section below and
 516 // you therefore will be able to employ all 4 FP units)... But these
 517 // Itanium days it's simply too hard to justify the effort so I just
 518 // drop down to bn_mul_comba8 code:-)
 519 //
 520 // void bn_sqr_comba8(BN_ULONG *r, BN_ULONG *a)
 521 //
 522 .global bn_sqr_comba8#
 523 .proc   bn_sqr_comba8#
 524 .align  64
 525 bn_sqr_comba8:
 526         .prologue
 527         .fframe 0
 528         .save   ar.pfs,r2
 529 { .mii  alloc   r2=ar.pfs,2,1,0,0
 530         mov     r34=r33
 531         add     r14=8,r33               };;
 532         .body
 533 { .mii  add     r17=8,r34
 534         add     r15=16,r33
 535         add     r18=16,r34              }
 536 { .mfb  add     r16=24,r33
 537         br      .L_cheat_entry_point8   };;
 538 #endif
 539
 540 #if 1
 541 // I've estimated this routine to run in ~120 ticks, but in reality
 542 // (i.e. according to ar.itc) it takes ~160 ticks. Are those extra
 543 // cycles consumed for instructions fetch? Or did I misinterpret some
 544 // clause in Itanium µ-architecture manual? Comments are welcomed and
 545 // highly appreciated.
 546 //
 547 // However! It should be noted that even 160 ticks is darn good result
 548 // as it's over 10 (yes, ten, spelled as t-e-n) times faster than the
 549 // C version (compiled with gcc with inline assembler). I really
 550 // kicked compiler's butt here, didn't I? Yeah! This brings us to the
 551 // following statement. It's damn shame that this routine isn't called
 552 // very often nowadays! According to the profiler most CPU time is
 553 // consumed by bn_mul_add_words called from BN_from_montgomery. In
 554 // order to estimate what we're missing, I've compared the performance
 555 // of this routine against "traditional" implementation, i.e. against
 556 // following routine:
 557 //
 558 // void bn_mul_comba8(BN_ULONG *r, BN_ULONG *a, BN_ULONG *b)
 559 // {    r[ 8]=bn_mul_words(    &(r[0]),a,8,b[0]);
 560 //      r[ 9]=bn_mul_add_words(&(r[1]),a,8,b[1]);
 561 //      r[10]=bn_mul_add_words(&(r[2]),a,8,b[2]);
 562 //      r[11]=bn_mul_add_words(&(r[3]),a,8,b[3]);
 563 //      r[12]=bn_mul_add_words(&(r[4]),a,8,b[4]);
 564 //      r[13]=bn_mul_add_words(&(r[5]),a,8,b[5]);
 565 //      r[14]=bn_mul_add_words(&(r[6]),a,8,b[6]);
 566 //      r[15]=bn_mul_add_words(&(r[7]),a,8,b[7]);
 567 // }
 568 //
 569 // The one below is over 8 times faster than the one above:-( Even
 570 // more reasons to "combafy" bn_mul_add_mont...
 571 //
 572 // And yes, this routine really made me wish there were an optimizing
 573 // assembler! It also feels like it deserves a dedication.
 574 //
 575 //      To my wife for being there and to my kids...
 576 //
 577 // void bn_mul_comba8(BN_ULONG *r, BN_ULONG *a, BN_ULONG *b)
 578 //
 579 #define carry1  r14
 580 #define carry2  r15
 581 #define carry3  r34
 582 .global bn_mul_comba8#
 583 .proc   bn_mul_comba8#
 584 .align  64
 585 bn_mul_comba8:
 586         .prologue
 587         .fframe 0
 588         .save   ar.pfs,r2
 589 { .mii  alloc   r2=ar.pfs,3,0,0,0
 590         add     r14=8,r33
 591         add     r17=8,r34               }
 592         .body
 593 { .mii  add     r15=16,r33
 594         add     r18=16,r34
 595         add     r16=24,r33              };;
 596 .L_cheat_entry_point8:
 597 { .mmi  add     r19=24,r34
 598
 599         ldf8    f32=[r33],32            }
 600
 601 { .mmi  ldf8    f120=[r34],32
 602         ldf8    f121=[r17],32           };;
 603 { .mmi  ldf8    f122=[r18],32
 604         ldf8    f123=[r19],32           }
 605 { .mmi  ldf8    f124=[r34]
 606         ldf8    f125=[r17]              }
 607 { .mmi  ldf8    f126=[r18]
 608         ldf8    f127=[r19]              }
 609
 610 { .mmi  ldf8    f33=[r14],32
 611         ldf8    f34=[r15],32            }
 612 { .mmi  ldf8    f35=[r16],32
 613         ldf8    f36=[r33]               }
 614 { .mmi  ldf8    f37=[r14]
 615         ldf8    f38=[r15]               }
 616 { .mfi  ldf8    f39=[r16]
 617 // -------\ Entering multiplier's heaven /-------
 618 // ------------\                    /------------
 619 // -----------------\          /-----------------
 620 // ----------------------\/----------------------
 621                 xma.hu  f41=f32,f120,f0         }
 622 { .mfi          xma.lu  f40=f32,f120,f0         };; // (*)
 623 { .mfi          xma.hu  f51=f32,f121,f0         }
 624 { .mfi          xma.lu  f50=f32,f121,f0         };;
 625 { .mfi          xma.hu  f61=f32,f122,f0         }
 626 { .mfi          xma.lu  f60=f32,f122,f0         };;
 627 { .mfi          xma.hu  f71=f32,f123,f0         }
 628 { .mfi          xma.lu  f70=f32,f123,f0         };;
 629 { .mfi          xma.hu  f81=f32,f124,f0         }
 630 { .mfi          xma.lu  f80=f32,f124,f0         };;
 631 { .mfi          xma.hu  f91=f32,f125,f0         }
 632 { .mfi          xma.lu  f90=f32,f125,f0         };;
 633 { .mfi          xma.hu  f101=f32,f126,f0        }
 634 { .mfi          xma.lu  f100=f32,f126,f0        };;
 635 { .mfi          xma.hu  f111=f32,f127,f0        }
 636 { .mfi          xma.lu  f110=f32,f127,f0        };;;;
 637 // (*)  You can argue that splitting at every second bundle would
 638 //      prevent "wider" IA-64 implementations from achieving the peak
 639 //      performance. Well, not really... The catch is that if you
 640 //      intend to keep 4 FP units busy by splitting at every fourth
 641 //      bundle and thus perform these 16 multiplications in 4 ticks,
 642 //      the first bundle *below* would stall because the result from
 643 //      the first xma bundle *above* won't be available for another 3
 644 //      ticks (if not more, being an optimist, I assume that "wider"
 645 //      implementation will have same latency:-). This stall will hold
 646 //      you back and the performance would be as if every second bundle
 647 //      were split *anyway*...
 648 { .mfi  getf.sig        r16=f40
 649                 xma.hu  f42=f33,f120,f41
 650         add             r33=8,r32               }
 651 { .mfi          xma.lu  f41=f33,f120,f41        };;
 652 { .mfi  getf.sig        r24=f50
 653                 xma.hu  f52=f33,f121,f51        }
 654 { .mfi          xma.lu  f51=f33,f121,f51        };;
 655 { .mfi  st8             [r32]=r16,16
 656                 xma.hu  f62=f33,f122,f61        }
 657 { .mfi          xma.lu  f61=f33,f122,f61        };;
 658 { .mfi          xma.hu  f72=f33,f123,f71        }
 659 { .mfi          xma.lu  f71=f33,f123,f71        };;
 660 { .mfi          xma.hu  f82=f33,f124,f81        }
 661 { .mfi          xma.lu  f81=f33,f124,f81        };;
 662 { .mfi          xma.hu  f92=f33,f125,f91        }
 663 { .mfi          xma.lu  f91=f33,f125,f91        };;
 664 { .mfi          xma.hu  f102=f33,f126,f101      }
 665 { .mfi          xma.lu  f101=f33,f126,f101      };;
 666 { .mfi          xma.hu  f112=f33,f127,f111      }
 667 { .mfi          xma.lu  f111=f33,f127,f111      };;;;
 668 //-------------------------------------------------//
 669 { .mfi  getf.sig        r25=f41
 670                 xma.hu  f43=f34,f120,f42        }
 671 { .mfi          xma.lu  f42=f34,f120,f42        };;
 672 { .mfi  getf.sig        r16=f60
 673                 xma.hu  f53=f34,f121,f52        }
 674 { .mfi          xma.lu  f52=f34,f121,f52        };;
 675 { .mfi  getf.sig        r17=f51
 676                 xma.hu  f63=f34,f122,f62
 677         add             r25=r25,r24             }
 678 { .mfi          xma.lu  f62=f34,f122,f62
 679         mov             carry1=0                };;
 680 { .mfi  cmp.ltu         p6,p0=r25,r24
 681                 xma.hu  f73=f34,f123,f72        }
 682 { .mfi          xma.lu  f72=f34,f123,f72        };;
 683 { .mfi  st8             [r33]=r25,16
 684                 xma.hu  f83=f34,f124,f82
 685 (p6)    add             carry1=1,carry1         }
 686 { .mfi          xma.lu  f82=f34,f124,f82        };;
 687 { .mfi          xma.hu  f93=f34,f125,f92        }
 688 { .mfi          xma.lu  f92=f34,f125,f92        };;
 689 { .mfi          xma.hu  f103=f34,f126,f102      }
 690 { .mfi          xma.lu  f102=f34,f126,f102      };;
 691 { .mfi          xma.hu  f113=f34,f127,f112      }
 692 { .mfi          xma.lu  f112=f34,f127,f112      };;;;
 693 //-------------------------------------------------//
 694 { .mfi  getf.sig        r18=f42
 695                 xma.hu  f44=f35,f120,f43
 696         add             r17=r17,r16             }
 697 { .mfi          xma.lu  f43=f35,f120,f43        };;
 698 { .mfi  getf.sig        r24=f70
 699                 xma.hu  f54=f35,f121,f53        }
 700 { .mfi  mov             carry2=0
 701                 xma.lu  f53=f35,f121,f53        };;
 702 { .mfi  getf.sig        r25=f61
 703                 xma.hu  f64=f35,f122,f63
 704         cmp.ltu         p7,p0=r17,r16           }
 705 { .mfi  add             r18=r18,r17
 706                 xma.lu  f63=f35,f122,f63        };;
 707 { .mfi  getf.sig        r26=f52
 708                 xma.hu  f74=f35,f123,f73
 709 (p7)    add             carry2=1,carry2         }
 710 { .mfi  cmp.ltu         p7,p0=r18,r17
 711                 xma.lu  f73=f35,f123,f73
 712         add             r18=r18,carry1          };;
 713 { .mfi
 714                 xma.hu  f84=f35,f124,f83
 715 (p7)    add             carry2=1,carry2         }
 716 { .mfi  cmp.ltu         p7,p0=r18,carry1
 717                 xma.lu  f83=f35,f124,f83        };;
 718 { .mfi  st8             [r32]=r18,16
 719                 xma.hu  f94=f35,f125,f93
 720 (p7)    add             carry2=1,carry2         }
 721 { .mfi          xma.lu  f93=f35,f125,f93        };;
 722 { .mfi          xma.hu  f104=f35,f126,f103      }
 723 { .mfi          xma.lu  f103=f35,f126,f103      };;
 724 { .mfi          xma.hu  f114=f35,f127,f113      }
 725 { .mfi  mov             carry1=0
 726                 xma.lu  f113=f35,f127,f113
 727         add             r25=r25,r24             };;;;
 728 //-------------------------------------------------//
 729 { .mfi  getf.sig        r27=f43
 730                 xma.hu  f45=f36,f120,f44
 731         cmp.ltu         p6,p0=r25,r24           }
 732 { .mfi          xma.lu  f44=f36,f120,f44
 733         add             r26=r26,r25             };;
 734 { .mfi  getf.sig        r16=f80
 735                 xma.hu  f55=f36,f121,f54
 736 (p6)    add             carry1=1,carry1         }
 737 { .mfi          xma.lu  f54=f36,f121,f54        };;
 738 { .mfi  getf.sig        r17=f71
 739                 xma.hu  f65=f36,f122,f64
 740         cmp.ltu         p6,p0=r26,r25           }
 741 { .mfi          xma.lu  f64=f36,f122,f64
 742         add             r27=r27,r26             };;
 743 { .mfi  getf.sig        r18=f62
 744                 xma.hu  f75=f36,f123,f74
 745 (p6)    add             carry1=1,carry1         }
 746 { .mfi  cmp.ltu         p6,p0=r27,r26
 747                 xma.lu  f74=f36,f123,f74
 748         add             r27=r27,carry2          };;
 749 { .mfi  getf.sig        r19=f53
 750                 xma.hu  f85=f36,f124,f84
 751 (p6)    add             carry1=1,carry1         }
 752 { .mfi          xma.lu  f84=f36,f124,f84
 753         cmp.ltu         p6,p0=r27,carry2        };;
 754 { .mfi  st8             [r33]=r27,16
 755                 xma.hu  f95=f36,f125,f94
 756 (p6)    add             carry1=1,carry1         }
 757 { .mfi          xma.lu  f94=f36,f125,f94        };;
 758 { .mfi          xma.hu  f105=f36,f126,f104      }
 759 { .mfi  mov             carry2=0
 760                 xma.lu  f104=f36,f126,f104
 761         add             r17=r17,r16             };;
 762 { .mfi          xma.hu  f115=f36,f127,f114
 763         cmp.ltu         p7,p0=r17,r16           }
 764 { .mfi          xma.lu  f114=f36,f127,f114
 765         add             r18=r18,r17             };;;;
 766 //-------------------------------------------------//
 767 { .mfi  getf.sig        r20=f44
 768                 xma.hu  f46=f37,f120,f45
 769 (p7)    add             carry2=1,carry2         }
 770 { .mfi  cmp.ltu         p7,p0=r18,r17
 771                 xma.lu  f45=f37,f120,f45
 772         add             r19=r19,r18             };;
 773 { .mfi  getf.sig        r24=f90
 774                 xma.hu  f56=f37,f121,f55        }
 775 { .mfi          xma.lu  f55=f37,f121,f55        };;
 776 { .mfi  getf.sig        r25=f81
 777                 xma.hu  f66=f37,f122,f65
 778 (p7)    add             carry2=1,carry2         }
 779 { .mfi  cmp.ltu         p7,p0=r19,r18
 780                 xma.lu  f65=f37,f122,f65
 781         add             r20=r20,r19             };;
 782 { .mfi  getf.sig        r26=f72
 783                 xma.hu  f76=f37,f123,f75
 784 (p7)    add             carry2=1,carry2         }
 785 { .mfi  cmp.ltu         p7,p0=r20,r19
 786                 xma.lu  f75=f37,f123,f75
 787         add             r20=r20,carry1          };;
 788 { .mfi  getf.sig        r27=f63
 789                 xma.hu  f86=f37,f124,f85
 790 (p7)    add             carry2=1,carry2         }
 791 { .mfi          xma.lu  f85=f37,f124,f85
 792         cmp.ltu         p7,p0=r20,carry1        };;
 793 { .mfi  getf.sig        r28=f54
 794                 xma.hu  f96=f37,f125,f95
 795 (p7)    add             carry2=1,carry2         }
 796 { .mfi  st8             [r32]=r20,16
 797                 xma.lu  f95=f37,f125,f95        };;
 798 { .mfi          xma.hu  f106=f37,f126,f105      }
 799 { .mfi  mov             carry1=0
 800                 xma.lu  f105=f37,f126,f105
 801         add             r25=r25,r24             };;
 802 { .mfi          xma.hu  f116=f37,f127,f115
 803         cmp.ltu         p6,p0=r25,r24           }
 804 { .mfi          xma.lu  f115=f37,f127,f115
 805         add             r26=r26,r25             };;;;
 806 //-------------------------------------------------//
 807 { .mfi  getf.sig        r29=f45
 808                 xma.hu  f47=f38,f120,f46
 809 (p6)    add             carry1=1,carry1         }
 810 { .mfi  cmp.ltu         p6,p0=r26,r25
 811                 xma.lu  f46=f38,f120,f46
 812         add             r27=r27,r26             };;
 813 { .mfi  getf.sig        r16=f100
 814                 xma.hu  f57=f38,f121,f56
 815 (p6)    add             carry1=1,carry1         }
 816 { .mfi  cmp.ltu         p6,p0=r27,r26
 817                 xma.lu  f56=f38,f121,f56
 818         add             r28=r28,r27             };;
 819 { .mfi  getf.sig        r17=f91
 820                 xma.hu  f67=f38,f122,f66
 821 (p6)    add             carry1=1,carry1         }
 822 { .mfi  cmp.ltu         p6,p0=r28,r27
 823                 xma.lu  f66=f38,f122,f66
 824         add             r29=r29,r28             };;
 825 { .mfi  getf.sig        r18=f82
 826                 xma.hu  f77=f38,f123,f76
 827 (p6)    add             carry1=1,carry1         }
 828 { .mfi  cmp.ltu         p6,p0=r29,r28
 829                 xma.lu  f76=f38,f123,f76
 830         add             r29=r29,carry2          };;
 831 { .mfi  getf.sig        r19=f73
 832                 xma.hu  f87=f38,f124,f86
 833 (p6)    add             carry1=1,carry1         }
 834 { .mfi          xma.lu  f86=f38,f124,f86
 835         cmp.ltu         p6,p0=r29,carry2        };;
 836 { .mfi  getf.sig        r20=f64
 837                 xma.hu  f97=f38,f125,f96
 838 (p6)    add             carry1=1,carry1         }
 839 { .mfi  st8             [r33]=r29,16
 840                 xma.lu  f96=f38,f125,f96        };;
 841 { .mfi  getf.sig        r21=f55
 842                 xma.hu  f107=f38,f126,f106      }
 843 { .mfi  mov             carry2=0
 844                 xma.lu  f106=f38,f126,f106
 845         add             r17=r17,r16             };;
 846 { .mfi          xma.hu  f117=f38,f127,f116
 847         cmp.ltu         p7,p0=r17,r16           }
 848 { .mfi          xma.lu  f116=f38,f127,f116
 849         add             r18=r18,r17             };;;;
 850 //-------------------------------------------------//
 851 { .mfi  getf.sig        r22=f46
 852                 xma.hu  f48=f39,f120,f47
 853 (p7)    add             carry2=1,carry2         }
 854 { .mfi  cmp.ltu         p7,p0=r18,r17
 855                 xma.lu  f47=f39,f120,f47
 856         add             r19=r19,r18             };;
 857 { .mfi  getf.sig        r24=f110
 858                 xma.hu  f58=f39,f121,f57
 859 (p7)    add             carry2=1,carry2         }
 860 { .mfi  cmp.ltu         p7,p0=r19,r18
 861                 xma.lu  f57=f39,f121,f57
 862         add             r20=r20,r19             };;
 863 { .mfi  getf.sig        r25=f101
 864                 xma.hu  f68=f39,f122,f67
 865 (p7)    add             carry2=1,carry2         }
 866 { .mfi  cmp.ltu         p7,p0=r20,r19
 867                 xma.lu  f67=f39,f122,f67
 868         add             r21=r21,r20             };;
 869 { .mfi  getf.sig        r26=f92
 870                 xma.hu  f78=f39,f123,f77
 871 (p7)    add             carry2=1,carry2         }
 872 { .mfi  cmp.ltu         p7,p0=r21,r20
 873                 xma.lu  f77=f39,f123,f77
 874         add             r22=r22,r21             };;
 875 { .mfi  getf.sig        r27=f83
 876                 xma.hu  f88=f39,f124,f87
 877 (p7)    add             carry2=1,carry2         }
 878 { .mfi  cmp.ltu         p7,p0=r22,r21
 879                 xma.lu  f87=f39,f124,f87
 880         add             r22=r22,carry1          };;
 881 { .mfi  getf.sig        r28=f74
 882                 xma.hu  f98=f39,f125,f97
 883 (p7)    add             carry2=1,carry2         }
 884 { .mfi          xma.lu  f97=f39,f125,f97
 885         cmp.ltu         p7,p0=r22,carry1        };;
 886 { .mfi  getf.sig        r29=f65
 887                 xma.hu  f108=f39,f126,f107
 888 (p7)    add             carry2=1,carry2         }
 889 { .mfi  st8             [r32]=r22,16
 890                 xma.lu  f107=f39,f126,f107      };;
 891 { .mfi  getf.sig        r30=f56
 892                 xma.hu  f118=f39,f127,f117      }
 893 { .mfi          xma.lu  f117=f39,f127,f117      };;;;
 894 //-------------------------------------------------//
 895 // Leaving muliplier's heaven... Quite a ride, huh?
 896
 897 { .mii  getf.sig        r31=f47
 898         add             r25=r25,r24
 899         mov             carry1=0                };;
 900 { .mii          getf.sig        r16=f111
 901         cmp.ltu         p6,p0=r25,r24
 902         add             r26=r26,r25             };;
 903 { .mfb          getf.sig        r17=f102        }
 904 { .mii
 905 (p6)    add             carry1=1,carry1
 906         cmp.ltu         p6,p0=r26,r25
 907         add             r27=r27,r26             };;
 908 { .mfb  nop.m   0x0                             }
 909 { .mii
 910 (p6)    add             carry1=1,carry1
 911         cmp.ltu         p6,p0=r27,r26
 912         add             r28=r28,r27             };;
 913 { .mii          getf.sig        r18=f93
 914                 add             r17=r17,r16
 915                 mov             carry3=0        }
 916 { .mii
 917 (p6)    add             carry1=1,carry1
 918         cmp.ltu         p6,p0=r28,r27
 919         add             r29=r29,r28             };;
 920 { .mii          getf.sig        r19=f84
 921                 cmp.ltu         p7,p0=r17,r16   }
 922 { .mii
 923 (p6)    add             carry1=1,carry1
 924         cmp.ltu         p6,p0=r29,r28
 925         add             r30=r30,r29             };;
 926 { .mii          getf.sig        r20=f75
 927                 add             r18=r18,r17     }
 928 { .mii
 929 (p6)    add             carry1=1,carry1
 930         cmp.ltu         p6,p0=r30,r29
 931         add             r31=r31,r30             };;
 932 { .mfb          getf.sig        r21=f66         }
 933 { .mii  (p7)    add             carry3=1,carry3
 934                 cmp.ltu         p7,p0=r18,r17
 935                 add             r19=r19,r18     }
 936 { .mfb  nop.m   0x0                             }
 937 { .mii
 938 (p6)    add             carry1=1,carry1
 939         cmp.ltu         p6,p0=r31,r30
 940         add             r31=r31,carry2          };;
 941 { .mfb          getf.sig        r22=f57         }
 942 { .mii  (p7)    add             carry3=1,carry3
 943                 cmp.ltu         p7,p0=r19,r18
 944                 add             r20=r20,r19     }
 945 { .mfb  nop.m   0x0                             }
 946 { .mii
 947 (p6)    add             carry1=1,carry1
 948         cmp.ltu         p6,p0=r31,carry2        };;
 949 { .mfb          getf.sig        r23=f48         }
 950 { .mii  (p7)    add             carry3=1,carry3
 951                 cmp.ltu         p7,p0=r20,r19
 952                 add             r21=r21,r20     }
 953 { .mii
 954 (p6)    add             carry1=1,carry1         }
 955 { .mfb  st8             [r33]=r31,16            };;
 956
 957 { .mfb  getf.sig        r24=f112                }
 958 { .mii  (p7)    add             carry3=1,carry3
 959                 cmp.ltu         p7,p0=r21,r20
 960                 add             r22=r22,r21     };;
 961 { .mfb  getf.sig        r25=f103                }
 962 { .mii  (p7)    add             carry3=1,carry3
 963                 cmp.ltu         p7,p0=r22,r21
 964                 add             r23=r23,r22     };;
 965 { .mfb  getf.sig        r26=f94                 }
 966 { .mii  (p7)    add             carry3=1,carry3
 967                 cmp.ltu         p7,p0=r23,r22
 968                 add             r23=r23,carry1  };;
 969 { .mfb  getf.sig        r27=f85                 }
 970 { .mii  (p7)    add             carry3=1,carry3
 971                 cmp.ltu         p7,p8=r23,carry1};;
 972 { .mii  getf.sig        r28=f76
 973         add             r25=r25,r24
 974         mov             carry1=0                }
 975 { .mii          st8             [r32]=r23,16
 976         (p7)    add             carry2=1,carry3
 977         (p8)    add             carry2=0,carry3 };;
 978
 979 { .mfb  nop.m   0x0                             }
 980 { .mii  getf.sig        r29=f67
 981         cmp.ltu         p6,p0=r25,r24
 982         add             r26=r26,r25             };;
 983 { .mfb  getf.sig        r30=f58                 }
 984 { .mii
 985 (p6)    add             carry1=1,carry1
 986         cmp.ltu         p6,p0=r26,r25
 987         add             r27=r27,r26             };;
 988 { .mfb          getf.sig        r16=f113        }
 989 { .mii
 990 (p6)    add             carry1=1,carry1
 991         cmp.ltu         p6,p0=r27,r26
 992         add             r28=r28,r27             };;
 993 { .mfb          getf.sig        r17=f104        }
 994 { .mii
 995 (p6)    add             carry1=1,carry1
 996         cmp.ltu         p6,p0=r28,r27
 997         add             r29=r29,r28             };;
 998 { .mfb          getf.sig        r18=f95         }
 999 { .mii
1000 (p6)    add             carry1=1,carry1
1001         cmp.ltu         p6,p0=r29,r28
1002         add             r30=r30,r29             };;
1003 { .mii          getf.sig        r19=f86
1004                 add             r17=r17,r16
1005                 mov             carry3=0        }
1006 { .mii
1007 (p6)    add             carry1=1,carry1
1008         cmp.ltu         p6,p0=r30,r29
1009         add             r30=r30,carry2          };;
1010 { .mii          getf.sig        r20=f77
1011                 cmp.ltu         p7,p0=r17,r16
1012                 add             r18=r18,r17     }
1013 { .mii
1014 (p6)    add             carry1=1,carry1
1015         cmp.ltu         p6,p0=r30,carry2        };;
1016 { .mfb          getf.sig        r21=f68         }
1017 { .mii  st8             [r33]=r30,16
1018 (p6)    add             carry1=1,carry1         };;
1019
1020 { .mfb  getf.sig        r24=f114                }
1021 { .mii  (p7)    add             carry3=1,carry3
1022                 cmp.ltu         p7,p0=r18,r17
1023                 add             r19=r19,r18     };;
1024 { .mfb  getf.sig        r25=f105                }
1025 { .mii  (p7)    add             carry3=1,carry3
1026                 cmp.ltu         p7,p0=r19,r18
1027                 add             r20=r20,r19     };;
1028 { .mfb  getf.sig        r26=f96                 }
1029 { .mii  (p7)    add             carry3=1,carry3
1030                 cmp.ltu         p7,p0=r20,r19
1031                 add             r21=r21,r20     };;
1032 { .mfb  getf.sig        r27=f87                 }
1033 { .mii  (p7)    add             carry3=1,carry3
1034                 cmp.ltu         p7,p0=r21,r20
1035                 add             r21=r21,carry1  };;
1036 { .mib  getf.sig        r28=f78
1037         add             r25=r25,r24             }
1038 { .mib  (p7)    add             carry3=1,carry3
1039                 cmp.ltu         p7,p8=r21,carry1};;
1040 { .mii          st8             [r32]=r21,16
1041         (p7)    add             carry2=1,carry3
1042         (p8)    add             carry2=0,carry3 }
1043
1044 { .mii  mov             carry1=0
1045         cmp.ltu         p6,p0=r25,r24
1046         add             r26=r26,r25             };;
1047 { .mfb          getf.sig        r16=f115        }
1048 { .mii
1049 (p6)    add             carry1=1,carry1
1050         cmp.ltu         p6,p0=r26,r25
1051         add             r27=r27,r26             };;
1052 { .mfb          getf.sig        r17=f106        }
1053 { .mii
1054 (p6)    add             carry1=1,carry1
1055         cmp.ltu         p6,p0=r27,r26
1056         add             r28=r28,r27             };;
1057 { .mfb          getf.sig        r18=f97         }
1058 { .mii
1059 (p6)    add             carry1=1,carry1
1060         cmp.ltu         p6,p0=r28,r27
1061         add             r28=r28,carry2          };;
1062 { .mib          getf.sig        r19=f88
1063                 add             r17=r17,r16     }
1064 { .mib
1065 (p6)    add             carry1=1,carry1
1066         cmp.ltu         p6,p0=r28,carry2        };;
1067 { .mii  st8             [r33]=r28,16
1068 (p6)    add             carry1=1,carry1         }
1069
1070 { .mii          mov             carry2=0
1071                 cmp.ltu         p7,p0=r17,r16
1072                 add             r18=r18,r17     };;
1073 { .mfb  getf.sig        r24=f116                }
1074 { .mii  (p7)    add             carry2=1,carry2
1075                 cmp.ltu         p7,p0=r18,r17
1076                 add             r19=r19,r18     };;
1077 { .mfb  getf.sig        r25=f107                }
1078 { .mii  (p7)    add             carry2=1,carry2
1079                 cmp.ltu         p7,p0=r19,r18
1080                 add             r19=r19,carry1  };;
1081 { .mfb  getf.sig        r26=f98                 }
1082 { .mii  (p7)    add             carry2=1,carry2
1083                 cmp.ltu         p7,p0=r19,carry1};;
1084 { .mii          st8             [r32]=r19,16
1085         (p7)    add             carry2=1,carry2 }
1086
1087 { .mfb  add             r25=r25,r24             };;
1088
1089 { .mfb          getf.sig        r16=f117        }
1090 { .mii  mov             carry1=0
1091         cmp.ltu         p6,p0=r25,r24
1092         add             r26=r26,r25             };;
1093 { .mfb          getf.sig        r17=f108        }
1094 { .mii
1095 (p6)    add             carry1=1,carry1
1096         cmp.ltu         p6,p0=r26,r25
1097         add             r26=r26,carry2          };;
1098 { .mfb  nop.m   0x0                             }
1099 { .mii
1100 (p6)    add             carry1=1,carry1
1101         cmp.ltu         p6,p0=r26,carry2        };;
1102 { .mii  st8             [r33]=r26,16
1103 (p6)    add             carry1=1,carry1         }
1104
1105 { .mfb          add             r17=r17,r16     };;
1106 { .mfb  getf.sig        r24=f118                }
1107 { .mii          mov             carry2=0
1108                 cmp.ltu         p7,p0=r17,r16
1109                 add             r17=r17,carry1  };;
1110 { .mii  (p7)    add             carry2=1,carry2
1111                 cmp.ltu         p7,p0=r17,carry1};;
1112 { .mii          st8             [r32]=r17
1113         (p7)    add             carry2=1,carry2 };;
1114 { .mfb  add             r24=r24,carry2          };;
1115 { .mib  st8             [r33]=r24               }
1116
1117 { .mib  rum             1<<5            // clear um.mfh
1118         br.ret.sptk.many        b0      };;
1119 .endp   bn_mul_comba8#
1120 .endp   bn_sqr_comba8#
1121 #undef  carry3
1122 #undef  carry2
1123 #undef  carry1
1124 #endif
1125
1126 #if 1
1127 // It's possible to make it faster (see comment to bn_sqr_comba8), but
1128 // I reckon it doesn't worth the effort. Basically because the routine
1129 // (actually both of them) practically never called... So I just play
1130 // same trick as with bn_sqr_comba8.
1131 //
1132 // void bn_sqr_comba4(BN_ULONG *r, BN_ULONG *a)
1133 //
1134 .global bn_sqr_comba4#
1135 .proc   bn_sqr_comba4#
1136 .align  64
1137 bn_sqr_comba4:
1138         .prologue
1139         .fframe 0
1140         .save   ar.pfs,r2
1141 { .mii  alloc   r2=ar.pfs,2,1,0,0
1142         mov     r34=r33
1143         add     r14=8,r33               };;
1144         .body
1145 { .mii  add     r17=8,r34
1146         add     r15=16,r33
1147         add     r18=16,r34              }
1148 { .mfb  add     r16=24,r33
1149         br      .L_cheat_entry_point4   };;
1150 #endif
1151
1152 #if 1
1153 // Runs in ~115 cycles and ~4.5 times faster than C. Well, whatever...
1154 //
1155 // void bn_mul_comba4(BN_ULONG *r, BN_ULONG *a, BN_ULONG *b)
1156 //
1157 #define carry1  r14
1158 #define carry2  r15
1159 .global bn_mul_comba4#
1160 .proc   bn_mul_comba4#
1161 .align  64
1162 bn_mul_comba4:
1163         .prologue
1164         .fframe 0
1165         .save   ar.pfs,r2
1166 { .mii  alloc   r2=ar.pfs,3,0,0,0
1167         add     r14=8,r33
1168         add     r17=8,r34               }
1169         .body
1170 { .mii  add     r15=16,r33
1171         add     r18=16,r34
1172         add     r16=24,r33              };;
1173 .L_cheat_entry_point4:
1174 { .mmi  add     r19=24,r34
1175
1176         ldf8    f32=[r33]               }
1177
1178 { .mmi  ldf8    f120=[r34]
1179         ldf8    f121=[r17]              };;
1180 { .mmi  ldf8    f122=[r18]
1181         ldf8    f123=[r19]              }
1182
1183 { .mmi  ldf8    f33=[r14]
1184         ldf8    f34=[r15]               }
1185 { .mfi  ldf8    f35=[r16]
1186
1187                 xma.hu  f41=f32,f120,f0         }
1188 { .mfi          xma.lu  f40=f32,f120,f0         };;
1189 { .mfi          xma.hu  f51=f32,f121,f0         }
1190 { .mfi          xma.lu  f50=f32,f121,f0         };;
1191 { .mfi          xma.hu  f61=f32,f122,f0         }
1192 { .mfi          xma.lu  f60=f32,f122,f0         };;
1193 { .mfi          xma.hu  f71=f32,f123,f0         }
1194 { .mfi          xma.lu  f70=f32,f123,f0         };;;;
1195 // Major stall takes place here, and 3 more places below. Result from
1196 // first xma is not available for another 3 ticks.
1197 { .mfi  getf.sig        r16=f40
1198                 xma.hu  f42=f33,f120,f41
1199         add             r33=8,r32               }
1200 { .mfi          xma.lu  f41=f33,f120,f41        };;
1201 { .mfi  getf.sig        r24=f50
1202                 xma.hu  f52=f33,f121,f51        }
1203 { .mfi          xma.lu  f51=f33,f121,f51        };;
1204 { .mfi  st8             [r32]=r16,16
1205                 xma.hu  f62=f33,f122,f61        }
1206 { .mfi          xma.lu  f61=f33,f122,f61        };;
1207 { .mfi          xma.hu  f72=f33,f123,f71        }
1208 { .mfi          xma.lu  f71=f33,f123,f71        };;;;
1209 //-------------------------------------------------//
1210 { .mfi  getf.sig        r25=f41
1211                 xma.hu  f43=f34,f120,f42        }
1212 { .mfi          xma.lu  f42=f34,f120,f42        };;
1213 { .mfi  getf.sig        r16=f60
1214                 xma.hu  f53=f34,f121,f52        }
1215 { .mfi          xma.lu  f52=f34,f121,f52        };;
1216 { .mfi  getf.sig        r17=f51
1217                 xma.hu  f63=f34,f122,f62
1218         add             r25=r25,r24             }
1219 { .mfi  mov             carry1=0
1220                 xma.lu  f62=f34,f122,f62        };;
1221 { .mfi  st8             [r33]=r25,16
1222                 xma.hu  f73=f34,f123,f72
1223         cmp.ltu         p6,p0=r25,r24           }
1224 { .mfi          xma.lu  f72=f34,f123,f72        };;;;
1225 //-------------------------------------------------//
1226 { .mfi  getf.sig        r18=f42
1227                 xma.hu  f44=f35,f120,f43
1228 (p6)    add             carry1=1,carry1         }
1229 { .mfi  add             r17=r17,r16
1230                 xma.lu  f43=f35,f120,f43
1231         mov             carry2=0                };;
1232 { .mfi  getf.sig        r24=f70
1233                 xma.hu  f54=f35,f121,f53
1234         cmp.ltu         p7,p0=r17,r16           }
1235 { .mfi          xma.lu  f53=f35,f121,f53        };;
1236 { .mfi  getf.sig        r25=f61
1237                 xma.hu  f64=f35,f122,f63
1238         add             r18=r18,r17             }
1239 { .mfi          xma.lu  f63=f35,f122,f63
1240 (p7)    add             carry2=1,carry2         };;
1241 { .mfi  getf.sig        r26=f52
1242                 xma.hu  f74=f35,f123,f73
1243         cmp.ltu         p7,p0=r18,r17           }
1244 { .mfi          xma.lu  f73=f35,f123,f73
1245         add             r18=r18,carry1          };;
1246 //-------------------------------------------------//
1247 { .mii  st8             [r32]=r18,16
1248 (p7)    add             carry2=1,carry2
1249         cmp.ltu         p7,p0=r18,carry1        };;
1250
1251 { .mfi  getf.sig        r27=f43 // last major stall
1252 (p7)    add             carry2=1,carry2         };;
1253 { .mii          getf.sig        r16=f71
1254         add             r25=r25,r24
1255         mov             carry1=0                };;
1256 { .mii          getf.sig        r17=f62
1257         cmp.ltu         p6,p0=r25,r24
1258         add             r26=r26,r25             };;
1259 { .mii
1260 (p6)    add             carry1=1,carry1
1261         cmp.ltu         p6,p0=r26,r25
1262         add             r27=r27,r26             };;
1263 { .mii
1264 (p6)    add             carry1=1,carry1
1265         cmp.ltu         p6,p0=r27,r26
1266         add             r27=r27,carry2          };;
1267 { .mii          getf.sig        r18=f53
1268 (p6)    add             carry1=1,carry1
1269         cmp.ltu         p6,p0=r27,carry2        };;
1270 { .mfi  st8             [r33]=r27,16
1271 (p6)    add             carry1=1,carry1         }
1272
1273 { .mii          getf.sig        r19=f44
1274                 add             r17=r17,r16
1275                 mov             carry2=0        };;
1276 { .mii  getf.sig        r24=f72
1277                 cmp.ltu         p7,p0=r17,r16
1278                 add             r18=r18,r17     };;
1279 { .mii  (p7)    add             carry2=1,carry2
1280                 cmp.ltu         p7,p0=r18,r17
1281                 add             r19=r19,r18     };;
1282 { .mii  (p7)    add             carry2=1,carry2
1283                 cmp.ltu         p7,p0=r19,r18
1284                 add             r19=r19,carry1  };;
1285 { .mii  getf.sig        r25=f63
1286         (p7)    add             carry2=1,carry2
1287                 cmp.ltu         p7,p0=r19,carry1};;
1288 { .mii          st8             [r32]=r19,16
1289         (p7)    add             carry2=1,carry2 }
1290
1291 { .mii  getf.sig        r26=f54
1292         add             r25=r25,r24
1293         mov             carry1=0                };;
1294 { .mii          getf.sig        r16=f73
1295         cmp.ltu         p6,p0=r25,r24
1296         add             r26=r26,r25             };;
1297 { .mii
1298 (p6)    add             carry1=1,carry1
1299         cmp.ltu         p6,p0=r26,r25
1300         add             r26=r26,carry2          };;
1301 { .mii          getf.sig        r17=f64
1302 (p6)    add             carry1=1,carry1
1303         cmp.ltu         p6,p0=r26,carry2        };;
1304 { .mii  st8             [r33]=r26,16
1305 (p6)    add             carry1=1,carry1         }
1306
1307 { .mii  getf.sig        r24=f74
1308                 add             r17=r17,r16
1309                 mov             carry2=0        };;
1310 { .mii          cmp.ltu         p7,p0=r17,r16
1311                 add             r17=r17,carry1  };;
1312
1313 { .mii  (p7)    add             carry2=1,carry2
1314                 cmp.ltu         p7,p0=r17,carry1};;
1315 { .mii          st8             [r32]=r17,16
1316         (p7)    add             carry2=1,carry2 };;
1317
1318 { .mii  add             r24=r24,carry2          };;
1319 { .mii  st8             [r33]=r24               }
1320
1321 { .mib  rum             1<<5            // clear um.mfh
1322         br.ret.sptk.many        b0      };;
1323 .endp   bn_mul_comba4#
1324 .endp   bn_sqr_comba4#
1325 #undef  carry2
1326 #undef  carry1
1327 #endif
1328
1329 #if 1
1330 //
1331 // BN_ULONG bn_div_words(BN_ULONG h, BN_ULONG l, BN_ULONG d)
1332 //
1333 // In the nutshell it's a port of my MIPS III/IV implementation.
1334 //
1335 #define AT      r14
1336 #define H       r16
1337 #define HH      r20
1338 #define L       r17
1339 #define D       r18
1340 #define DH      r22
1341 #define I       r21
1342
1343 #define cont    p16
1344 #define break   p0      // p20
1345 #define equ     p24
1346 .global abort#
1347 .global bn_div_words#
1348 .proc   bn_div_words#
1349 .align  64
1350 bn_div_words:
1351         .prologue
1352         .fframe 0
1353         .save   ar.pfs,r2
1354         .save   b0,r3
1355 { .mii  alloc           r2=ar.pfs,3,5,0,8
1356         mov             r3=b0
1357         mov             r10=pr          };;
1358 { .mmb  cmp.eq          p6,p0=r34,r0
1359         mov             r8=-1
1360 (p6)    br.ret.spnt.many        b0      };;
1361
1362         .body
1363 { .mii  mov             H=r32           // save h
1364         mov             ar.ec=0         // don't rotate at exit
1365         mov             pr.rot=0        }
1366 { .mii  mov             L=r33           // save l
1367         mov             r36=r0          }
1368
1369 1:      ;;      // -vv- note signed comparison
1370 { .mfi  (p0)    cmp.lt          p16,p0=r0,r34   // d
1371         (p0)    shladd          r33=r34,1,r0    }
1372 { .mfb  (p0)    add             r35=1,r36
1373         (p0)    nop.f           0x0
1374 (p16)   br.wtop.dpnt            1b              };;
1375
1376 { .mii  mov             D=r34
1377         shr.u           DH=r34,32
1378         sub             r35=64,r36              };;
1379 { .mii  setf.sig        f7=DH
1380         shr.u           AT=H,r35
1381         mov             I=r36                   };;
1382 { .mib  cmp.ne          p6,p0=r0,AT
1383         shl             H=H,r36
1384 (p6)    br.call.spnt.clr        b0=abort        };;     // overflow, die...
1385
1386 { .mfi  fcvt.xuf.s1     f7=f7
1387         shr.u           AT=L,r35                };;
1388 { .mii  shl             L=L,r36
1389         or              H=H,AT                  };;
1390
1391 { .mii  nop.m           0x0
1392         cmp.leu         p6,p0=D,H;;
1393 (p6)    sub             H=H,D                   }
1394
1395 { .mlx  setf.sig        f14=D
1396         movl            AT=0xffffffff           };;
1397 ///////////////////////////////////////////////////////////
1398 { .mii  setf.sig        f6=H
1399         shr.u           HH=H,32;;
1400         cmp.eq          p6,p7=HH,DH             };;
1401 { .mfb
1402 (p6)    setf.sig        f8=AT
1403 (p7)    fcvt.xuf.s1     f6=f6
1404 (p7)    br.call.sptk    b6=.L_udiv64_32_b6      };;
1405
1406 { .mfi  getf.sig        r33=f8                          // q
1407         xmpy.lu         f9=f8,f14               }
1408 { .mfi  xmpy.hu         f10=f8,f14
1409         shrp            H=H,L,32                };;
1410
1411 { .mmi  getf.sig        r35=f9                          // tl
1412         getf.sig        r31=f10                 };;     // th
1413
1414 2:      ;;
1415 { .mii  (p0)    add             r32=-1,r33
1416         (p0)    cmp.eq          equ,cont=HH,r31         };;
1417 { .mii  (p0)    cmp.ltu         p8,p0=r35,D
1418         (p0)    sub             r34=r35,D
1419         (equ)   cmp.leu         break,cont=r35,H        };;
1420 { .mib  (cont)  cmp.leu         cont,break=HH,r31
1421         (p8)    add             r31=-1,r31
1422 (cont)  br.wtop.spnt            2b                      };;
1423 ///////////////////////////////////////////////////////////
1424 { .mii  sub             H=H,r35
1425         shl             r8=r33,32
1426         shl             L=L,32                  };;
1427 ///////////////////////////////////////////////////////////
1428 { .mii  setf.sig        f6=H
1429         shr.u           HH=H,32;;
1430         cmp.eq          p6,p7=HH,DH             };;
1431 { .mfb
1432 (p6)    setf.sig        f8=AT
1433 (p7)    fcvt.xuf.s1     f6=f6
1434 (p7)    br.call.sptk    b6=.L_udiv64_32_b6      };;
1435
1436 { .mfi  getf.sig        r33=f8                          // q
1437         xmpy.lu         f9=f8,f14               }
1438 { .mfi  xmpy.hu         f10=f8,f14
1439         shrp            H=H,L,32                };;
1440
1441 { .mmi  getf.sig        r35=f9                          // tl
1442         getf.sig        r31=f10                 };;     // th
1443
1444 2:      ;;
1445 { .mii  (p0)    add             r32=-1,r33
1446         (p0)    cmp.eq          equ,cont=HH,r31         };;
1447 { .mii  (p0)    cmp.ltu         p8,p0=r35,D
1448         (p0)    sub             r34=r35,D
1449         (equ)   cmp.leu         break,cont=r35,H        };;
1450 { .mib  (cont)  cmp.leu         cont,break=HH,r31
1451         (p8)    add             r31=-1,r31
1452 (cont)  br.wtop.spnt            2b                      };;
1453 ///////////////////////////////////////////////////////////
1454 { .mii  sub     H=H,r35
1455         or      r8=r8,r33
1456         mov     ar.pfs=r2               };;
1457 { .mii  shr.u   r9=H,I                  // remainder if anybody wants it
1458         mov     pr=r10,-1               }
1459 { .mfb  br.ret.sptk.many        b0      };;
1460
1461 // Unsigned 64 by 32 (well, by 64 for the moment) bit integer division
1462 // procedure.
1463 //
1464 // inputs:      f6 = (double)a, f7 = (double)b
1465 // output:      f8 = (int)(a/b)
1466 // clobbered:   f8,f9,f10,f11,PR
1467 #define PR      p15
1468 // This procedure is essentially Intel code and therefore is
1469 // copyrighted to Intel Corporation (I suppose...). It's sligtly
1470 // modified for specific needs.
1471 .align  32
1472 .space  16
1473 .L_udiv64_32_b6:
1474         frcpa.s1        f8,PR=f6,f7;;           // [0]  y0 = 1 / b
1475
1476 (PR)    fnma.s1         f9=f7,f8,f1             // [5]  e0 = 1 - b * y0
1477 (PR)    fmpy.s1         f10=f6,f8;;             // [5]  q0 = a * y0
1478 (PR)    fmpy.s1         f11=f9,f9               // [10] e1 = e0 * e0
1479 (PR)    fma.s1          f10=f9,f10,f10;;        // [10] q1 = q0 + e0 * q0
1480 (PR)    fma.s1          f8=f9,f8,f8     //;;    // [15] y1 = y0 + e0 * y0
1481 (PR)    fma.s1          f9=f11,f10,f10;;        // [15] q2 = q1 + e1 * q1
1482 (PR)    fma.s1          f8=f11,f8,f8    //;;    // [20] y2 = y1 + e1 * y1
1483 (PR)    fnma.s1         f10=f7,f9,f6;;          // [20] r2 = a - b * q2
1484 (PR)    fma.s1          f8=f10,f8,f9;;          // [25] q3 = q2 + r2 * y2
1485
1486         fcvt.fxu.trunc.s1       f8=f8           // [30] q = trunc(q3)
1487         br.ret.sptk.many        b6;;
1488 .endp   bn_div_words#
1489 #endif