crypto/bn/asm/ia64.S

   1 .explicit
   2 .text
   3 .ident  "ia64.S, Version 2.1"
   4 .ident  "IA-64 ISA artwork by Andy Polyakov <appro@fy.chalmers.se>"
   5
   6 //
   7 // ====================================================================
   8 // Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
   9 // project.
  10 //
  11 // Rights for redistribution and usage in source and binary forms are
  12 // granted according to the OpenSSL license. Warranty of any kind is
  13 // disclaimed.
  14 // ====================================================================
  15 //
  16 // Version 2.x is Itanium2 re-tune. Few words about how Itanum2 is
  17 // different from Itanium to this module viewpoint. Most notably, is it
  18 // "wider" than Itanium? Can you experience loop scalability as
  19 // discussed in commentary sections? Not really:-( Itanium2 has 6
  20 // integer ALU ports, i.e. it's 2 ports wider, but it's not enough to
  21 // spin twice as fast, as I need 8 IALU ports. Amount of floating point
  22 // ports is the same, i.e. 2, while I need 4. In other words, to this
  23 // module Itanium2 remains effectively as "wide" as Itanium. Yet it's
  24 // essentially different in respect to this module, and a re-tune was
  25 // required. Well, because some intruction latencies has changed. Most
  26 // noticeably those intensively used:
  27 //
  28 //                      Itanium Itanium2
  29 //      ldf8            9       6               L2 hit
  30 //      ld8             2       1               L1 hit
  31 //      getf            2       5
  32 //      xma[->getf]     7[+1]   4[+0]
  33 //      add[->st8]      1[+1]   1[+0]
  34 //
  35 // What does it mean? You might ratiocinate that the original code
  36 // should run just faster... Because sum of latencies is smaller...
  37 // Wrong! Note that getf latency increased. This means that if a loop is
  38 // scheduled for lower latency (as they were), then it will suffer from
  39 // stall condition and the code will therefore turn anti-scalable, e.g.
  40 // original bn_mul_words spun at 5*n or 2.5 times slower than expected
  41 // on Itanium2! What to do? Reschedule loops for Itanium2? But then
  42 // Itanium would exhibit anti-scalability. So I've chosen to reschedule
  43 // for worst latency for every instruction aiming for best *all-round*
  44 // performance.
  45
  46 // Q.   How much faster does it get?
  47 // A.   Here is the output from 'openssl speed rsa dsa' for vanilla
  48 //      0.9.6a compiled with gcc version 2.96 20000731 (Red Hat
  49 //      Linux 7.1 2.96-81):
  50 //
  51 //                        sign    verify    sign/s verify/s
  52 //      rsa  512 bits   0.0036s   0.0003s    275.3   2999.2
  53 //      rsa 1024 bits   0.0203s   0.0011s     49.3    894.1
  54 //      rsa 2048 bits   0.1331s   0.0040s      7.5    250.9
  55 //      rsa 4096 bits   0.9270s   0.0147s      1.1     68.1
  56 //                        sign    verify    sign/s verify/s
  57 //      dsa  512 bits   0.0035s   0.0043s    288.3    234.8
  58 //      dsa 1024 bits   0.0111s   0.0135s     90.0     74.2
  59 //
  60 //      And here is similar output but for this assembler
  61 //      implementation:-)
  62 //
  63 //                        sign    verify    sign/s verify/s
  64 //      rsa  512 bits   0.0021s   0.0001s    549.4   9638.5
  65 //      rsa 1024 bits   0.0055s   0.0002s    183.8   4481.1
  66 //      rsa 2048 bits   0.0244s   0.0006s     41.4   1726.3
  67 //      rsa 4096 bits   0.1295s   0.0018s      7.7    561.5
  68 //                        sign    verify    sign/s verify/s
  69 //      dsa  512 bits   0.0012s   0.0013s    891.9    756.6
  70 //      dsa 1024 bits   0.0023s   0.0028s    440.4    376.2
  71 //
  72 //      Yes, you may argue that it's not fair comparison as it's
  73 //      possible to craft the C implementation with BN_UMULT_HIGH
  74 //      inline assembler macro. But of course! Here is the output
  75 //      with the macro:
  76 //
  77 //                        sign    verify    sign/s verify/s
  78 //      rsa  512 bits   0.0020s   0.0002s    495.0   6561.0
  79 //      rsa 1024 bits   0.0086s   0.0004s    116.2   2235.7
  80 //      rsa 2048 bits   0.0519s   0.0015s     19.3    667.3
  81 //      rsa 4096 bits   0.3464s   0.0053s      2.9    187.7
  82 //                        sign    verify    sign/s verify/s
  83 //      dsa  512 bits   0.0016s   0.0020s    613.1    510.5
  84 //      dsa 1024 bits   0.0045s   0.0054s    221.0    183.9
  85 //
  86 //      My code is still way faster, huh:-) And I believe that even
  87 //      higher performance can be achieved. Note that as keys get
  88 //      longer, performance gain is larger. Why? According to the
  89 //      profiler there is another player in the field, namely
  90 //      BN_from_montgomery consuming larger and larger portion of CPU
  91 //      time as keysize decreases. I therefore consider putting effort
  92 //      to assembler implementation of the following routine:
  93 //
  94 //      void bn_mul_add_mont (BN_ULONG *rp,BN_ULONG *np,int nl,BN_ULONG n0)
  95 //      {
  96 //      int      i,j;
  97 //      BN_ULONG v;
  98 //
  99 //      for (i=0; i<nl; i++)
 100 //              {
 101 //              v=bn_mul_add_words(rp,np,nl,(rp[0]*n0)&BN_MASK2);
 102 //              nrp++;
 103 //              rp++;
 104 //              if (((nrp[-1]+=v)&BN_MASK2) < v)
 105 //                      for (j=0; ((++nrp[j])&BN_MASK2) == 0; j++) ;
 106 //              }
 107 //      }
 108 //
 109 //      It might as well be beneficial to implement even combaX
 110 //      variants, as it appears as it can literally unleash the
 111 //      performance (see comment section to bn_mul_comba8 below).
 112 //
 113 //      And finally for your reference the output for 0.9.6a compiled
 114 //      with SGIcc version 0.01.0-12 (keep in mind that for the moment
 115 //      of this writing it's not possible to convince SGIcc to use
 116 //      BN_UMULT_HIGH inline assembler macro, yet the code is fast,
 117 //      i.e. for a compiler generated one:-):
 118 //
 119 //                        sign    verify    sign/s verify/s
 120 //      rsa  512 bits   0.0022s   0.0002s    452.7   5894.3
 121 //      rsa 1024 bits   0.0097s   0.0005s    102.7   2002.9
 122 //      rsa 2048 bits   0.0578s   0.0017s     17.3    600.2
 123 //      rsa 4096 bits   0.3838s   0.0061s      2.6    164.5
 124 //                        sign    verify    sign/s verify/s
 125 //      dsa  512 bits   0.0018s   0.0022s    547.3    459.6
 126 //      dsa 1024 bits   0.0051s   0.0062s    196.6    161.3
 127 //
 128 //      Oh! Benchmarks were performed on 733MHz Lion-class Itanium
 129 //      system running Redhat Linux 7.1 (very special thanks to Ray
 130 //      McCaffity of Williams Communications for providing an account).
 131 //
 132 // Q.   What's the heck with 'rum 1<<5' at the end of every function?
 133 // A.   Well, by clearing the "upper FP registers written" bit of the
 134 //      User Mask I want to excuse the kernel from preserving upper
 135 //      (f32-f128) FP register bank over process context switch, thus
 136 //      minimizing bus bandwidth consumption during the switch (i.e.
 137 //      after PKI opration completes and the program is off doing
 138 //      something else like bulk symmetric encryption). Having said
 139 //      this, I also want to point out that it might be good idea
 140 //      to compile the whole toolkit (as well as majority of the
 141 //      programs for that matter) with -mfixed-range=f32-f127 command
 142 //      line option. No, it doesn't prevent the compiler from writing
 143 //      to upper bank, but at least discourages to do so. If you don't
 144 //      like the idea you have the option to compile the module with
 145 //      -Drum=nop.m in command line.
 146 //
 147
 148 #if defined(_HPUX_SOURCE) && !defined(_LP64)
 149 #define ADDP    addp4
 150 #else
 151 #define ADDP    add
 152 #endif
 153
 154 #if 1
 155 //
 156 // bn_[add|sub]_words routines.
 157 //
 158 // Loops are spinning in 2*(n+5) ticks on Itanuim (provided that the
 159 // data reside in L1 cache, i.e. 2 ticks away). It's possible to
 160 // compress the epilogue and get down to 2*n+6, but at the cost of
 161 // scalability (the neat feature of this implementation is that it
 162 // shall automagically spin in n+5 on "wider" IA-64 implementations:-)
 163 // I consider that the epilogue is short enough as it is to trade tiny
 164 // performance loss on Itanium for scalability.
 165 //
 166 // BN_ULONG bn_add_words(BN_ULONG *rp, BN_ULONG *ap, BN_ULONG *bp,int num)
 167 //
 168 .global bn_add_words#
 169 .proc   bn_add_words#
 170 .align  64
 171 .skip   32      // makes the loop body aligned at 64-byte boundary
 172 bn_add_words:
 173         .prologue
 174         .save   ar.pfs,r2
 175 { .mii; alloc           r2=ar.pfs,4,12,0,16
 176         cmp4.le         p6,p0=r35,r0    };;
 177 { .mfb; mov             r8=r0                   // return value
 178 (p6)    br.ret.spnt.many        b0      };;
 179
 180 { .mib; sub             r10=r35,r0,1
 181         .save   ar.lc,r3
 182         mov             r3=ar.lc
 183         brp.loop.imp    .L_bn_add_words_ctop,.L_bn_add_words_cend-16
 184                                         }
 185         .body
 186 { .mib; ADDP            r14=0,r32               // rp
 187         mov             r9=pr           };;
 188 { .mii; ADDP            r15=0,r33               // ap
 189         mov             ar.lc=r10
 190         mov             ar.ec=6         }
 191 { .mib; ADDP            r16=0,r34               // bp
 192         mov             pr.rot=1<<16    };;
 193
 194 .L_bn_add_words_ctop:
 195 { .mii; (p16)   ld8             r32=[r16],8       // b=*(bp++)
 196         (p18)   add             r39=r37,r34
 197         (p19)   cmp.ltu.unc     p56,p0=r40,r38  }
 198 { .mfb; (p0)    nop.m           0x0
 199         (p0)    nop.f           0x0
 200         (p0)    nop.b           0x0             }
 201 { .mii; (p16)   ld8             r35=[r15],8       // a=*(ap++)
 202         (p58)   cmp.eq.or       p57,p0=-1,r41     // (p20)
 203         (p58)   add             r41=1,r41       } // (p20)
 204 { .mfb; (p21)   st8             [r14]=r42,8       // *(rp++)=r
 205         (p0)    nop.f           0x0
 206         br.ctop.sptk    .L_bn_add_words_ctop    };;
 207 .L_bn_add_words_cend:
 208
 209 { .mii;
 210 (p59)   add             r8=1,r8         // return value
 211         mov             pr=r9,0x1ffff
 212         mov             ar.lc=r3        }
 213 { .mbb; nop.b           0x0
 214         br.ret.sptk.many        b0      };;
 215 .endp   bn_add_words#
 216
 217 //
 218 // BN_ULONG bn_sub_words(BN_ULONG *rp, BN_ULONG *ap, BN_ULONG *bp,int num)
 219 //
 220 .global bn_sub_words#
 221 .proc   bn_sub_words#
 222 .align  64
 223 .skip   32      // makes the loop body aligned at 64-byte boundary
 224 bn_sub_words:
 225         .prologue
 226         .save   ar.pfs,r2
 227 { .mii; alloc           r2=ar.pfs,4,12,0,16
 228         cmp4.le         p6,p0=r35,r0    };;
 229 { .mfb; mov             r8=r0                   // return value
 230 (p6)    br.ret.spnt.many        b0      };;
 231
 232 { .mib; sub             r10=r35,r0,1
 233         .save   ar.lc,r3
 234         mov             r3=ar.lc
 235         brp.loop.imp    .L_bn_sub_words_ctop,.L_bn_sub_words_cend-16
 236                                         }
 237         .body
 238 { .mib; ADDP            r14=0,r32               // rp
 239         mov             r9=pr           };;
 240 { .mii; ADDP            r15=0,r33               // ap
 241         mov             ar.lc=r10
 242         mov             ar.ec=6         }
 243 { .mib; ADDP            r16=0,r34               // bp
 244         mov             pr.rot=1<<16    };;
 245
 246 .L_bn_sub_words_ctop:
 247 { .mii; (p16)   ld8             r32=[r16],8       // b=*(bp++)
 248         (p18)   sub             r39=r37,r34
 249         (p19)   cmp.gtu.unc     p56,p0=r40,r38  }
 250 { .mfb; (p0)    nop.m           0x0
 251         (p0)    nop.f           0x0
 252         (p0)    nop.b           0x0             }
 253 { .mii; (p16)   ld8             r35=[r15],8       // a=*(ap++)
 254         (p58)   cmp.eq.or       p57,p0=0,r41      // (p20)
 255         (p58)   add             r41=-1,r41      } // (p20)
 256 { .mbb; (p21)   st8             [r14]=r42,8       // *(rp++)=r
 257         (p0)    nop.b           0x0
 258         br.ctop.sptk    .L_bn_sub_words_ctop    };;
 259 .L_bn_sub_words_cend:
 260
 261 { .mii;
 262 (p59)   add             r8=1,r8         // return value
 263         mov             pr=r9,0x1ffff
 264         mov             ar.lc=r3        }
 265 { .mbb; nop.b           0x0
 266         br.ret.sptk.many        b0      };;
 267 .endp   bn_sub_words#
 268 #endif
 269
 270 #if 0
 271 #define XMA_TEMPTATION
 272 #endif
 273
 274 #if 1
 275 //
 276 // BN_ULONG bn_mul_words(BN_ULONG *rp, BN_ULONG *ap, int num, BN_ULONG w)
 277 //
 278 .global bn_mul_words#
 279 .proc   bn_mul_words#
 280 .align  64
 281 .skip   32      // makes the loop body aligned at 64-byte boundary
 282 bn_mul_words:
 283         .prologue
 284         .save   ar.pfs,r2
 285 #ifdef XMA_TEMPTATION
 286 { .mfi; alloc           r2=ar.pfs,4,0,0,0       };;
 287 #else
 288 { .mfi; alloc           r2=ar.pfs,4,12,0,16     };;
 289 #endif
 290 { .mib; mov             r8=r0                   // return value
 291         cmp4.le         p6,p0=r34,r0
 292 (p6)    br.ret.spnt.many        b0              };;
 293
 294 { .mii; sub     r10=r34,r0,1
 295         .save   ar.lc,r3
 296         mov     r3=ar.lc
 297         mov     r9=pr                   };;
 298
 299         .body
 300 { .mib; setf.sig        f8=r35  // w
 301         mov             pr.rot=0x800001<<16
 302                         // ------^----- serves as (p50) at first (p27)
 303         brp.loop.imp    .L_bn_mul_words_ctop,.L_bn_mul_words_cend-16
 304                                         }
 305
 306 #ifndef XMA_TEMPTATION
 307
 308 { .mmi; ADDP            r14=0,r32       // rp
 309         ADDP            r15=0,r33       // ap
 310         mov             ar.lc=r10       }
 311 { .mmi; mov             r40=0           // serves as r35 at first (p27)
 312         mov             ar.ec=13        };;
 313
 314 // This loop spins in 2*(n+12) ticks. It's scheduled for data in Itanium
 315 // L2 cache (i.e. 9 ticks away) as floating point load/store instructions
 316 // bypass L1 cache and L2 latency is actually best-case scenario for
 317 // ldf8. The loop is not scalable and shall run in 2*(n+12) even on
 318 // "wider" IA-64 implementations. It's a trade-off here. n+24 loop
 319 // would give us ~5% in *overall* performance improvement on "wider"
 320 // IA-64, but would hurt Itanium for about same because of longer
 321 // epilogue. As it's a matter of few percents in either case I've
 322 // chosen to trade the scalability for development time (you can see
 323 // this very instruction sequence in bn_mul_add_words loop which in
 324 // turn is scalable).
 325 .L_bn_mul_words_ctop:
 326 { .mfi; (p25)   getf.sig        r36=f52                 // low
 327         (p21)   xmpy.lu         f48=f37,f8
 328         (p28)   cmp.ltu         p54,p50=r41,r39 }
 329 { .mfi; (p16)   ldf8            f32=[r15],8
 330         (p21)   xmpy.hu         f40=f37,f8
 331         (p0)    nop.i           0x0             };;
 332 { .mii; (p25)   getf.sig        r32=f44                 // high
 333         .pred.rel       "mutex",p50,p54
 334         (p50)   add             r40=r38,r35             // (p27)
 335         (p54)   add             r40=r38,r35,1   }       // (p27)
 336 { .mfb; (p28)   st8             [r14]=r41,8
 337         (p0)    nop.f           0x0
 338         br.ctop.sptk    .L_bn_mul_words_ctop    };;
 339 .L_bn_mul_words_cend:
 340
 341 { .mii; nop.m           0x0
 342 .pred.rel       "mutex",p51,p55
 343 (p51)   add             r8=r36,r0
 344 (p55)   add             r8=r36,r0,1     }
 345 { .mfb; nop.m   0x0
 346         nop.f   0x0
 347         nop.b   0x0                     }
 348
 349 #else   // XMA_TEMPTATION
 350
 351         setf.sig        f37=r0  // serves as carry at (p18) tick
 352         mov             ar.lc=r10
 353         mov             ar.ec=5;;
 354
 355 // Most of you examining this code very likely wonder why in the name
 356 // of Intel the following loop is commented out? Indeed, it looks so
 357 // neat that you find it hard to believe that it's something wrong
 358 // with it, right? The catch is that every iteration depends on the
 359 // result from previous one and the latter isn't available instantly.
 360 // The loop therefore spins at the latency of xma minus 1, or in other
 361 // words at 6*(n+4) ticks:-( Compare to the "production" loop above
 362 // that runs in 2*(n+11) where the low latency problem is worked around
 363 // by moving the dependency to one-tick latent interger ALU. Note that
 364 // "distance" between ldf8 and xma is not latency of ldf8, but the
 365 // *difference* between xma and ldf8 latencies.
 366 .L_bn_mul_words_ctop:
 367 { .mfi; (p16)   ldf8            f32=[r33],8
 368         (p18)   xma.hu          f38=f34,f8,f39  }
 369 { .mfb; (p20)   stf8            [r32]=f37,8
 370         (p18)   xma.lu          f35=f34,f8,f39
 371         br.ctop.sptk    .L_bn_mul_words_ctop    };;
 372 .L_bn_mul_words_cend:
 373
 374         getf.sig        r8=f41          // the return value
 375
 376 #endif  // XMA_TEMPTATION
 377
 378 { .mii; nop.m           0x0
 379         mov             pr=r9,0x1ffff
 380         mov             ar.lc=r3        }
 381 { .mfb; rum             1<<5            // clear um.mfh
 382         nop.f           0x0
 383         br.ret.sptk.many        b0      };;
 384 .endp   bn_mul_words#
 385 #endif
 386
 387 #if 1
 388 //
 389 // BN_ULONG bn_mul_add_words(BN_ULONG *rp, BN_ULONG *ap, int num, BN_ULONG w)
 390 //
 391 .global bn_mul_add_words#
 392 .proc   bn_mul_add_words#
 393 .align  64
 394 .skip   48      // makes the loop body aligned at 64-byte boundary
 395 bn_mul_add_words:
 396         .prologue
 397         .save   ar.pfs,r2
 398 { .mmi; alloc           r2=ar.pfs,4,4,0,8
 399         cmp4.le         p6,p0=r34,r0
 400         .save   ar.lc,r3
 401         mov             r3=ar.lc        };;
 402 { .mib; mov             r8=r0           // return value
 403         sub             r10=r34,r0,1
 404 (p6)    br.ret.spnt.many        b0      };;
 405
 406         .body
 407 { .mib; setf.sig        f8=r35          // w
 408         .save   pr,r9
 409         mov             r9=pr
 410         brp.loop.imp    .L_bn_mul_add_words_ctop,.L_bn_mul_add_words_cend-16
 411                                         }
 412 { .mmi; ADDP            r14=0,r32       // rp
 413         ADDP            r15=0,r33       // ap
 414         mov             ar.lc=r10       }
 415 { .mii; ADDP            r16=0,r32       // rp copy
 416         mov             pr.rot=0x2001<<16
 417                         // ------^----- serves as (p40) at first (p27)
 418         mov             ar.ec=11        };;
 419
 420 // This loop spins in 3*(n+10) ticks on Itanium and in 2*(n+10) on
 421 // Itanium 2. Yes, unlike previous versions it scales:-) Previous
 422 // version was peforming *all* additions in IALU and was starving
 423 // for those even on Itanium 2. In this version one addition is
 424 // moved to FPU and is folded with multiplication. This is at cost
 425 // of propogating the result from previous call to this subroutine
 426 // to L2 cache... In other words negligible even for shorter keys.
 427 // *Overall* performance improvement [over previous version] varies
 428 // from 11 to 22 percent depending on key length.
 429 .L_bn_mul_add_words_ctop:
 430 .pred.rel       "mutex",p40,p42
 431 { .mfi; (p23)   getf.sig        r36=f45                 // low
 432         (p20)   xma.lu          f42=f36,f8,f50          // low
 433         (p40)   add             r39=r39,r35     }       // (p27)
 434 { .mfi; (p16)   ldf8            f32=[r15],8             // *(ap++)
 435         (p20)   xma.hu          f36=f36,f8,f50          // high
 436         (p42)   add             r39=r39,r35,1   };;     // (p27)
 437 { .mmi; (p24)   getf.sig        r32=f40                 // high
 438         (p16)   ldf8            f46=[r16],8             // *(rp1++)
 439         (p40)   cmp.ltu         p41,p39=r39,r35 }       // (p27)
 440 { .mib; (p26)   st8             [r14]=r39,8             // *(rp2++)
 441         (p42)   cmp.leu         p41,p39=r39,r35         // (p27)
 442         br.ctop.sptk    .L_bn_mul_add_words_ctop};;
 443 .L_bn_mul_add_words_cend:
 444
 445 { .mmi; .pred.rel       "mutex",p40,p42
 446 (p40)   add             r8=r35,r0
 447 (p42)   add             r8=r35,r0,1
 448         mov             pr=r9,0x1ffff   }
 449 { .mib; rum             1<<5            // clear um.mfh
 450         mov             ar.lc=r3
 451         br.ret.sptk.many        b0      };;
 452 .endp   bn_mul_add_words#
 453 #endif
 454
 455 #if 1
 456 //
 457 // void bn_sqr_words(BN_ULONG *rp, BN_ULONG *ap, int num)
 458 //
 459 .global bn_sqr_words#
 460 .proc   bn_sqr_words#
 461 .align  64
 462 .skip   32      // makes the loop body aligned at 64-byte boundary
 463 bn_sqr_words:
 464         .prologue
 465         .save   ar.pfs,r2
 466 { .mii; alloc           r2=ar.pfs,3,0,0,0
 467         sxt4            r34=r34         };;
 468 { .mii; cmp.le          p6,p0=r34,r0
 469         mov             r8=r0           }       // return value
 470 { .mfb; ADDP            r32=0,r32
 471         nop.f           0x0
 472 (p6)    br.ret.spnt.many        b0      };;
 473
 474 { .mii; sub     r10=r34,r0,1
 475         .save   ar.lc,r3
 476         mov     r3=ar.lc
 477         .save   pr,r9
 478         mov     r9=pr                   };;
 479
 480         .body
 481 { .mib; ADDP            r33=0,r33
 482         mov             pr.rot=1<<16
 483         brp.loop.imp    .L_bn_sqr_words_ctop,.L_bn_sqr_words_cend-16
 484                                         }
 485 { .mii; add             r34=8,r32
 486         mov             ar.lc=r10
 487         mov             ar.ec=18        };;
 488
 489 // 2*(n+17) on Itanium, (n+17) on "wider" IA-64 implementations. It's
 490 // possible to compress the epilogue (I'm getting tired to write this
 491 // comment over and over) and get down to 2*n+16 at the cost of
 492 // scalability. The decision will very likely be reconsidered after the
 493 // benchmark program is profiled. I.e. if perfomance gain on Itanium
 494 // will appear larger than loss on "wider" IA-64, then the loop should
 495 // be explicitely split and the epilogue compressed.
 496 .L_bn_sqr_words_ctop:
 497 { .mfi; (p16)   ldf8            f32=[r33],8
 498         (p25)   xmpy.lu         f42=f41,f41
 499         (p0)    nop.i           0x0             }
 500 { .mib; (p33)   stf8            [r32]=f50,16
 501         (p0)    nop.i           0x0
 502         (p0)    nop.b           0x0             }
 503 { .mfi; (p0)    nop.m           0x0
 504         (p25)   xmpy.hu         f52=f41,f41
 505         (p0)    nop.i           0x0             }
 506 { .mib; (p33)   stf8            [r34]=f60,16
 507         (p0)    nop.i           0x0
 508         br.ctop.sptk    .L_bn_sqr_words_ctop    };;
 509 .L_bn_sqr_words_cend:
 510
 511 { .mii; nop.m           0x0
 512         mov             pr=r9,0x1ffff
 513         mov             ar.lc=r3        }
 514 { .mfb; rum             1<<5            // clear um.mfh
 515         nop.f           0x0
 516         br.ret.sptk.many        b0      };;
 517 .endp   bn_sqr_words#
 518 #endif
 519
 520 #if 1
 521 // Apparently we win nothing by implementing special bn_sqr_comba8.
 522 // Yes, it is possible to reduce the number of multiplications by
 523 // almost factor of two, but then the amount of additions would
 524 // increase by factor of two (as we would have to perform those
 525 // otherwise performed by xma ourselves). Normally we would trade
 526 // anyway as multiplications are way more expensive, but not this
 527 // time... Multiplication kernel is fully pipelined and as we drain
 528 // one 128-bit multiplication result per clock cycle multiplications
 529 // are effectively as inexpensive as additions. Special implementation
 530 // might become of interest for "wider" IA-64 implementation as you'll
 531 // be able to get through the multiplication phase faster (there won't
 532 // be any stall issues as discussed in the commentary section below and
 533 // you therefore will be able to employ all 4 FP units)... But these
 534 // Itanium days it's simply too hard to justify the effort so I just
 535 // drop down to bn_mul_comba8 code:-)
 536 //
 537 // void bn_sqr_comba8(BN_ULONG *r, BN_ULONG *a)
 538 //
 539 .global bn_sqr_comba8#
 540 .proc   bn_sqr_comba8#
 541 .align  64
 542 bn_sqr_comba8:
 543         .prologue
 544         .save   ar.pfs,r2
 545 #if defined(_HPUX_SOURCE) && !defined(_LP64)
 546 { .mii; alloc   r2=ar.pfs,2,1,0,0
 547         addp4   r33=0,r33
 548         addp4   r32=0,r32               };;
 549 { .mii;
 550 #else
 551 { .mii; alloc   r2=ar.pfs,2,1,0,0
 552 #endif
 553         mov     r34=r33
 554         add     r14=8,r33               };;
 555         .body
 556 { .mii; add     r17=8,r34
 557         add     r15=16,r33
 558         add     r18=16,r34              }
 559 { .mfb; add     r16=24,r33
 560         br      .L_cheat_entry_point8   };;
 561 .endp   bn_sqr_comba8#
 562 #endif
 563
 564 #if 1
 565 // I've estimated this routine to run in ~120 ticks, but in reality
 566 // (i.e. according to ar.itc) it takes ~160 ticks. Are those extra
 567 // cycles consumed for instructions fetch? Or did I misinterpret some
 568 // clause in Itanium µ-architecture manual? Comments are welcomed and
 569 // highly appreciated.
 570 //
 571 // On Itanium 2 it takes ~190 ticks. This is because of stalls on
 572 // result from getf.sig. I do nothing about it at this point for
 573 // reasons depicted below.
 574 //
 575 // However! It should be noted that even 160 ticks is darn good result
 576 // as it's over 10 (yes, ten, spelled as t-e-n) times faster than the
 577 // C version (compiled with gcc with inline assembler). I really
 578 // kicked compiler's butt here, didn't I? Yeah! This brings us to the
 579 // following statement. It's damn shame that this routine isn't called
 580 // very often nowadays! According to the profiler most CPU time is
 581 // consumed by bn_mul_add_words called from BN_from_montgomery. In
 582 // order to estimate what we're missing, I've compared the performance
 583 // of this routine against "traditional" implementation, i.e. against
 584 // following routine:
 585 //
 586 // void bn_mul_comba8(BN_ULONG *r, BN_ULONG *a, BN_ULONG *b)
 587 // {    r[ 8]=bn_mul_words(    &(r[0]),a,8,b[0]);
 588 //      r[ 9]=bn_mul_add_words(&(r[1]),a,8,b[1]);
 589 //      r[10]=bn_mul_add_words(&(r[2]),a,8,b[2]);
 590 //      r[11]=bn_mul_add_words(&(r[3]),a,8,b[3]);
 591 //      r[12]=bn_mul_add_words(&(r[4]),a,8,b[4]);
 592 //      r[13]=bn_mul_add_words(&(r[5]),a,8,b[5]);
 593 //      r[14]=bn_mul_add_words(&(r[6]),a,8,b[6]);
 594 //      r[15]=bn_mul_add_words(&(r[7]),a,8,b[7]);
 595 // }
 596 //
 597 // The one below is over 8 times faster than the one above:-( Even
 598 // more reasons to "combafy" bn_mul_add_mont...
 599 //
 600 // And yes, this routine really made me wish there were an optimizing
 601 // assembler! It also feels like it deserves a dedication.
 602 //
 603 //      To my wife for being there and to my kids...
 604 //
 605 // void bn_mul_comba8(BN_ULONG *r, BN_ULONG *a, BN_ULONG *b)
 606 //
 607 #define carry1  r14
 608 #define carry2  r15
 609 #define carry3  r34
 610 .global bn_mul_comba8#
 611 .proc   bn_mul_comba8#
 612 .align  64
 613 bn_mul_comba8:
 614         .prologue
 615         .save   ar.pfs,r2
 616 #if defined(_HPUX_SOURCE) && !defined(_LP64)
 617 { .mii; alloc   r2=ar.pfs,3,0,0,0
 618         addp4   r33=0,r33
 619         addp4   r34=0,r34               };;
 620 { .mii; addp4   r32=0,r32
 621 #else
 622 { .mii; alloc   r2=ar.pfs,3,0,0,0
 623 #endif
 624         add     r14=8,r33
 625         add     r17=8,r34               }
 626         .body
 627 { .mii; add     r15=16,r33
 628         add     r18=16,r34
 629         add     r16=24,r33              }
 630 .L_cheat_entry_point8:
 631 { .mmi; add     r19=24,r34
 632
 633         ldf8    f32=[r33],32            };;
 634
 635 { .mmi; ldf8    f120=[r34],32
 636         ldf8    f121=[r17],32           }
 637 { .mmi; ldf8    f122=[r18],32
 638         ldf8    f123=[r19],32           };;
 639 { .mmi; ldf8    f124=[r34]
 640         ldf8    f125=[r17]              }
 641 { .mmi; ldf8    f126=[r18]
 642         ldf8    f127=[r19]              }
 643
 644 { .mmi; ldf8    f33=[r14],32
 645         ldf8    f34=[r15],32            }
 646 { .mmi; ldf8    f35=[r16],32;;
 647         ldf8    f36=[r33]               }
 648 { .mmi; ldf8    f37=[r14]
 649         ldf8    f38=[r15]               }
 650 { .mfi; ldf8    f39=[r16]
 651 // -------\ Entering multiplier's heaven /-------
 652 // ------------\                    /------------
 653 // -----------------\          /-----------------
 654 // ----------------------\/----------------------
 655                 xma.hu  f41=f32,f120,f0         }
 656 { .mfi;         xma.lu  f40=f32,f120,f0         };; // (*)
 657 { .mfi;         xma.hu  f51=f32,f121,f0         }
 658 { .mfi;         xma.lu  f50=f32,f121,f0         };;
 659 { .mfi;         xma.hu  f61=f32,f122,f0         }
 660 { .mfi;         xma.lu  f60=f32,f122,f0         };;
 661 { .mfi;         xma.hu  f71=f32,f123,f0         }
 662 { .mfi;         xma.lu  f70=f32,f123,f0         };;
 663 { .mfi;         xma.hu  f81=f32,f124,f0         }
 664 { .mfi;         xma.lu  f80=f32,f124,f0         };;
 665 { .mfi;         xma.hu  f91=f32,f125,f0         }
 666 { .mfi;         xma.lu  f90=f32,f125,f0         };;
 667 { .mfi;         xma.hu  f101=f32,f126,f0        }
 668 { .mfi;         xma.lu  f100=f32,f126,f0        };;
 669 { .mfi;         xma.hu  f111=f32,f127,f0        }
 670 { .mfi;         xma.lu  f110=f32,f127,f0        };;//
 671 // (*)  You can argue that splitting at every second bundle would
 672 //      prevent "wider" IA-64 implementations from achieving the peak
 673 //      performance. Well, not really... The catch is that if you
 674 //      intend to keep 4 FP units busy by splitting at every fourth
 675 //      bundle and thus perform these 16 multiplications in 4 ticks,
 676 //      the first bundle *below* would stall because the result from
 677 //      the first xma bundle *above* won't be available for another 3
 678 //      ticks (if not more, being an optimist, I assume that "wider"
 679 //      implementation will have same latency:-). This stall will hold
 680 //      you back and the performance would be as if every second bundle
 681 //      were split *anyway*...
 682 { .mfi; getf.sig        r16=f40
 683                 xma.hu  f42=f33,f120,f41
 684         add             r33=8,r32               }
 685 { .mfi;         xma.lu  f41=f33,f120,f41        };;
 686 { .mfi; getf.sig        r24=f50
 687                 xma.hu  f52=f33,f121,f51        }
 688 { .mfi;         xma.lu  f51=f33,f121,f51        };;
 689 { .mfi; st8             [r32]=r16,16
 690                 xma.hu  f62=f33,f122,f61        }
 691 { .mfi;         xma.lu  f61=f33,f122,f61        };;
 692 { .mfi;         xma.hu  f72=f33,f123,f71        }
 693 { .mfi;         xma.lu  f71=f33,f123,f71        };;
 694 { .mfi;         xma.hu  f82=f33,f124,f81        }
 695 { .mfi;         xma.lu  f81=f33,f124,f81        };;
 696 { .mfi;         xma.hu  f92=f33,f125,f91        }
 697 { .mfi;         xma.lu  f91=f33,f125,f91        };;
 698 { .mfi;         xma.hu  f102=f33,f126,f101      }
 699 { .mfi;         xma.lu  f101=f33,f126,f101      };;
 700 { .mfi;         xma.hu  f112=f33,f127,f111      }
 701 { .mfi;         xma.lu  f111=f33,f127,f111      };;//
 702 //-------------------------------------------------//
 703 { .mfi; getf.sig        r25=f41
 704                 xma.hu  f43=f34,f120,f42        }
 705 { .mfi;         xma.lu  f42=f34,f120,f42        };;
 706 { .mfi; getf.sig        r16=f60
 707                 xma.hu  f53=f34,f121,f52        }
 708 { .mfi;         xma.lu  f52=f34,f121,f52        };;
 709 { .mfi; getf.sig        r17=f51
 710                 xma.hu  f63=f34,f122,f62
 711         add             r25=r25,r24             }
 712 { .mfi;         xma.lu  f62=f34,f122,f62
 713         mov             carry1=0                };;
 714 { .mfi; cmp.ltu         p6,p0=r25,r24
 715                 xma.hu  f73=f34,f123,f72        }
 716 { .mfi;         xma.lu  f72=f34,f123,f72        };;
 717 { .mfi; st8             [r33]=r25,16
 718                 xma.hu  f83=f34,f124,f82
 719 (p6)    add             carry1=1,carry1         }
 720 { .mfi;         xma.lu  f82=f34,f124,f82        };;
 721 { .mfi;         xma.hu  f93=f34,f125,f92        }
 722 { .mfi;         xma.lu  f92=f34,f125,f92        };;
 723 { .mfi;         xma.hu  f103=f34,f126,f102      }
 724 { .mfi;         xma.lu  f102=f34,f126,f102      };;
 725 { .mfi;         xma.hu  f113=f34,f127,f112      }
 726 { .mfi;         xma.lu  f112=f34,f127,f112      };;//
 727 //-------------------------------------------------//
 728 { .mfi; getf.sig        r18=f42
 729                 xma.hu  f44=f35,f120,f43
 730         add             r17=r17,r16             }
 731 { .mfi;         xma.lu  f43=f35,f120,f43        };;
 732 { .mfi; getf.sig        r24=f70
 733                 xma.hu  f54=f35,f121,f53        }
 734 { .mfi; mov             carry2=0
 735                 xma.lu  f53=f35,f121,f53        };;
 736 { .mfi; getf.sig        r25=f61
 737                 xma.hu  f64=f35,f122,f63
 738         cmp.ltu         p7,p0=r17,r16           }
 739 { .mfi; add             r18=r18,r17
 740                 xma.lu  f63=f35,f122,f63        };;
 741 { .mfi; getf.sig        r26=f52
 742                 xma.hu  f74=f35,f123,f73
 743 (p7)    add             carry2=1,carry2         }
 744 { .mfi; cmp.ltu         p7,p0=r18,r17
 745                 xma.lu  f73=f35,f123,f73
 746         add             r18=r18,carry1          };;
 747 { .mfi;
 748                 xma.hu  f84=f35,f124,f83
 749 (p7)    add             carry2=1,carry2         }
 750 { .mfi; cmp.ltu         p7,p0=r18,carry1
 751                 xma.lu  f83=f35,f124,f83        };;
 752 { .mfi; st8             [r32]=r18,16
 753                 xma.hu  f94=f35,f125,f93
 754 (p7)    add             carry2=1,carry2         }
 755 { .mfi;         xma.lu  f93=f35,f125,f93        };;
 756 { .mfi;         xma.hu  f104=f35,f126,f103      }
 757 { .mfi;         xma.lu  f103=f35,f126,f103      };;
 758 { .mfi;         xma.hu  f114=f35,f127,f113      }
 759 { .mfi; mov             carry1=0
 760                 xma.lu  f113=f35,f127,f113
 761         add             r25=r25,r24             };;//
 762 //-------------------------------------------------//
 763 { .mfi; getf.sig        r27=f43
 764                 xma.hu  f45=f36,f120,f44
 765         cmp.ltu         p6,p0=r25,r24           }
 766 { .mfi;         xma.lu  f44=f36,f120,f44
 767         add             r26=r26,r25             };;
 768 { .mfi; getf.sig        r16=f80
 769                 xma.hu  f55=f36,f121,f54
 770 (p6)    add             carry1=1,carry1         }
 771 { .mfi;         xma.lu  f54=f36,f121,f54        };;
 772 { .mfi; getf.sig        r17=f71
 773                 xma.hu  f65=f36,f122,f64
 774         cmp.ltu         p6,p0=r26,r25           }
 775 { .mfi;         xma.lu  f64=f36,f122,f64
 776         add             r27=r27,r26             };;
 777 { .mfi; getf.sig        r18=f62
 778                 xma.hu  f75=f36,f123,f74
 779 (p6)    add             carry1=1,carry1         }
 780 { .mfi; cmp.ltu         p6,p0=r27,r26
 781                 xma.lu  f74=f36,f123,f74
 782         add             r27=r27,carry2          };;
 783 { .mfi; getf.sig        r19=f53
 784                 xma.hu  f85=f36,f124,f84
 785 (p6)    add             carry1=1,carry1         }
 786 { .mfi;         xma.lu  f84=f36,f124,f84
 787         cmp.ltu         p6,p0=r27,carry2        };;
 788 { .mfi; st8             [r33]=r27,16
 789                 xma.hu  f95=f36,f125,f94
 790 (p6)    add             carry1=1,carry1         }
 791 { .mfi;         xma.lu  f94=f36,f125,f94        };;
 792 { .mfi;         xma.hu  f105=f36,f126,f104      }
 793 { .mfi; mov             carry2=0
 794                 xma.lu  f104=f36,f126,f104
 795         add             r17=r17,r16             };;
 796 { .mfi;         xma.hu  f115=f36,f127,f114
 797         cmp.ltu         p7,p0=r17,r16           }
 798 { .mfi;         xma.lu  f114=f36,f127,f114
 799         add             r18=r18,r17             };;//
 800 //-------------------------------------------------//
 801 { .mfi; getf.sig        r20=f44
 802                 xma.hu  f46=f37,f120,f45
 803 (p7)    add             carry2=1,carry2         }
 804 { .mfi; cmp.ltu         p7,p0=r18,r17
 805                 xma.lu  f45=f37,f120,f45
 806         add             r19=r19,r18             };;
 807 { .mfi; getf.sig        r24=f90
 808                 xma.hu  f56=f37,f121,f55        }
 809 { .mfi;         xma.lu  f55=f37,f121,f55        };;
 810 { .mfi; getf.sig        r25=f81
 811                 xma.hu  f66=f37,f122,f65
 812 (p7)    add             carry2=1,carry2         }
 813 { .mfi; cmp.ltu         p7,p0=r19,r18
 814                 xma.lu  f65=f37,f122,f65
 815         add             r20=r20,r19             };;
 816 { .mfi; getf.sig        r26=f72
 817                 xma.hu  f76=f37,f123,f75
 818 (p7)    add             carry2=1,carry2         }
 819 { .mfi; cmp.ltu         p7,p0=r20,r19
 820                 xma.lu  f75=f37,f123,f75
 821         add             r20=r20,carry1          };;
 822 { .mfi; getf.sig        r27=f63
 823                 xma.hu  f86=f37,f124,f85
 824 (p7)    add             carry2=1,carry2         }
 825 { .mfi;         xma.lu  f85=f37,f124,f85
 826         cmp.ltu         p7,p0=r20,carry1        };;
 827 { .mfi; getf.sig        r28=f54
 828                 xma.hu  f96=f37,f125,f95
 829 (p7)    add             carry2=1,carry2         }
 830 { .mfi; st8             [r32]=r20,16
 831                 xma.lu  f95=f37,f125,f95        };;
 832 { .mfi;         xma.hu  f106=f37,f126,f105      }
 833 { .mfi; mov             carry1=0
 834                 xma.lu  f105=f37,f126,f105
 835         add             r25=r25,r24             };;
 836 { .mfi;         xma.hu  f116=f37,f127,f115
 837         cmp.ltu         p6,p0=r25,r24           }
 838 { .mfi;         xma.lu  f115=f37,f127,f115
 839         add             r26=r26,r25             };;//
 840 //-------------------------------------------------//
 841 { .mfi; getf.sig        r29=f45
 842                 xma.hu  f47=f38,f120,f46
 843 (p6)    add             carry1=1,carry1         }
 844 { .mfi; cmp.ltu         p6,p0=r26,r25
 845                 xma.lu  f46=f38,f120,f46
 846         add             r27=r27,r26             };;
 847 { .mfi; getf.sig        r16=f100
 848                 xma.hu  f57=f38,f121,f56
 849 (p6)    add             carry1=1,carry1         }
 850 { .mfi; cmp.ltu         p6,p0=r27,r26
 851                 xma.lu  f56=f38,f121,f56
 852         add             r28=r28,r27             };;
 853 { .mfi; getf.sig        r17=f91
 854                 xma.hu  f67=f38,f122,f66
 855 (p6)    add             carry1=1,carry1         }
 856 { .mfi; cmp.ltu         p6,p0=r28,r27
 857                 xma.lu  f66=f38,f122,f66
 858         add             r29=r29,r28             };;
 859 { .mfi; getf.sig        r18=f82
 860                 xma.hu  f77=f38,f123,f76
 861 (p6)    add             carry1=1,carry1         }
 862 { .mfi; cmp.ltu         p6,p0=r29,r28
 863                 xma.lu  f76=f38,f123,f76
 864         add             r29=r29,carry2          };;
 865 { .mfi; getf.sig        r19=f73
 866                 xma.hu  f87=f38,f124,f86
 867 (p6)    add             carry1=1,carry1         }
 868 { .mfi;         xma.lu  f86=f38,f124,f86
 869         cmp.ltu         p6,p0=r29,carry2        };;
 870 { .mfi; getf.sig        r20=f64
 871                 xma.hu  f97=f38,f125,f96
 872 (p6)    add             carry1=1,carry1         }
 873 { .mfi; st8             [r33]=r29,16
 874                 xma.lu  f96=f38,f125,f96        };;
 875 { .mfi; getf.sig        r21=f55
 876                 xma.hu  f107=f38,f126,f106      }
 877 { .mfi; mov             carry2=0
 878                 xma.lu  f106=f38,f126,f106
 879         add             r17=r17,r16             };;
 880 { .mfi;         xma.hu  f117=f38,f127,f116
 881         cmp.ltu         p7,p0=r17,r16           }
 882 { .mfi;         xma.lu  f116=f38,f127,f116
 883         add             r18=r18,r17             };;//
 884 //-------------------------------------------------//
 885 { .mfi; getf.sig        r22=f46
 886                 xma.hu  f48=f39,f120,f47
 887 (p7)    add             carry2=1,carry2         }
 888 { .mfi; cmp.ltu         p7,p0=r18,r17
 889                 xma.lu  f47=f39,f120,f47
 890         add             r19=r19,r18             };;
 891 { .mfi; getf.sig        r24=f110
 892                 xma.hu  f58=f39,f121,f57
 893 (p7)    add             carry2=1,carry2         }
 894 { .mfi; cmp.ltu         p7,p0=r19,r18
 895                 xma.lu  f57=f39,f121,f57
 896         add             r20=r20,r19             };;
 897 { .mfi; getf.sig        r25=f101
 898                 xma.hu  f68=f39,f122,f67
 899 (p7)    add             carry2=1,carry2         }
 900 { .mfi; cmp.ltu         p7,p0=r20,r19
 901                 xma.lu  f67=f39,f122,f67
 902         add             r21=r21,r20             };;
 903 { .mfi; getf.sig        r26=f92
 904                 xma.hu  f78=f39,f123,f77
 905 (p7)    add             carry2=1,carry2         }
 906 { .mfi; cmp.ltu         p7,p0=r21,r20
 907                 xma.lu  f77=f39,f123,f77
 908         add             r22=r22,r21             };;
 909 { .mfi; getf.sig        r27=f83
 910                 xma.hu  f88=f39,f124,f87
 911 (p7)    add             carry2=1,carry2         }
 912 { .mfi; cmp.ltu         p7,p0=r22,r21
 913                 xma.lu  f87=f39,f124,f87
 914         add             r22=r22,carry1          };;
 915 { .mfi; getf.sig        r28=f74
 916                 xma.hu  f98=f39,f125,f97
 917 (p7)    add             carry2=1,carry2         }
 918 { .mfi;         xma.lu  f97=f39,f125,f97
 919         cmp.ltu         p7,p0=r22,carry1        };;
 920 { .mfi; getf.sig        r29=f65
 921                 xma.hu  f108=f39,f126,f107
 922 (p7)    add             carry2=1,carry2         }
 923 { .mfi; st8             [r32]=r22,16
 924                 xma.lu  f107=f39,f126,f107      };;
 925 { .mfi; getf.sig        r30=f56
 926                 xma.hu  f118=f39,f127,f117      }
 927 { .mfi;         xma.lu  f117=f39,f127,f117      };;//
 928 //-------------------------------------------------//
 929 // Leaving muliplier's heaven... Quite a ride, huh?
 930
 931 { .mii; getf.sig        r31=f47
 932         add             r25=r25,r24
 933         mov             carry1=0                };;
 934 { .mii;         getf.sig        r16=f111
 935         cmp.ltu         p6,p0=r25,r24
 936         add             r26=r26,r25             };;
 937 { .mfb;         getf.sig        r17=f102        }
 938 { .mii;
 939 (p6)    add             carry1=1,carry1
 940         cmp.ltu         p6,p0=r26,r25
 941         add             r27=r27,r26             };;
 942 { .mfb; nop.m   0x0                             }
 943 { .mii;
 944 (p6)    add             carry1=1,carry1
 945         cmp.ltu         p6,p0=r27,r26
 946         add             r28=r28,r27             };;
 947 { .mii;         getf.sig        r18=f93
 948                 add             r17=r17,r16
 949                 mov             carry3=0        }
 950 { .mii;
 951 (p6)    add             carry1=1,carry1
 952         cmp.ltu         p6,p0=r28,r27
 953         add             r29=r29,r28             };;
 954 { .mii;         getf.sig        r19=f84
 955                 cmp.ltu         p7,p0=r17,r16   }
 956 { .mii;
 957 (p6)    add             carry1=1,carry1
 958         cmp.ltu         p6,p0=r29,r28
 959         add             r30=r30,r29             };;
 960 { .mii;         getf.sig        r20=f75
 961                 add             r18=r18,r17     }
 962 { .mii;
 963 (p6)    add             carry1=1,carry1
 964         cmp.ltu         p6,p0=r30,r29
 965         add             r31=r31,r30             };;
 966 { .mfb;         getf.sig        r21=f66         }
 967 { .mii; (p7)    add             carry3=1,carry3
 968                 cmp.ltu         p7,p0=r18,r17
 969                 add             r19=r19,r18     }
 970 { .mfb; nop.m   0x0                             }
 971 { .mii;
 972 (p6)    add             carry1=1,carry1
 973         cmp.ltu         p6,p0=r31,r30
 974         add             r31=r31,carry2          };;
 975 { .mfb;         getf.sig        r22=f57         }
 976 { .mii; (p7)    add             carry3=1,carry3
 977                 cmp.ltu         p7,p0=r19,r18
 978                 add             r20=r20,r19     }
 979 { .mfb; nop.m   0x0                             }
 980 { .mii;
 981 (p6)    add             carry1=1,carry1
 982         cmp.ltu         p6,p0=r31,carry2        };;
 983 { .mfb;         getf.sig        r23=f48         }
 984 { .mii; (p7)    add             carry3=1,carry3
 985                 cmp.ltu         p7,p0=r20,r19
 986                 add             r21=r21,r20     }
 987 { .mii;
 988 (p6)    add             carry1=1,carry1         }
 989 { .mfb; st8             [r33]=r31,16            };;
 990
 991 { .mfb; getf.sig        r24=f112                }
 992 { .mii; (p7)    add             carry3=1,carry3
 993                 cmp.ltu         p7,p0=r21,r20
 994                 add             r22=r22,r21     };;
 995 { .mfb; getf.sig        r25=f103                }
 996 { .mii; (p7)    add             carry3=1,carry3
 997                 cmp.ltu         p7,p0=r22,r21
 998                 add             r23=r23,r22     };;
 999 { .mfb; getf.sig        r26=f94                 }
1000 { .mii; (p7)    add             carry3=1,carry3
1001                 cmp.ltu         p7,p0=r23,r22
1002                 add             r23=r23,carry1  };;
1003 { .mfb; getf.sig        r27=f85                 }
1004 { .mii; (p7)    add             carry3=1,carry3
1005                 cmp.ltu         p7,p8=r23,carry1};;
1006 { .mii; getf.sig        r28=f76
1007         add             r25=r25,r24
1008         mov             carry1=0                }
1009 { .mii;         st8             [r32]=r23,16
1010         (p7)    add             carry2=1,carry3
1011         (p8)    add             carry2=0,carry3 };;
1012
1013 { .mfb; nop.m   0x0                             }
1014 { .mii; getf.sig        r29=f67
1015         cmp.ltu         p6,p0=r25,r24
1016         add             r26=r26,r25             };;
1017 { .mfb; getf.sig        r30=f58                 }
1018 { .mii;
1019 (p6)    add             carry1=1,carry1
1020         cmp.ltu         p6,p0=r26,r25
1021         add             r27=r27,r26             };;
1022 { .mfb;         getf.sig        r16=f113        }
1023 { .mii;
1024 (p6)    add             carry1=1,carry1
1025         cmp.ltu         p6,p0=r27,r26
1026         add             r28=r28,r27             };;
1027 { .mfb;         getf.sig        r17=f104        }
1028 { .mii;
1029 (p6)    add             carry1=1,carry1
1030         cmp.ltu         p6,p0=r28,r27
1031         add             r29=r29,r28             };;
1032 { .mfb;         getf.sig        r18=f95         }
1033 { .mii;
1034 (p6)    add             carry1=1,carry1
1035         cmp.ltu         p6,p0=r29,r28
1036         add             r30=r30,r29             };;
1037 { .mii;         getf.sig        r19=f86
1038                 add             r17=r17,r16
1039                 mov             carry3=0        }
1040 { .mii;
1041 (p6)    add             carry1=1,carry1
1042         cmp.ltu         p6,p0=r30,r29
1043         add             r30=r30,carry2          };;
1044 { .mii;         getf.sig        r20=f77
1045                 cmp.ltu         p7,p0=r17,r16
1046                 add             r18=r18,r17     }
1047 { .mii;
1048 (p6)    add             carry1=1,carry1
1049         cmp.ltu         p6,p0=r30,carry2        };;
1050 { .mfb;         getf.sig        r21=f68         }
1051 { .mii; st8             [r33]=r30,16
1052 (p6)    add             carry1=1,carry1         };;
1053
1054 { .mfb; getf.sig        r24=f114                }
1055 { .mii; (p7)    add             carry3=1,carry3
1056                 cmp.ltu         p7,p0=r18,r17
1057                 add             r19=r19,r18     };;
1058 { .mfb; getf.sig        r25=f105                }
1059 { .mii; (p7)    add             carry3=1,carry3
1060                 cmp.ltu         p7,p0=r19,r18
1061                 add             r20=r20,r19     };;
1062 { .mfb; getf.sig        r26=f96                 }
1063 { .mii; (p7)    add             carry3=1,carry3
1064                 cmp.ltu         p7,p0=r20,r19
1065                 add             r21=r21,r20     };;
1066 { .mfb; getf.sig        r27=f87                 }
1067 { .mii; (p7)    add             carry3=1,carry3
1068                 cmp.ltu         p7,p0=r21,r20
1069                 add             r21=r21,carry1  };;
1070 { .mib; getf.sig        r28=f78
1071         add             r25=r25,r24             }
1072 { .mib; (p7)    add             carry3=1,carry3
1073                 cmp.ltu         p7,p8=r21,carry1};;
1074 { .mii;         st8             [r32]=r21,16
1075         (p7)    add             carry2=1,carry3
1076         (p8)    add             carry2=0,carry3 }
1077
1078 { .mii; mov             carry1=0
1079         cmp.ltu         p6,p0=r25,r24
1080         add             r26=r26,r25             };;
1081 { .mfb;         getf.sig        r16=f115        }
1082 { .mii;
1083 (p6)    add             carry1=1,carry1
1084         cmp.ltu         p6,p0=r26,r25
1085         add             r27=r27,r26             };;
1086 { .mfb;         getf.sig        r17=f106        }
1087 { .mii;
1088 (p6)    add             carry1=1,carry1
1089         cmp.ltu         p6,p0=r27,r26
1090         add             r28=r28,r27             };;
1091 { .mfb;         getf.sig        r18=f97         }
1092 { .mii;
1093 (p6)    add             carry1=1,carry1
1094         cmp.ltu         p6,p0=r28,r27
1095         add             r28=r28,carry2          };;
1096 { .mib;         getf.sig        r19=f88
1097                 add             r17=r17,r16     }
1098 { .mib;
1099 (p6)    add             carry1=1,carry1
1100         cmp.ltu         p6,p0=r28,carry2        };;
1101 { .mii; st8             [r33]=r28,16
1102 (p6)    add             carry1=1,carry1         }
1103
1104 { .mii;         mov             carry2=0
1105                 cmp.ltu         p7,p0=r17,r16
1106                 add             r18=r18,r17     };;
1107 { .mfb; getf.sig        r24=f116                }
1108 { .mii; (p7)    add             carry2=1,carry2
1109                 cmp.ltu         p7,p0=r18,r17
1110                 add             r19=r19,r18     };;
1111 { .mfb; getf.sig        r25=f107                }
1112 { .mii; (p7)    add             carry2=1,carry2
1113                 cmp.ltu         p7,p0=r19,r18
1114                 add             r19=r19,carry1  };;
1115 { .mfb; getf.sig        r26=f98                 }
1116 { .mii; (p7)    add             carry2=1,carry2
1117                 cmp.ltu         p7,p0=r19,carry1};;
1118 { .mii;         st8             [r32]=r19,16
1119         (p7)    add             carry2=1,carry2 }
1120
1121 { .mfb; add             r25=r25,r24             };;
1122
1123 { .mfb;         getf.sig        r16=f117        }
1124 { .mii; mov             carry1=0
1125         cmp.ltu         p6,p0=r25,r24
1126         add             r26=r26,r25             };;
1127 { .mfb;         getf.sig        r17=f108        }
1128 { .mii;
1129 (p6)    add             carry1=1,carry1
1130         cmp.ltu         p6,p0=r26,r25
1131         add             r26=r26,carry2          };;
1132 { .mfb; nop.m   0x0                             }
1133 { .mii;
1134 (p6)    add             carry1=1,carry1
1135         cmp.ltu         p6,p0=r26,carry2        };;
1136 { .mii; st8             [r33]=r26,16
1137 (p6)    add             carry1=1,carry1         }
1138
1139 { .mfb;         add             r17=r17,r16     };;
1140 { .mfb; getf.sig        r24=f118                }
1141 { .mii;         mov             carry2=0
1142                 cmp.ltu         p7,p0=r17,r16
1143                 add             r17=r17,carry1  };;
1144 { .mii; (p7)    add             carry2=1,carry2
1145                 cmp.ltu         p7,p0=r17,carry1};;
1146 { .mii;         st8             [r32]=r17
1147         (p7)    add             carry2=1,carry2 };;
1148 { .mfb; add             r24=r24,carry2          };;
1149 { .mib; st8             [r33]=r24               }
1150
1151 { .mib; rum             1<<5            // clear um.mfh
1152         br.ret.sptk.many        b0      };;
1153 .endp   bn_mul_comba8#
1154 #undef  carry3
1155 #undef  carry2
1156 #undef  carry1
1157 #endif
1158
1159 #if 1
1160 // It's possible to make it faster (see comment to bn_sqr_comba8), but
1161 // I reckon it doesn't worth the effort. Basically because the routine
1162 // (actually both of them) practically never called... So I just play
1163 // same trick as with bn_sqr_comba8.
1164 //
1165 // void bn_sqr_comba4(BN_ULONG *r, BN_ULONG *a)
1166 //
1167 .global bn_sqr_comba4#
1168 .proc   bn_sqr_comba4#
1169 .align  64
1170 bn_sqr_comba4:
1171         .prologue
1172         .save   ar.pfs,r2
1173 #if defined(_HPUX_SOURCE) && !defined(_LP64)
1174 { .mii; alloc   r2=ar.pfs,2,1,0,0
1175         addp4   r32=0,r32
1176         addp4   r33=0,r33               };;
1177 { .mii;
1178 #else
1179 { .mii; alloc   r2=ar.pfs,2,1,0,0
1180 #endif
1181         mov     r34=r33
1182         add     r14=8,r33               };;
1183         .body
1184 { .mii; add     r17=8,r34
1185         add     r15=16,r33
1186         add     r18=16,r34              }
1187 { .mfb; add     r16=24,r33
1188         br      .L_cheat_entry_point4   };;
1189 .endp   bn_sqr_comba4#
1190 #endif
1191
1192 #if 1
1193 // Runs in ~115 cycles and ~4.5 times faster than C. Well, whatever...
1194 //
1195 // void bn_mul_comba4(BN_ULONG *r, BN_ULONG *a, BN_ULONG *b)
1196 //
1197 #define carry1  r14
1198 #define carry2  r15
1199 .global bn_mul_comba4#
1200 .proc   bn_mul_comba4#
1201 .align  64
1202 bn_mul_comba4:
1203         .prologue
1204         .save   ar.pfs,r2
1205 #if defined(_HPUX_SOURCE) && !defined(_LP64)
1206 { .mii; alloc   r2=ar.pfs,3,0,0,0
1207         addp4   r33=0,r33
1208         addp4   r34=0,r34               };;
1209 { .mii; addp4   r32=0,r32
1210 #else
1211 { .mii; alloc   r2=ar.pfs,3,0,0,0
1212 #endif
1213         add     r14=8,r33
1214         add     r17=8,r34               }
1215         .body
1216 { .mii; add     r15=16,r33
1217         add     r18=16,r34
1218         add     r16=24,r33              };;
1219 .L_cheat_entry_point4:
1220 { .mmi; add     r19=24,r34
1221
1222         ldf8    f32=[r33]               }
1223
1224 { .mmi; ldf8    f120=[r34]
1225         ldf8    f121=[r17]              };;
1226 { .mmi; ldf8    f122=[r18]
1227         ldf8    f123=[r19]              }
1228
1229 { .mmi; ldf8    f33=[r14]
1230         ldf8    f34=[r15]               }
1231 { .mfi; ldf8    f35=[r16]
1232
1233                 xma.hu  f41=f32,f120,f0         }
1234 { .mfi;         xma.lu  f40=f32,f120,f0         };;
1235 { .mfi;         xma.hu  f51=f32,f121,f0         }
1236 { .mfi;         xma.lu  f50=f32,f121,f0         };;
1237 { .mfi;         xma.hu  f61=f32,f122,f0         }
1238 { .mfi;         xma.lu  f60=f32,f122,f0         };;
1239 { .mfi;         xma.hu  f71=f32,f123,f0         }
1240 { .mfi;         xma.lu  f70=f32,f123,f0         };;//
1241 // Major stall takes place here, and 3 more places below. Result from
1242 // first xma is not available for another 3 ticks.
1243 { .mfi; getf.sig        r16=f40
1244                 xma.hu  f42=f33,f120,f41
1245         add             r33=8,r32               }
1246 { .mfi;         xma.lu  f41=f33,f120,f41        };;
1247 { .mfi; getf.sig        r24=f50
1248                 xma.hu  f52=f33,f121,f51        }
1249 { .mfi;         xma.lu  f51=f33,f121,f51        };;
1250 { .mfi; st8             [r32]=r16,16
1251                 xma.hu  f62=f33,f122,f61        }
1252 { .mfi;         xma.lu  f61=f33,f122,f61        };;
1253 { .mfi;         xma.hu  f72=f33,f123,f71        }
1254 { .mfi;         xma.lu  f71=f33,f123,f71        };;//
1255 //-------------------------------------------------//
1256 { .mfi; getf.sig        r25=f41
1257                 xma.hu  f43=f34,f120,f42        }
1258 { .mfi;         xma.lu  f42=f34,f120,f42        };;
1259 { .mfi; getf.sig        r16=f60
1260                 xma.hu  f53=f34,f121,f52        }
1261 { .mfi;         xma.lu  f52=f34,f121,f52        };;
1262 { .mfi; getf.sig        r17=f51
1263                 xma.hu  f63=f34,f122,f62
1264         add             r25=r25,r24             }
1265 { .mfi; mov             carry1=0
1266                 xma.lu  f62=f34,f122,f62        };;
1267 { .mfi; st8             [r33]=r25,16
1268                 xma.hu  f73=f34,f123,f72
1269         cmp.ltu         p6,p0=r25,r24           }
1270 { .mfi;         xma.lu  f72=f34,f123,f72        };;//
1271 //-------------------------------------------------//
1272 { .mfi; getf.sig        r18=f42
1273                 xma.hu  f44=f35,f120,f43
1274 (p6)    add             carry1=1,carry1         }
1275 { .mfi; add             r17=r17,r16
1276                 xma.lu  f43=f35,f120,f43
1277         mov             carry2=0                };;
1278 { .mfi; getf.sig        r24=f70
1279                 xma.hu  f54=f35,f121,f53
1280         cmp.ltu         p7,p0=r17,r16           }
1281 { .mfi;         xma.lu  f53=f35,f121,f53        };;
1282 { .mfi; getf.sig        r25=f61
1283                 xma.hu  f64=f35,f122,f63
1284         add             r18=r18,r17             }
1285 { .mfi;         xma.lu  f63=f35,f122,f63
1286 (p7)    add             carry2=1,carry2         };;
1287 { .mfi; getf.sig        r26=f52
1288                 xma.hu  f74=f35,f123,f73
1289         cmp.ltu         p7,p0=r18,r17           }
1290 { .mfi;         xma.lu  f73=f35,f123,f73
1291         add             r18=r18,carry1          };;
1292 //-------------------------------------------------//
1293 { .mii; st8             [r32]=r18,16
1294 (p7)    add             carry2=1,carry2
1295         cmp.ltu         p7,p0=r18,carry1        };;
1296
1297 { .mfi; getf.sig        r27=f43 // last major stall
1298 (p7)    add             carry2=1,carry2         };;
1299 { .mii;         getf.sig        r16=f71
1300         add             r25=r25,r24
1301         mov             carry1=0                };;
1302 { .mii;         getf.sig        r17=f62
1303         cmp.ltu         p6,p0=r25,r24
1304         add             r26=r26,r25             };;
1305 { .mii;
1306 (p6)    add             carry1=1,carry1
1307         cmp.ltu         p6,p0=r26,r25
1308         add             r27=r27,r26             };;
1309 { .mii;
1310 (p6)    add             carry1=1,carry1
1311         cmp.ltu         p6,p0=r27,r26
1312         add             r27=r27,carry2          };;
1313 { .mii;         getf.sig        r18=f53
1314 (p6)    add             carry1=1,carry1
1315         cmp.ltu         p6,p0=r27,carry2        };;
1316 { .mfi; st8             [r33]=r27,16
1317 (p6)    add             carry1=1,carry1         }
1318
1319 { .mii;         getf.sig        r19=f44
1320                 add             r17=r17,r16
1321                 mov             carry2=0        };;
1322 { .mii; getf.sig        r24=f72
1323                 cmp.ltu         p7,p0=r17,r16
1324                 add             r18=r18,r17     };;
1325 { .mii; (p7)    add             carry2=1,carry2
1326                 cmp.ltu         p7,p0=r18,r17
1327                 add             r19=r19,r18     };;
1328 { .mii; (p7)    add             carry2=1,carry2
1329                 cmp.ltu         p7,p0=r19,r18
1330                 add             r19=r19,carry1  };;
1331 { .mii; getf.sig        r25=f63
1332         (p7)    add             carry2=1,carry2
1333                 cmp.ltu         p7,p0=r19,carry1};;
1334 { .mii;         st8             [r32]=r19,16
1335         (p7)    add             carry2=1,carry2 }
1336
1337 { .mii; getf.sig        r26=f54
1338         add             r25=r25,r24
1339         mov             carry1=0                };;
1340 { .mii;         getf.sig        r16=f73
1341         cmp.ltu         p6,p0=r25,r24
1342         add             r26=r26,r25             };;
1343 { .mii;
1344 (p6)    add             carry1=1,carry1
1345         cmp.ltu         p6,p0=r26,r25
1346         add             r26=r26,carry2          };;
1347 { .mii;         getf.sig        r17=f64
1348 (p6)    add             carry1=1,carry1
1349         cmp.ltu         p6,p0=r26,carry2        };;
1350 { .mii; st8             [r33]=r26,16
1351 (p6)    add             carry1=1,carry1         }
1352
1353 { .mii; getf.sig        r24=f74
1354                 add             r17=r17,r16
1355                 mov             carry2=0        };;
1356 { .mii;         cmp.ltu         p7,p0=r17,r16
1357                 add             r17=r17,carry1  };;
1358
1359 { .mii; (p7)    add             carry2=1,carry2
1360                 cmp.ltu         p7,p0=r17,carry1};;
1361 { .mii;         st8             [r32]=r17,16
1362         (p7)    add             carry2=1,carry2 };;
1363
1364 { .mii; add             r24=r24,carry2          };;
1365 { .mii; st8             [r33]=r24               }
1366
1367 { .mib; rum             1<<5            // clear um.mfh
1368         br.ret.sptk.many        b0      };;
1369 .endp   bn_mul_comba4#
1370 #undef  carry2
1371 #undef  carry1
1372 #endif
1373
1374 #if 1
1375 //
1376 // BN_ULONG bn_div_words(BN_ULONG h, BN_ULONG l, BN_ULONG d)
1377 //
1378 // In the nutshell it's a port of my MIPS III/IV implementation.
1379 //
1380 #define AT      r14
1381 #define H       r16
1382 #define HH      r20
1383 #define L       r17
1384 #define D       r18
1385 #define DH      r22
1386 #define I       r21
1387
1388 #if 0
1389 // Some preprocessors (most notably HP-UX) appear to be allergic to
1390 // macros enclosed to parenthesis [as these three were].
1391 #define cont    p16
1392 #define break   p0      // p20
1393 #define equ     p24
1394 #else
1395 cont=p16
1396 break=p0
1397 equ=p24
1398 #endif
1399
1400 .global abort#
1401 .global bn_div_words#
1402 .proc   bn_div_words#
1403 .align  64
1404 bn_div_words:
1405         .prologue
1406         .save   ar.pfs,r2
1407 { .mii; alloc           r2=ar.pfs,3,5,0,8
1408         .save   b0,r3
1409         mov             r3=b0
1410         mov             r10=pr          };;
1411 { .mmb; cmp.eq          p6,p0=r34,r0
1412         mov             r8=-1
1413 (p6)    br.ret.spnt.many        b0      };;
1414
1415         .body
1416 { .mii; mov             H=r32           // save h
1417         mov             ar.ec=0         // don't rotate at exit
1418         mov             pr.rot=0        }
1419 { .mii; mov             L=r33           // save l
1420         mov             r36=r0          };;
1421
1422 .L_divw_shift:  // -vv- note signed comparison
1423 { .mfi; (p0)    cmp.lt          p16,p0=r0,r34   // d
1424         (p0)    shladd          r33=r34,1,r0    }
1425 { .mfb; (p0)    add             r35=1,r36
1426         (p0)    nop.f           0x0
1427 (p16)   br.wtop.dpnt            .L_divw_shift   };;
1428
1429 { .mii; mov             D=r34
1430         shr.u           DH=r34,32
1431         sub             r35=64,r36              };;
1432 { .mii; setf.sig        f7=DH
1433         shr.u           AT=H,r35
1434         mov             I=r36                   };;
1435 { .mib; cmp.ne          p6,p0=r0,AT
1436         shl             H=H,r36
1437 (p6)    br.call.spnt.clr        b0=abort        };;     // overflow, die...
1438
1439 { .mfi; fcvt.xuf.s1     f7=f7
1440         shr.u           AT=L,r35                };;
1441 { .mii; shl             L=L,r36
1442         or              H=H,AT                  };;
1443
1444 { .mii; nop.m           0x0
1445         cmp.leu         p6,p0=D,H;;
1446 (p6)    sub             H=H,D                   }
1447
1448 { .mlx; setf.sig        f14=D
1449         movl            AT=0xffffffff           };;
1450 ///////////////////////////////////////////////////////////
1451 { .mii; setf.sig        f6=H
1452         shr.u           HH=H,32;;
1453         cmp.eq          p6,p7=HH,DH             };;
1454 { .mfb;
1455 (p6)    setf.sig        f8=AT
1456 (p7)    fcvt.xuf.s1     f6=f6
1457 (p7)    br.call.sptk    b6=.L_udiv64_32_b6      };;
1458
1459 { .mfi; getf.sig        r33=f8                          // q
1460         xmpy.lu         f9=f8,f14               }
1461 { .mfi; xmpy.hu         f10=f8,f14
1462         shrp            H=H,L,32                };;
1463
1464 { .mmi; getf.sig        r35=f9                          // tl
1465         getf.sig        r31=f10                 };;     // th
1466
1467 .L_divw_1st_iter:
1468 { .mii; (p0)    add             r32=-1,r33
1469         (p0)    cmp.eq          equ,cont=HH,r31         };;
1470 { .mii; (p0)    cmp.ltu         p8,p0=r35,D
1471         (p0)    sub             r34=r35,D
1472         (equ)   cmp.leu         break,cont=r35,H        };;
1473 { .mib; (cont)  cmp.leu         cont,break=HH,r31
1474         (p8)    add             r31=-1,r31
1475 (cont)  br.wtop.spnt            .L_divw_1st_iter        };;
1476 ///////////////////////////////////////////////////////////
1477 { .mii; sub             H=H,r35
1478         shl             r8=r33,32
1479         shl             L=L,32                  };;
1480 ///////////////////////////////////////////////////////////
1481 { .mii; setf.sig        f6=H
1482         shr.u           HH=H,32;;
1483         cmp.eq          p6,p7=HH,DH             };;
1484 { .mfb;
1485 (p6)    setf.sig        f8=AT
1486 (p7)    fcvt.xuf.s1     f6=f6
1487 (p7)    br.call.sptk    b6=.L_udiv64_32_b6      };;
1488
1489 { .mfi; getf.sig        r33=f8                          // q
1490         xmpy.lu         f9=f8,f14               }
1491 { .mfi; xmpy.hu         f10=f8,f14
1492         shrp            H=H,L,32                };;
1493
1494 { .mmi; getf.sig        r35=f9                          // tl
1495         getf.sig        r31=f10                 };;     // th
1496
1497 .L_divw_2nd_iter:
1498 { .mii; (p0)    add             r32=-1,r33
1499         (p0)    cmp.eq          equ,cont=HH,r31         };;
1500 { .mii; (p0)    cmp.ltu         p8,p0=r35,D
1501         (p0)    sub             r34=r35,D
1502         (equ)   cmp.leu         break,cont=r35,H        };;
1503 { .mib; (cont)  cmp.leu         cont,break=HH,r31
1504         (p8)    add             r31=-1,r31
1505 (cont)  br.wtop.spnt            .L_divw_2nd_iter        };;
1506 ///////////////////////////////////////////////////////////
1507 { .mii; sub     H=H,r35
1508         or      r8=r8,r33
1509         mov     ar.pfs=r2               };;
1510 { .mii; shr.u   r9=H,I                  // remainder if anybody wants it
1511         mov     pr=r10,0x1ffff          }
1512 { .mfb; br.ret.sptk.many        b0      };;
1513
1514 // Unsigned 64 by 32 (well, by 64 for the moment) bit integer division
1515 // procedure.
1516 //
1517 // inputs:      f6 = (double)a, f7 = (double)b
1518 // output:      f8 = (int)(a/b)
1519 // clobbered:   f8,f9,f10,f11,pred
1520 pred=p15
1521 // One can argue that this snippet is copyrighted to Intel
1522 // Corporation, as it's essentially identical to one of those
1523 // found in "Divide, Square Root and Remainder" section at
1524 // http://www.intel.com/software/products/opensource/libraries/num.htm.
1525 // Yes, I admit that the referred code was used as template,
1526 // but after I realized that there hardly is any other instruction
1527 // sequence which would perform this operation. I mean I figure that
1528 // any independent attempt to implement high-performance division
1529 // will result in code virtually identical to the Intel code. It
1530 // should be noted though that below division kernel is 1 cycle
1531 // faster than Intel one (note commented splits:-), not to mention
1532 // original prologue (rather lack of one) and epilogue.
1533 .align  32
1534 .skip   16
1535 .L_udiv64_32_b6:
1536         frcpa.s1        f8,pred=f6,f7;;         // [0]  y0 = 1 / b
1537
1538 (pred)  fnma.s1         f9=f7,f8,f1             // [5]  e0 = 1 - b * y0
1539 (pred)  fmpy.s1         f10=f6,f8;;             // [5]  q0 = a * y0
1540 (pred)  fmpy.s1         f11=f9,f9               // [10] e1 = e0 * e0
1541 (pred)  fma.s1          f10=f9,f10,f10;;        // [10] q1 = q0 + e0 * q0
1542 (pred)  fma.s1          f8=f9,f8,f8     //;;    // [15] y1 = y0 + e0 * y0
1543 (pred)  fma.s1          f9=f11,f10,f10;;        // [15] q2 = q1 + e1 * q1
1544 (pred)  fma.s1          f8=f11,f8,f8    //;;    // [20] y2 = y1 + e1 * y1
1545 (pred)  fnma.s1         f10=f7,f9,f6;;          // [20] r2 = a - b * q2
1546 (pred)  fma.s1          f8=f10,f8,f9;;          // [25] q3 = q2 + r2 * y2
1547
1548         fcvt.fxu.trunc.s1       f8=f8           // [30] q = trunc(q3)
1549         br.ret.sptk.many        b6;;
1550 .endp   bn_div_words#
1551 #endif