2 * Copyright 2011-2022 The OpenSSL Project Authors. All Rights Reserved.
4 * Licensed under the Apache License 2.0 (the "License"). You may not use
5 * this file except in compliance with the License. You can obtain a copy
6 * in the file LICENSE in the source distribution or at
7 * https://www.openssl.org/source/license.html
10 #ifndef OSSL_CRYPTO_ARM_ARCH_H
11 # define OSSL_CRYPTO_ARM_ARCH_H
13 # if !defined(__ARM_ARCH__)
14 # if defined(__CC_ARM)
15 # define __ARM_ARCH__ __TARGET_ARCH_ARM
16 # if defined(__BIG_ENDIAN)
21 # elif defined(__GNUC__)
22 # if defined(__aarch64__)
23 # define __ARM_ARCH__ 8
25 * Why doesn't gcc define __ARM_ARCH__? Instead it defines
26 * bunch of below macros. See all_architectures[] table in
27 * gcc/config/arm/arm.c. On a side note it defines
28 * __ARMEL__/__ARMEB__ for little-/big-endian.
30 # elif defined(__ARM_ARCH)
31 # define __ARM_ARCH__ __ARM_ARCH
32 # elif defined(__ARM_ARCH_8A__)
33 # define __ARM_ARCH__ 8
34 # elif defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) || \
35 defined(__ARM_ARCH_7R__)|| defined(__ARM_ARCH_7M__) || \
36 defined(__ARM_ARCH_7EM__)
37 # define __ARM_ARCH__ 7
38 # elif defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || \
39 defined(__ARM_ARCH_6K__)|| defined(__ARM_ARCH_6M__) || \
40 defined(__ARM_ARCH_6Z__)|| defined(__ARM_ARCH_6ZK__) || \
41 defined(__ARM_ARCH_6T2__)
42 # define __ARM_ARCH__ 6
43 # elif defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5T__) || \
44 defined(__ARM_ARCH_5E__)|| defined(__ARM_ARCH_5TE__) || \
45 defined(__ARM_ARCH_5TEJ__)
46 # define __ARM_ARCH__ 5
47 # elif defined(__ARM_ARCH_4__) || defined(__ARM_ARCH_4T__)
48 # define __ARM_ARCH__ 4
50 # error "unsupported ARM architecture"
55 # if !defined(__ARM_MAX_ARCH__)
56 # define __ARM_MAX_ARCH__ __ARM_ARCH__
59 # if __ARM_MAX_ARCH__<__ARM_ARCH__
60 # error "__ARM_MAX_ARCH__ can't be less than __ARM_ARCH__"
61 # elif __ARM_MAX_ARCH__!=__ARM_ARCH__
62 # if __ARM_ARCH__<7 && __ARM_MAX_ARCH__>=7 && defined(__ARMEB__)
63 # error "can't build universal big-endian binary"
67 # ifndef __ASSEMBLER__
68 extern unsigned int OPENSSL_armcap_P;
69 extern unsigned int OPENSSL_arm_midr;
70 extern unsigned int OPENSSL_armv8_rsa_neonized;
73 # define ARMV7_NEON (1<<0)
74 # define ARMV7_TICK (1<<1)
75 # define ARMV8_AES (1<<2)
76 # define ARMV8_SHA1 (1<<3)
77 # define ARMV8_SHA256 (1<<4)
78 # define ARMV8_PMULL (1<<5)
79 # define ARMV8_SHA512 (1<<6)
80 # define ARMV8_CPUID (1<<7)
81 # define ARMV8_RNG (1<<8)
82 # define ARMV8_SM3 (1<<9)
83 # define ARMV8_SM4 (1<<10)
84 # define ARMV8_SHA3 (1<<11)
85 # define ARMV8_UNROLL8_EOR3 (1<<12)
86 # define ARMV8_SVE (1<<13)
87 # define ARMV8_SVE2 (1<<14)
90 * MIDR_EL1 system register
92 * 63___ _ ___32_31___ _ ___24_23_____20_19_____16_15__ _ __4_3_______0
94 * |RES0 | Implementer | Variant | Arch | PartNum |Revision|
95 * |____ _ _____|_____ _ _____|_________|_______ _|____ _ ___|________|
99 # define ARM_CPU_IMP_ARM 0x41
100 # define HISI_CPU_IMP 0x48
102 # define ARM_CPU_PART_CORTEX_A72 0xD08
103 # define ARM_CPU_PART_N1 0xD0C
104 # define ARM_CPU_PART_V1 0xD40
105 # define ARM_CPU_PART_N2 0xD49
106 # define HISI_CPU_PART_KP920 0xD01
107 # define ARM_CPU_PART_V2 0xD4F
109 # define MIDR_PARTNUM_SHIFT 4
110 # define MIDR_PARTNUM_MASK (0xfffU << MIDR_PARTNUM_SHIFT)
111 # define MIDR_PARTNUM(midr) \
112 (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
114 # define MIDR_IMPLEMENTER_SHIFT 24
115 # define MIDR_IMPLEMENTER_MASK (0xffU << MIDR_IMPLEMENTER_SHIFT)
116 # define MIDR_IMPLEMENTER(midr) \
117 (((midr) & MIDR_IMPLEMENTER_MASK) >> MIDR_IMPLEMENTER_SHIFT)
119 # define MIDR_ARCHITECTURE_SHIFT 16
120 # define MIDR_ARCHITECTURE_MASK (0xfU << MIDR_ARCHITECTURE_SHIFT)
121 # define MIDR_ARCHITECTURE(midr) \
122 (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
124 # define MIDR_CPU_MODEL_MASK \
125 (MIDR_IMPLEMENTER_MASK | \
126 MIDR_PARTNUM_MASK | \
127 MIDR_ARCHITECTURE_MASK)
129 # define MIDR_CPU_MODEL(imp, partnum) \
130 (((imp) << MIDR_IMPLEMENTER_SHIFT) | \
131 (0xfU << MIDR_ARCHITECTURE_SHIFT) | \
132 ((partnum) << MIDR_PARTNUM_SHIFT))
134 # define MIDR_IS_CPU_MODEL(midr, imp, partnum) \
135 (((midr) & MIDR_CPU_MODEL_MASK) == MIDR_CPU_MODEL(imp, partnum))
137 #if defined(__ASSEMBLER__)
141 * - Armv8.3-A Pointer Authentication and
142 * - Armv8.5-A Branch Target Identification
143 * features which require emitting a .note.gnu.property section with the
144 * appropriate architecture-dependent feature bits set.
145 * Read more: "ELF for the ArmĀ® 64-bit Architecture"
148 # if defined(__ARM_FEATURE_BTI_DEFAULT) && __ARM_FEATURE_BTI_DEFAULT == 1
149 # define GNU_PROPERTY_AARCH64_BTI (1 << 0) /* Has Branch Target Identification */
150 # define AARCH64_VALID_CALL_TARGET hint #34 /* BTI 'c' */
152 # define GNU_PROPERTY_AARCH64_BTI 0 /* No Branch Target Identification */
153 # define AARCH64_VALID_CALL_TARGET
156 # if defined(__ARM_FEATURE_PAC_DEFAULT) && \
157 (__ARM_FEATURE_PAC_DEFAULT & 1) == 1 /* Signed with A-key */
158 # define GNU_PROPERTY_AARCH64_POINTER_AUTH \
159 (1 << 1) /* Has Pointer Authentication */
160 # define AARCH64_SIGN_LINK_REGISTER hint #25 /* PACIASP */
161 # define AARCH64_VALIDATE_LINK_REGISTER hint #29 /* AUTIASP */
162 # elif defined(__ARM_FEATURE_PAC_DEFAULT) && \
163 (__ARM_FEATURE_PAC_DEFAULT & 2) == 2 /* Signed with B-key */
164 # define GNU_PROPERTY_AARCH64_POINTER_AUTH \
165 (1 << 1) /* Has Pointer Authentication */
166 # define AARCH64_SIGN_LINK_REGISTER hint #27 /* PACIBSP */
167 # define AARCH64_VALIDATE_LINK_REGISTER hint #31 /* AUTIBSP */
169 # define GNU_PROPERTY_AARCH64_POINTER_AUTH 0 /* No Pointer Authentication */
170 # if GNU_PROPERTY_AARCH64_BTI != 0
171 # define AARCH64_SIGN_LINK_REGISTER AARCH64_VALID_CALL_TARGET
173 # define AARCH64_SIGN_LINK_REGISTER
175 # define AARCH64_VALIDATE_LINK_REGISTER
178 # if GNU_PROPERTY_AARCH64_POINTER_AUTH != 0 || GNU_PROPERTY_AARCH64_BTI != 0
179 .pushsection .note.gnu.property, "a";
185 .long 0xc0000000; /* GNU_PROPERTY_AARCH64_FEATURE_1_AND */
187 .long (GNU_PROPERTY_AARCH64_POINTER_AUTH | GNU_PROPERTY_AARCH64_BTI);
192 # endif /* defined __ASSEMBLER__ */
194 # define IS_CPU_SUPPORT_UNROLL8_EOR3() \
195 (OPENSSL_armcap_P & ARMV8_UNROLL8_EOR3)