Fix ctr mode properly this time....

[openssl.git] / crypto / sparccpuid.S

diff --git a/crypto/sparccpuid.S b/crypto/sparccpuid.S
index 4691bd72bb3a6b32ca164cf7694b85d391e0f9ef..1e0756a173c88d04a95fa34be18ba95cf74bce8d 100644 (file)
--- a/crypto/sparccpuid.S
+++ b/crypto/sparccpuid.S
@@ -179,7 +179,7 @@ OPENSSL_atomic_add:
        ba      .enter
        nop
 #ifdef __sun
-! Note that you don't have to link with libthread to call thr_yield,
+! Note that you do not have to link with libthread to call thr_yield,
 ! as libc provides a stub, which is overloaded the moment you link
 ! with *either* libpthread or libthread...
 #define        YIELD_CPU       thr_yield
@@ -225,13 +225,69 @@ _sparcv9_rdtick:
        xor     %o0,%o0,%o0
        .word   0x91410000      !rd     %tick,%o0
        retl
-       .word   0x93323020      !srlx   %o2,32,%o1
+       .word   0x93323020      !srlx   %o0,32,%o1
 .notick:
        retl
        xor     %o1,%o1,%o1
 .type  _sparcv9_rdtick,#function
 .size  _sparcv9_rdtick,.-_sparcv9_rdtick
 
+! Probe and instrument VIS1 instruction. Output is number of cycles it
+! takes to execute rdtick and pair of VIS1 instructions. US-Tx VIS unit
+! is slow (documented to be 6 cycles on T2) and the core is in-order
+! single-issue, it should be possible to distinguish Tx reliably...
+! Observed return values are:
+!
+!      UltraSPARC IIi          7
+!      UltraSPARC III          7
+!      UltraSPARC T1           24
+!
+! Numbers for T2 and SPARC64 V-VII are more than welcomed.
+!
+! It would be possible to detect specifically US-T1 by instrumenting
+! fmul8ulx16, which is emulated on T1 and as such accounts for quite
+! a lot of %tick-s, couple of thousand on Linux...
+.global        _sparcv9_vis1_probe
+.align 8
+_sparcv9_vis1_probe:
+       .word   0x91410000      !rd     %tick,%o0
+       .word   0x81b00d80      !fxor   %f0,%f0,%f0
+       .word   0x85b08d82      !fxor   %f2,%f2,%f2
+       .word   0x93410000      !rd     %tick,%o1
+       .word   0x81b00d80      !fxor   %f0,%f0,%f0
+       .word   0x85b08d82      !fxor   %f2,%f2,%f2
+       .word   0x95410000      !rd     %tick,%o2
+       .word   0x81b00d80      !fxor   %f0,%f0,%f0
+       .word   0x85b08d82      !fxor   %f2,%f2,%f2
+       .word   0x97410000      !rd     %tick,%o3
+       .word   0x81b00d80      !fxor   %f0,%f0,%f0
+       .word   0x85b08d82      !fxor   %f2,%f2,%f2
+       .word   0x99410000      !rd     %tick,%o4
+
+       ! calculate intervals
+       sub     %o1,%o0,%o0
+       sub     %o2,%o1,%o1
+       sub     %o3,%o2,%o2
+       sub     %o4,%o3,%o3
+
+       ! find minumum value
+       cmp     %o0,%o1
+       .word   0x38680002      !bgu,a  %xcc,.+8
+       mov     %o1,%o0
+       cmp     %o0,%o2
+       .word   0x38680002      !bgu,a  %xcc,.+8
+       mov     %o2,%o0
+       cmp     %o0,%o3
+       .word   0x38680002      !bgu,a  %xcc,.+8
+       mov     %o3,%o0
+
+       ! check for ASI_FP16_P is redundant...
+       add     %sp,BIAS+2,%o1
+       retl
+       .word   0xc19a5a40      !ldda   [%o1]ASI_FP16_P,%f0
+.type  _sparcv9_vis1_probe,#function
+.size  _sparcv9_vis1_probe,.-_sparcv9_vis1_probe
+
 .global        OPENSSL_cleanse
 .align 32
 OPENSSL_cleanse:
@@ -242,6 +298,10 @@ OPENSSL_cleanse:
 #else
        bgu     .Lot
 #endif
+       cmp     %o1,0
+       bne     .Little
+       nop
+       retl
        nop
 
 .Little: