3 # ====================================================================
4 # [Re]written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
5 # project. The module is, however, dual licensed under OpenSSL and
6 # CRYPTOGAMS licenses depending on where you obtain it. For further
7 # details see http://www.openssl.org/~appro/cryptogams/.
8 # ====================================================================
10 # At some point it became apparent that the original SSLeay RC4
11 # assembler implementation performs suboptimally on latest IA-32
12 # microarchitectures. After re-tuning performance has changed as
20 # (*) This number is actually a trade-off:-) It's possible to
21 # achieve +72%, but at the cost of -48% off PIII performance.
22 # In other words code performing further 13% faster on AMD
23 # would perform almost 2 times slower on Intel PIII...
24 # For reference! This code delivers ~80% of rc4-amd64.pl
25 # performance on the same Opteron machine.
26 # (**) This number requires compressed key schedule set up by
27 # RC4_set_key [see commentary below for further details].
29 # <appro@fy.chalmers.se>
33 # Optimize for Core2 and Westmere [and incidentally Opteron]. Current
34 # performance in cycles per processed byte (less is better) and
35 # improvement relative to previous version of this module is:
37 # Pentium 10.2 # original numbers
41 # Opteron 6.1/+20% # new MMX numbers
43 # Westmere 5.1/+94%(**)
44 # Sandy Bridge 5.0/+8%
50 # (*) PIII can actually deliver 6.6 cycles per byte with MMX code,
51 # but this specific code performs poorly on Core2. And vice
52 # versa, below MMX/SSE code delivering 5.8/7.1 on Core2 performs
53 # poorly on PIII, at 8.0/14.5:-( As PIII is not a "hot" CPU
54 # [anymore], I chose to discard PIII-specific code path and opt
55 # for original IALU-only code, which is why MMX/SSE code path
56 # is guarded by SSE2 bit (see below), not MMX/SSE.
57 # (**) Performance vs. block size on Core2 and Westmere had a maximum
58 # at ... 64 bytes block size. And it was quite a maximum, 40-60%
59 # in comparison to largest 8KB block size. Above improvement
60 # coefficients are for the largest block size.
62 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
63 push(@INC,"${dir}","${dir}../../perlasm");
67 open STDOUT,">$output";
69 &asm_init($ARGV[0],"rc4-586.pl",$x86only = $ARGV[$#ARGV] eq "386");
81 my $func = ($i==0)?*mov:*or;
83 &add (&LB($yy),&LB($tx));
84 &mov ($ty,&DWP(0,$dat,$yy,4));
85 &mov (&DWP(0,$dat,$yy,4),$tx);
86 &mov (&DWP(0,$dat,$xx,4),$ty);
90 &ror ($out,8) if ($i!=0);
92 &mov ($tx,&DWP(0,$dat,$xx,4));
94 &mov ($tx,&wparam(3)); # reload [re-biased] out
96 &$func ($out,&DWP(0,$dat,$ty,4));
100 # >20% faster on Atom and Sandy Bridge[!], 8% faster on Opteron,
101 # but ~40% slower on Core2 and Westmere... Attempt to add movz
102 # brings down Opteron by 25%, Atom and Sandy Bridge by 15%, yet
103 # on Core2 with movz it's almost 20% slower than below alternative
104 # code... Yes, it's a total mess...
106 $RC4_loop_mmx = sub { # SSE actually...
109 my $mm=$i<=0?"mm0":"mm".($i&1);
111 &add (&LB($yy),&LB($tx));
112 &lea (@XX[1],&DWP(1,@XX[0]));
113 &pxor ("mm2","mm0") if ($i==0);
114 &psllq ("mm1",8) if ($i==0);
116 &pxor ("mm0","mm0") if ($i<=0);
117 &mov ($ty,&DWP(0,$dat,$yy,4));
118 &mov (&DWP(0,$dat,$yy,4),$tx);
119 &pxor ("mm1","mm2") if ($i==0);
120 &mov (&DWP(0,$dat,$XX[0],4),$ty);
121 &add (&LB($ty),&LB($tx));
122 &movd (@XX[0],"mm7") if ($i==0);
123 &mov ($tx,&DWP(0,$dat,@XX[1],4));
124 &pxor ("mm1","mm1") if ($i==1);
125 &movq ("mm2",&QWP(0,$inp)) if ($i==1);
126 &movq (&QWP(-8,(@XX[0],$inp)),"mm1") if ($i==0);
127 &pinsrw ($mm,&DWP(0,$dat,$ty,4),$j);
129 push (@XX,shift(@XX)) if ($i>=0);
132 # Using pinsrw here improves performane on Intel CPUs by 2-3%, but
133 # brings down AMD by 7%...
134 $RC4_loop_mmx = sub {
137 &add (&LB($yy),&LB($tx));
138 &psllq ("mm1",8*(($i-1)&7)) if (abs($i)!=1);
139 &mov ($ty,&DWP(0,$dat,$yy,4));
140 &mov (&DWP(0,$dat,$yy,4),$tx);
141 &mov (&DWP(0,$dat,$xx,4),$ty);
144 &movz ($xx,&LB($xx)); # (*)
145 &movz ($ty,&LB($ty)); # (*)
146 &pxor ("mm2",$i==1?"mm0":"mm1") if ($i>=0);
147 &movq ("mm0",&QWP(0,$inp)) if ($i<=0);
148 &movq (&QWP(-8,($out,$inp)),"mm2") if ($i==0);
149 &mov ($tx,&DWP(0,$dat,$xx,4));
150 &movd ($i>0?"mm1":"mm2",&DWP(0,$dat,$ty,4));
152 # (*) This is the key to Core2 and Westmere performance.
153 # Whithout movz out-of-order execution logic confuses
154 # itself and fails to reorder loads and stores. Problem
155 # appears to be fixed in Sandy Bridge...
159 &external_label("OPENSSL_ia32cap_P");
161 # void RC4(RC4_KEY *key,size_t len,const unsigned char *inp,unsigned char *out);
162 &function_begin("RC4");
163 &mov ($dat,&wparam(0)); # load key schedule pointer
164 &mov ($ty, &wparam(1)); # load len
165 &mov ($inp,&wparam(2)); # load inp
166 &mov ($out,&wparam(3)); # load out
168 &xor ($xx,$xx); # avoid partial register stalls
171 &cmp ($ty,0); # safety net
172 &je (&label("abort"));
174 &mov (&LB($xx),&BP(0,$dat)); # load key->x
175 &mov (&LB($yy),&BP(4,$dat)); # load key->y
178 &lea ($tx,&DWP(0,$inp,$ty));
179 &sub ($out,$inp); # re-bias out
180 &mov (&wparam(1),$tx); # save input+len
184 # detect compressed key schedule...
185 &cmp (&DWP(256,$dat),-1);
186 &je (&label("RC4_CHAR"));
188 &mov ($tx,&DWP(0,$dat,$xx,4));
190 &and ($ty,-4); # how many 4-byte chunks?
191 &jz (&label("loop1"));
193 &mov (&wparam(3),$out); # $out as accumulator in these loops
195 &jmp (&label("go4loop4"));
198 &jz (&label("go4loop4"));
200 &picmeup($out,"OPENSSL_ia32cap_P");
201 &bt (&DWP(0,$out),26); # check SSE2 bit [could have been MMX]
202 &jnc (&label("go4loop4"));
204 &mov ($out,&wparam(3)) if (!$alt);
205 &movd ("mm7",&wparam(3)) if ($alt);
207 &lea ($ty,&DWP(-8,$inp,$ty));
208 &mov (&DWP(-4,$dat),$ty); # save input+(len/8)*8-8
211 &jmp(&label("loop_mmx_enter"));
213 &set_label("loop_mmx",16);
215 &set_label("loop_mmx_enter");
216 for ($i=1;$i<8;$i++) { &$RC4_loop_mmx($i); }
218 &xor ($yy,$yy); # this is second key to Core2
219 &mov (&LB($yy),&LB($ty)); # and Westmere performance...
220 &cmp ($inp,&DWP(-4,$dat));
221 &lea ($inp,&DWP(8,$inp));
222 &jb (&label("loop_mmx"));
229 &movq (&QWP(-8,$out,$inp),"mm1");
233 &movq (&QWP(-8,$out,$inp),"mm2");
237 &cmp ($inp,&wparam(1)); # compare to input+len
238 &je (&label("done"));
239 &jmp (&label("loop1"));
242 &set_label("go4loop4",16);
243 &lea ($ty,&DWP(-4,$inp,$ty));
244 &mov (&wparam(2),$ty); # save input+(len/4)*4-4
247 for ($i=0;$i<4;$i++) { RC4_loop($i); }
249 &xor ($out,&DWP(0,$inp));
250 &cmp ($inp,&wparam(2)); # compare to input+(len/4)*4-4
251 &mov (&DWP(0,$tx,$inp),$out);# $tx holds re-biased out here
252 &lea ($inp,&DWP(4,$inp));
253 &mov ($tx,&DWP(0,$dat,$xx,4));
254 &jb (&label("loop4"));
256 &cmp ($inp,&wparam(1)); # compare to input+len
257 &je (&label("done"));
258 &mov ($out,&wparam(3)); # restore $out
260 &set_label("loop1",16);
261 &add (&LB($yy),&LB($tx));
262 &mov ($ty,&DWP(0,$dat,$yy,4));
263 &mov (&DWP(0,$dat,$yy,4),$tx);
264 &mov (&DWP(0,$dat,$xx,4),$ty);
268 &mov ($ty,&DWP(0,$dat,$ty,4));
269 &xor (&LB($ty),&BP(0,$inp));
270 &lea ($inp,&DWP(1,$inp));
271 &mov ($tx,&DWP(0,$dat,$xx,4));
272 &cmp ($inp,&wparam(1)); # compare to input+len
273 &mov (&BP(-1,$out,$inp),&LB($ty));
274 &jb (&label("loop1"));
276 &jmp (&label("done"));
278 # this is essentially Intel P4 specific codepath...
279 &set_label("RC4_CHAR",16);
280 &movz ($tx,&BP(0,$dat,$xx));
281 # strangely enough unrolled loop performs over 20% slower...
282 &set_label("cloop1");
283 &add (&LB($yy),&LB($tx));
284 &movz ($ty,&BP(0,$dat,$yy));
285 &mov (&BP(0,$dat,$yy),&LB($tx));
286 &mov (&BP(0,$dat,$xx),&LB($ty));
287 &add (&LB($ty),&LB($tx));
288 &movz ($ty,&BP(0,$dat,$ty));
290 &xor (&LB($ty),&BP(0,$inp));
291 &lea ($inp,&DWP(1,$inp));
292 &movz ($tx,&BP(0,$dat,$xx));
293 &cmp ($inp,&wparam(1));
294 &mov (&BP(-1,$out,$inp),&LB($ty));
295 &jb (&label("cloop1"));
299 &mov (&DWP(-4,$dat),$yy); # save key->y
300 &mov (&BP(-8,$dat),&LB($xx)); # save key->x
302 &function_end("RC4");
304 ########################################################################
312 # void RC4_set_key(RC4_KEY *key,int len,const unsigned char *data);
313 &function_begin("RC4_set_key");
314 &mov ($out,&wparam(0)); # load key
315 &mov ($idi,&wparam(1)); # load len
316 &mov ($inp,&wparam(2)); # load data
317 &picmeup($idx,"OPENSSL_ia32cap_P");
319 &lea ($out,&DWP(2*4,$out)); # &key->data
320 &lea ($inp,&DWP(0,$inp,$idi)); # $inp to point at the end
323 &mov (&DWP(-4,$out),$idi); # borrow key->y
325 &bt (&DWP(0,$idx),20); # check for bit#20
326 &jc (&label("c1stloop"));
328 &set_label("w1stloop",16);
329 &mov (&DWP(0,$out,"eax",4),"eax"); # key->data[i]=i;
330 &add (&LB("eax"),1); # i++;
331 &jnc (&label("w1stloop"));
336 &set_label("w2ndloop",16);
337 &mov ("eax",&DWP(0,$out,$ido,4));
338 &add (&LB($idx),&BP(0,$inp,$idi));
339 &add (&LB($idx),&LB("eax"));
341 &mov ("ebx",&DWP(0,$out,$idx,4));
342 &jnz (&label("wnowrap"));
343 &mov ($idi,&DWP(-4,$out));
344 &set_label("wnowrap");
345 &mov (&DWP(0,$out,$idx,4),"eax");
346 &mov (&DWP(0,$out,$ido,4),"ebx");
348 &jnc (&label("w2ndloop"));
349 &jmp (&label("exit"));
351 # Unlike all other x86 [and x86_64] implementations, Intel P4 core
352 # [including EM64T] was found to perform poorly with above "32-bit" key
353 # schedule, a.k.a. RC4_INT. Performance improvement for IA-32 hand-coded
354 # assembler turned out to be 3.5x if re-coded for compressed 8-bit one,
355 # a.k.a. RC4_CHAR! It's however inappropriate to just switch to 8-bit
356 # schedule for x86[_64], because non-P4 implementations suffer from
357 # significant performance losses then, e.g. PIII exhibits >2x
358 # deterioration, and so does Opteron. In order to assure optimal
359 # all-round performance, we detect P4 at run-time and set up compressed
360 # key schedule, which is recognized by RC4 procedure.
362 &set_label("c1stloop",16);
363 &mov (&BP(0,$out,"eax"),&LB("eax")); # key->data[i]=i;
364 &add (&LB("eax"),1); # i++;
365 &jnc (&label("c1stloop"));
371 &set_label("c2ndloop",16);
372 &mov (&LB("eax"),&BP(0,$out,$ido));
373 &add (&LB($idx),&BP(0,$inp,$idi));
374 &add (&LB($idx),&LB("eax"));
376 &mov (&LB("ebx"),&BP(0,$out,$idx));
377 &jnz (&label("cnowrap"));
378 &mov ($idi,&DWP(-4,$out));
379 &set_label("cnowrap");
380 &mov (&BP(0,$out,$idx),&LB("eax"));
381 &mov (&BP(0,$out,$ido),&LB("ebx"));
383 &jnc (&label("c2ndloop"));
385 &mov (&DWP(256,$out),-1); # mark schedule as compressed
389 &mov (&DWP(-8,$out),"eax"); # key->x=0;
390 &mov (&DWP(-4,$out),"eax"); # key->y=0;
391 &function_end("RC4_set_key");
393 # const char *RC4_options(void);
394 &function_begin_B("RC4_options");
395 &call (&label("pic_point"));
396 &set_label("pic_point");
398 &lea ("eax",&DWP(&label("opts")."-".&label("pic_point"),"eax"));
399 &picmeup("edx","OPENSSL_ia32cap_P");
400 &mov ("edx",&DWP(0,"edx"));
402 &jc (&label("1xchar"));
404 &jnc (&label("ret"));
407 &set_label("1xchar");
411 &set_label("opts",64);
412 &asciz ("rc4(4x,int)");
413 &asciz ("rc4(1x,char)");
414 &asciz ("rc4(8x,mmx)");
415 &asciz ("RC4 for x86, CRYPTOGAMS by <appro\@openssl.org>");
417 &function_end_B("RC4_options");