3 # Specific modes implementations for SPARC Architecture 2011. There
4 # is T4 dependency though, an ASI value that is not specified in the
5 # Architecture Manual. But as SPARC universe is rather monocultural,
6 # we imply that processor capable of executing crypto instructions
7 # can handle the ASI in question as well. This means that we ought to
8 # keep eyes open when new processors emerge...
10 # As for above mentioned ASI. It's so called "block initializing
11 # store" which cancels "read" in "read-update-write" on cache lines.
12 # This is "cooperative" optimization, as it reduces overall pressure
13 # on memory interface. Benefits can't be observed/quantified with
14 # usual benchmarks, on the contrary you can notice that single-thread
15 # performance for parallelizable modes is ~1.5% worse for largest
16 # block sizes [though few percent better for not so long ones]. All
17 # this based on suggestions from David Miller.
19 my ($inp,$out,$len,$key,$ivec,$enc)=map("%i$_",(0..5));
20 my ($ileft,$iright,$ooff,$omask,$ivoff,$blk_init)=map("%l$_",(0..7));
22 sub alg_cbc_encrypt_implement {
26 .globl ${alg}${bits}_t4_cbc_encrypt
28 ${alg}${bits}_t4_cbc_encrypt:
29 save %sp, -$::frame, %sp
30 sub $inp, $out, $blk_init ! $inp!=$out
32 $::code.=<<___ if (!$::evp);
33 andcc $ivec, 7, $ivoff
34 alignaddr $ivec, %g0, $ivec
36 ldd [$ivec + 0], %f0 ! load ivec
40 faligndata %f0, %f2, %f0
41 faligndata %f2, %f4, %f2
44 $::code.=<<___ if ($::evp);
52 prefetch [$inp + 63], 20
53 call _${alg}${bits}_load_enckey
59 sub $iright, $ileft, $iright
62 movrnz $ooff, 0, $blk_init ! if ( $out&7 ||
63 movleu $::size_t_cc, 0, $blk_init ! $len<128 ||
64 brnz,pn $blk_init, .L${bits}cbc_enc_blk ! $inp==$out)
65 srl $omask, $ooff, $omask
67 alignaddrl $out, %g0, $out
71 .L${bits}_cbc_enc_loop:
78 srlx %o1, $iright, %g1
81 srlx %o2, $iright, %o2
84 xor %g4, %o0, %o0 ! ^= rk[0]
89 fxor %f12, %f0, %f0 ! ^= ivec
91 prefetch [$out + 63], 22
92 prefetch [$inp + 16+63], 20
93 call _${alg}${bits}_encrypt_1x
101 brnz,pt $len, .L${bits}_cbc_enc_loop
104 $::code.=<<___ if ($::evp);
110 $::code.=<<___ if (!$::evp);
114 std %f0, [$ivec + 0] ! write out ivec
122 2: ldxa [$inp]0x82, %o0 ! avoid read-after-write hazard
123 ! and ~3x deterioration
125 faligndata %f0, %f0, %f4 ! handle unaligned output
126 faligndata %f0, %f2, %f6
127 faligndata %f2, %f2, %f8
129 stda %f4, [$out + $omask]0xc0 ! partial store
132 orn %g0, $omask, $omask
133 stda %f8, [$out + $omask]0xc0 ! partial store
135 brnz,pt $len, .L${bits}_cbc_enc_loop+4
136 orn %g0, $omask, $omask
138 $::code.=<<___ if ($::evp);
144 $::code.=<<___ if (!$::evp);
148 std %f0, [$ivec + 0] ! write out ivec
154 3: alignaddrl $ivec, $ivoff, %g0 ! handle unaligned ivec
156 srl $omask, $ivoff, $omask
157 faligndata %f0, %f0, %f4
158 faligndata %f0, %f2, %f6
159 faligndata %f2, %f2, %f8
160 stda %f4, [$ivec + $omask]0xc0
163 orn %g0, $omask, $omask
164 stda %f8, [$ivec + $omask]0xc0
170 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
172 .L${bits}cbc_enc_blk:
173 add $out, $len, $blk_init
174 and $blk_init, 63, $blk_init ! tail
175 sub $len, $blk_init, $len
176 add $blk_init, 15, $blk_init ! round up to 16n
178 srl $blk_init, 4, $blk_init
180 .L${bits}_cbc_enc_blk_loop:
186 sllx %o0, $ileft, %o0
187 srlx %o1, $iright, %g1
188 sllx %o1, $ileft, %o1
190 srlx %o2, $iright, %o2
193 xor %g4, %o0, %o0 ! ^= rk[0]
198 fxor %f12, %f0, %f0 ! ^= ivec
200 prefetch [$inp + 16+63], 20
201 call _${alg}${bits}_encrypt_1x
205 stda %f0, [$out]0xf2 ! ASI_BLK_INIT, T4-specific
207 stda %f2, [$out]0xf2 ! ASI_BLK_INIT, T4-specific
208 brnz,pt $len, .L${bits}_cbc_enc_blk_loop
211 membar #StoreLoad|#StoreStore
212 brnz,pt $blk_init, .L${bits}_cbc_enc_loop
215 $::code.=<<___ if ($::evp);
221 $::code.=<<___ if (!$::evp);
225 std %f0, [$ivec + 0] ! write out ivec
231 .type ${alg}${bits}_t4_cbc_encrypt,#function
232 .size ${alg}${bits}_t4_cbc_encrypt,.-${alg}${bits}_t4_cbc_encrypt
236 sub alg_cbc_decrypt_implement {
237 my ($alg,$bits) = @_;
240 .globl ${alg}${bits}_t4_cbc_decrypt
242 ${alg}${bits}_t4_cbc_decrypt:
243 save %sp, -$::frame, %sp
244 sub $inp, $out, $blk_init ! $inp!=$out
246 $::code.=<<___ if (!$::evp);
247 andcc $ivec, 7, $ivoff
248 alignaddr $ivec, %g0, $ivec
250 ldd [$ivec + 0], %f12 ! load ivec
252 ldd [$ivec + 8], %f14
253 ldd [$ivec + 16], %f0
254 faligndata %f12, %f14, %f12
255 faligndata %f14, %f0, %f14
258 $::code.=<<___ if ($::evp);
259 ld [$ivec + 0], %f12 ! load ivec
262 ld [$ivec + 12], %f15
266 prefetch [$inp + 63], 20
267 call _${alg}${bits}_load_deckey
270 sll $ileft, 3, $ileft
273 sub $iright, $ileft, $iright
276 movrnz $ooff, 0, $blk_init ! if ( $out&7 ||
277 movleu $::size_t_cc, 0, $blk_init ! $len<256 ||
278 brnz,pn $blk_init, .L${bits}cbc_dec_blk ! $inp==$out)
279 srl $omask, $ooff, $omask
281 andcc $len, 16, %g0 ! is number of blocks even?
283 alignaddrl $out, %g0, $out
284 bz %icc, .L${bits}_cbc_dec_loop2x
286 .L${bits}_cbc_dec_loop:
292 sllx %o0, $ileft, %o0
293 srlx %o1, $iright, %g1
294 sllx %o1, $ileft, %o1
296 srlx %o2, $iright, %o2
299 xor %g4, %o0, %o2 ! ^= rk[0]
304 prefetch [$out + 63], 22
305 prefetch [$inp + 16+63], 20
306 call _${alg}${bits}_decrypt_1x
309 fxor %f12, %f0, %f0 ! ^= ivec
319 brnz,pt $len, .L${bits}_cbc_dec_loop2x
322 $::code.=<<___ if ($::evp);
326 st %f15, [$ivec + 12]
328 $::code.=<<___ if (!$::evp);
329 brnz,pn $ivoff, .L${bits}_cbc_dec_unaligned_ivec
332 std %f12, [$ivec + 0] ! write out ivec
333 std %f14, [$ivec + 8]
340 2: ldxa [$inp]0x82, %o0 ! avoid read-after-write hazard
341 ! and ~3x deterioration
343 faligndata %f0, %f0, %f4 ! handle unaligned output
344 faligndata %f0, %f2, %f6
345 faligndata %f2, %f2, %f8
347 stda %f4, [$out + $omask]0xc0 ! partial store
350 orn %g0, $omask, $omask
351 stda %f8, [$out + $omask]0xc0 ! partial store
353 brnz,pt $len, .L${bits}_cbc_dec_loop2x+4
354 orn %g0, $omask, $omask
356 $::code.=<<___ if ($::evp);
360 st %f15, [$ivec + 12]
362 $::code.=<<___ if (!$::evp);
363 brnz,pn $ivoff, .L${bits}_cbc_dec_unaligned_ivec
366 std %f12, [$ivec + 0] ! write out ivec
367 std %f14, [$ivec + 8]
373 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
375 .L${bits}_cbc_dec_loop2x:
383 sllx %o0, $ileft, %o0
384 srlx %o1, $iright, %g1
386 sllx %o1, $ileft, %o1
387 srlx %o2, $iright, %g1
389 sllx %o2, $ileft, %o2
390 srlx %o3, $iright, %g1
392 sllx %o3, $ileft, %o3
393 srlx %o4, $iright, %o4
396 xor %g4, %o0, %o4 ! ^= rk[0]
405 prefetch [$out + 63], 22
406 prefetch [$inp + 32+63], 20
407 call _${alg}${bits}_decrypt_2x
412 fxor %f12, %f0, %f0 ! ^= ivec
426 brnz,pt $len, .L${bits}_cbc_dec_loop2x
429 $::code.=<<___ if ($::evp);
433 st %f15, [$ivec + 12]
435 $::code.=<<___ if (!$::evp);
436 brnz,pn $ivoff, .L${bits}_cbc_dec_unaligned_ivec
439 std %f12, [$ivec + 0] ! write out ivec
440 std %f14, [$ivec + 8]
447 2: ldxa [$inp]0x82, %o0 ! avoid read-after-write hazard
448 ! and ~3x deterioration
450 faligndata %f0, %f0, %f8 ! handle unaligned output
451 faligndata %f0, %f2, %f0
452 faligndata %f2, %f4, %f2
453 faligndata %f4, %f6, %f4
454 faligndata %f6, %f6, %f6
455 stda %f8, [$out + $omask]0xc0 ! partial store
460 orn %g0, $omask, $omask
461 stda %f6, [$out + $omask]0xc0 ! partial store
463 brnz,pt $len, .L${bits}_cbc_dec_loop2x+4
464 orn %g0, $omask, $omask
466 $::code.=<<___ if ($::evp);
470 st %f15, [$ivec + 12]
472 $::code.=<<___ if (!$::evp);
473 brnz,pn $ivoff, .L${bits}_cbc_dec_unaligned_ivec
476 std %f12, [$ivec + 0] ! write out ivec
477 std %f14, [$ivec + 8]
482 .L${bits}_cbc_dec_unaligned_ivec:
483 alignaddrl $ivec, $ivoff, %g0 ! handle unaligned ivec
485 srl $omask, $ivoff, $omask
486 faligndata %f12, %f12, %f0
487 faligndata %f12, %f14, %f2
488 faligndata %f14, %f14, %f4
489 stda %f0, [$ivec + $omask]0xc0
492 orn %g0, $omask, $omask
493 stda %f4, [$ivec + $omask]0xc0
499 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
501 .L${bits}cbc_dec_blk:
502 add $out, $len, $blk_init
503 and $blk_init, 63, $blk_init ! tail
504 sub $len, $blk_init, $len
505 add $blk_init, 15, $blk_init ! round up to 16n
507 srl $blk_init, 4, $blk_init
509 add $blk_init, 1, $blk_init
511 .L${bits}_cbc_dec_blk_loop2x:
519 sllx %o0, $ileft, %o0
520 srlx %o1, $iright, %g1
522 sllx %o1, $ileft, %o1
523 srlx %o2, $iright, %g1
525 sllx %o2, $ileft, %o2
526 srlx %o3, $iright, %g1
528 sllx %o3, $ileft, %o3
529 srlx %o4, $iright, %o4
532 xor %g4, %o0, %o4 ! ^= rk[0]
541 prefetch [$inp + 32+63], 20
542 call _${alg}${bits}_decrypt_2x
548 fxor %f12, %f0, %f0 ! ^= ivec
555 stda %f0, [$out]0xf2 ! ASI_BLK_INIT, T4-specific
557 stda %f2, [$out]0xf2 ! ASI_BLK_INIT, T4-specific
559 stda %f4, [$out]0xf2 ! ASI_BLK_INIT, T4-specific
561 stda %f6, [$out]0xf2 ! ASI_BLK_INIT, T4-specific
562 bgu,pt $::size_t_cc, .L${bits}_cbc_dec_blk_loop2x
565 add $blk_init, $len, $len
566 andcc $len, 1, %g0 ! is number of blocks even?
567 membar #StoreLoad|#StoreStore
568 bnz,pt %icc, .L${bits}_cbc_dec_loop
570 brnz,pn $len, .L${bits}_cbc_dec_loop2x
573 $::code.=<<___ if ($::evp);
579 $::code.=<<___ if (!$::evp);
583 std %f0, [$ivec + 0] ! write out ivec
589 .type ${alg}${bits}_t4_cbc_decrypt,#function
590 .size ${alg}${bits}_t4_cbc_decrypt,.-${alg}${bits}_t4_cbc_decrypt
594 sub alg_ctr32_implement {
595 my ($alg,$bits) = @_;
598 .globl ${alg}${bits}_t4_ctr32_encrypt
600 ${alg}${bits}_t4_ctr32_encrypt:
601 save %sp, -$::frame, %sp
604 prefetch [$inp + 63], 20
605 call _${alg}${bits}_load_enckey
608 ld [$ivec + 0], %l4 ! counter
616 xor %o5, %g4, %g4 ! ^= rk[0]
618 movxtod %g4, %f14 ! most significant 64 bits
620 sub $inp, $out, $blk_init ! $inp!=$out
623 sll $ileft, 3, $ileft
626 sub $iright, $ileft, $iright
629 movrnz $ooff, 0, $blk_init ! if ( $out&7 ||
630 movleu $::size_t_cc, 0, $blk_init ! $len<256 ||
631 brnz,pn $blk_init, .L${bits}_ctr32_blk ! $inp==$out)
632 srl $omask, $ooff, $omask
634 andcc $len, 16, %g0 ! is number of blocks even?
635 alignaddrl $out, %g0, $out
636 bz %icc, .L${bits}_ctr32_loop2x
638 .L${bits}_ctr32_loop:
644 sllx %o0, $ileft, %o0
645 srlx %o1, $iright, %g1
646 sllx %o1, $ileft, %o1
648 srlx %o2, $iright, %o2
651 xor %g5, %l7, %g1 ! ^= rk[0]
654 srl %l7, 0, %l7 ! clruw
655 prefetch [$out + 63], 22
656 prefetch [$inp + 16+63], 20
658 $::code.=<<___ if ($alg eq "aes");
659 aes_eround01 %f16, %f14, %f2, %f4
660 aes_eround23 %f18, %f14, %f2, %f2
662 $::code.=<<___ if ($alg eq "cmll");
663 camellia_f %f16, %f2, %f14, %f2
664 camellia_f %f18, %f14, %f2, %f0
667 call _${alg}${bits}_encrypt_1x+8
672 fxor %f10, %f0, %f0 ! ^= inp
680 brnz,pt $len, .L${bits}_ctr32_loop2x
687 2: ldxa [$inp]0x82, %o0 ! avoid read-after-write hazard
688 ! and ~3x deterioration
690 faligndata %f0, %f0, %f4 ! handle unaligned output
691 faligndata %f0, %f2, %f6
692 faligndata %f2, %f2, %f8
693 stda %f4, [$out + $omask]0xc0 ! partial store
696 orn %g0, $omask, $omask
697 stda %f8, [$out + $omask]0xc0 ! partial store
699 brnz,pt $len, .L${bits}_ctr32_loop2x+4
700 orn %g0, $omask, $omask
705 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
707 .L${bits}_ctr32_loop2x:
715 sllx %o0, $ileft, %o0
716 srlx %o1, $iright, %g1
718 sllx %o1, $ileft, %o1
719 srlx %o2, $iright, %g1
721 sllx %o2, $ileft, %o2
722 srlx %o3, $iright, %g1
724 sllx %o3, $ileft, %o3
725 srlx %o4, $iright, %o4
728 xor %g5, %l7, %g1 ! ^= rk[0]
731 srl %l7, 0, %l7 ! clruw
735 srl %l7, 0, %l7 ! clruw
736 prefetch [$out + 63], 22
737 prefetch [$inp + 32+63], 20
739 $::code.=<<___ if ($alg eq "aes");
740 aes_eround01 %f16, %f14, %f2, %f8
741 aes_eround23 %f18, %f14, %f2, %f2
742 aes_eround01 %f16, %f14, %f6, %f10
743 aes_eround23 %f18, %f14, %f6, %f6
745 $::code.=<<___ if ($alg eq "cmll");
746 camellia_f %f16, %f2, %f14, %f2
747 camellia_f %f16, %f6, %f14, %f6
748 camellia_f %f18, %f14, %f2, %f0
749 camellia_f %f18, %f14, %f6, %f4
752 call _${alg}${bits}_encrypt_2x+16
758 fxor %f8, %f0, %f0 ! ^= inp
771 brnz,pt $len, .L${bits}_ctr32_loop2x
778 2: ldxa [$inp]0x82, %o0 ! avoid read-after-write hazard
779 ! and ~3x deterioration
781 faligndata %f0, %f0, %f8 ! handle unaligned output
782 faligndata %f0, %f2, %f0
783 faligndata %f2, %f4, %f2
784 faligndata %f4, %f6, %f4
785 faligndata %f6, %f6, %f6
787 stda %f8, [$out + $omask]0xc0 ! partial store
792 orn %g0, $omask, $omask
793 stda %f6, [$out + $omask]0xc0 ! partial store
795 brnz,pt $len, .L${bits}_ctr32_loop2x+4
796 orn %g0, $omask, $omask
801 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
804 add $out, $len, $blk_init
805 and $blk_init, 63, $blk_init ! tail
806 sub $len, $blk_init, $len
807 add $blk_init, 15, $blk_init ! round up to 16n
809 srl $blk_init, 4, $blk_init
811 add $blk_init, 1, $blk_init
813 .L${bits}_ctr32_blk_loop2x:
821 sllx %o0, $ileft, %o0
822 srlx %o1, $iright, %g1
824 sllx %o1, $ileft, %o1
825 srlx %o2, $iright, %g1
827 sllx %o2, $ileft, %o2
828 srlx %o3, $iright, %g1
830 sllx %o3, $ileft, %o3
831 srlx %o4, $iright, %o4
834 xor %g5, %l7, %g1 ! ^= rk[0]
837 srl %l7, 0, %l7 ! clruw
841 srl %l7, 0, %l7 ! clruw
842 prefetch [$inp + 32+63], 20
844 $::code.=<<___ if ($alg eq "aes");
845 aes_eround01 %f16, %f14, %f2, %f8
846 aes_eround23 %f18, %f14, %f2, %f2
847 aes_eround01 %f16, %f14, %f6, %f10
848 aes_eround23 %f18, %f14, %f6, %f6
850 $::code.=<<___ if ($alg eq "cmll");
851 camellia_f %f16, %f2, %f14, %f2
852 camellia_f %f16, %f6, %f14, %f6
853 camellia_f %f18, %f14, %f2, %f0
854 camellia_f %f18, %f14, %f6, %f4
857 call _${alg}${bits}_encrypt_2x+16
864 fxor %f8, %f0, %f0 ! ^= inp
870 stda %f0, [$out]0xf2 ! ASI_BLK_INIT, T4-specific
872 stda %f2, [$out]0xf2 ! ASI_BLK_INIT, T4-specific
874 stda %f4, [$out]0xf2 ! ASI_BLK_INIT, T4-specific
876 stda %f6, [$out]0xf2 ! ASI_BLK_INIT, T4-specific
877 bgu,pt $::size_t_cc, .L${bits}_ctr32_blk_loop2x
880 add $blk_init, $len, $len
881 andcc $len, 1, %g0 ! is number of blocks even?
882 membar #StoreLoad|#StoreStore
883 bnz,pt %icc, .L${bits}_ctr32_loop
885 brnz,pn $len, .L${bits}_ctr32_loop2x
890 .type ${alg}${bits}_t4_ctr32_encrypt,#function
891 .size ${alg}${bits}_t4_ctr32_encrypt,.-${alg}${bits}_t4_ctr32_encrypt
895 # Purpose of these subroutines is to explicitly encode VIS instructions,
896 # so that one can compile the module without having to specify VIS
897 # extentions on compiler command line, e.g. -xarch=v9 vs. -xarch=v9a.
898 # Idea is to reserve for option to produce "universal" binary and let
899 # programmer detect if current CPU is VIS capable at run-time.
901 my ($mnemonic,$rs1,$rs2,$rd)=@_;
903 my %visopf = ( "faligndata" => 0x048,
908 $ref = "$mnemonic\t$rs1,$rs2,$rd";
910 if ($opf=$visopf{$mnemonic}) {
911 foreach ($rs1,$rs2,$rd) {
912 return $ref if (!/%f([0-9]{1,2})/);
915 return $ref if ($1&1);
916 # re-encode for upper double register addressing
921 return sprintf ".word\t0x%08x !%s",
922 0x81b00000|$rd<<25|$rs1<<14|$opf<<5|$rs2,
929 my ($mnemonic,$rs1,$rs2,$rd)=@_;
930 my %bias = ( "g" => 0, "o" => 8, "l" => 16, "i" => 24 );
931 my $ref = "$mnemonic\t$rs1,$rs2,$rd";
932 my $opf = $mnemonic =~ /l$/ ? 0x01a :0x18;
934 foreach ($rs1,$rs2,$rd) {
935 if (/%([goli])([0-7])/) { $_=$bias{$1}+$2; }
936 else { return $ref; }
938 return sprintf ".word\t0x%08x !%s",
939 0x81b00000|$rd<<25|$rs1<<14|$opf<<5|$rs2,
943 sub unaes_round { # 4-argument instructions
944 my ($mnemonic,$rs1,$rs2,$rs3,$rd)=@_;
946 my %aesopf = ( "aes_eround01" => 0,
950 "aes_eround01_l"=> 4,
951 "aes_eround23_l"=> 5,
952 "aes_dround01_l"=> 6,
953 "aes_dround23_l"=> 7,
954 "aes_kexpand1" => 8 );
956 $ref = "$mnemonic\t$rs1,$rs2,$rs3,$rd";
958 if (defined($opf=$aesopf{$mnemonic})) {
959 $rs3 = ($rs3 =~ /%f([0-6]*[02468])/) ? (($1|$1>>5)&31) : $rs3;
960 foreach ($rs1,$rs2,$rd) {
961 return $ref if (!/%f([0-9]{1,2})/);
964 return $ref if ($1&1);
965 # re-encode for upper double register addressing
970 return sprintf ".word\t0x%08x !%s",
971 2<<30|$rd<<25|0x19<<19|$rs1<<14|$rs3<<9|$opf<<5|$rs2,
978 sub unaes_kexpand { # 3-argument instructions
979 my ($mnemonic,$rs1,$rs2,$rd)=@_;
981 my %aesopf = ( "aes_kexpand0" => 0x130,
982 "aes_kexpand2" => 0x131 );
984 $ref = "$mnemonic\t$rs1,$rs2,$rd";
986 if (defined($opf=$aesopf{$mnemonic})) {
987 foreach ($rs1,$rs2,$rd) {
988 return $ref if (!/%f([0-9]{1,2})/);
991 return $ref if ($1&1);
992 # re-encode for upper double register addressing
997 return sprintf ".word\t0x%08x !%s",
998 2<<30|$rd<<25|0x36<<19|$rs1<<14|$opf<<5|$rs2,
1005 sub uncamellia_f { # 4-argument instructions
1006 my ($mnemonic,$rs1,$rs2,$rs3,$rd)=@_;
1009 $ref = "$mnemonic\t$rs1,$rs2,$rs3,$rd";
1012 $rs3 = ($rs3 =~ /%f([0-6]*[02468])/) ? (($1|$1>>5)&31) : $rs3;
1013 foreach ($rs1,$rs2,$rd) {
1014 return $ref if (!/%f([0-9]{1,2})/);
1017 return $ref if ($1&1);
1018 # re-encode for upper double register addressing
1023 return sprintf ".word\t0x%08x !%s",
1024 2<<30|$rd<<25|0x19<<19|$rs1<<14|$rs3<<9|0xc<<5|$rs2,
1031 sub uncamellia3 { # 3-argument instructions
1032 my ($mnemonic,$rs1,$rs2,$rd)=@_;
1034 my %cmllopf = ( "camellia_fl" => 0x13c,
1035 "camellia_fli" => 0x13d );
1037 $ref = "$mnemonic\t$rs1,$rs2,$rd";
1039 if (defined($opf=$cmllopf{$mnemonic})) {
1040 foreach ($rs1,$rs2,$rd) {
1041 return $ref if (!/%f([0-9]{1,2})/);
1044 return $ref if ($1&1);
1045 # re-encode for upper double register addressing
1050 return sprintf ".word\t0x%08x !%s",
1051 2<<30|$rd<<25|0x36<<19|$rs1<<14|$opf<<5|$rs2,
1058 sub unmovxtox { # 2-argument instructions
1059 my ($mnemonic,$rs,$rd)=@_;
1060 my %bias = ( "g" => 0, "o" => 8, "l" => 16, "i" => 24, "f" => 0 );
1062 my %movxopf = ( "movdtox" => 0x110,
1063 "movstouw" => 0x111,
1064 "movstosw" => 0x113,
1066 "movwtos" => 0x119 );
1068 $ref = "$mnemonic\t$rs,$rd";
1070 if (defined($opf=$movxopf{$mnemonic})) {
1072 return $ref if (!/%([fgoli])([0-9]{1,2})/);
1075 return $ref if ($2&1);
1076 # re-encode for upper double register addressing
1081 return sprintf ".word\t0x%08x !%s",
1082 2<<30|$rd<<25|0x36<<19|$opf<<5|$rs,
1089 sub emit_assembler {
1090 foreach (split("\n",$::code)) {
1091 s/\`([^\`]*)\`/eval $1/ge;
1093 s/\b(f[a-z]+2[sd]*)\s+(%f[0-9]{1,2}),\s*(%f[0-9]{1,2})\s*$/$1\t%f0,$2,$3/g;
1095 s/\b(aes_[edk][^\s]*)\s+(%f[0-9]{1,2}),\s*(%f[0-9]{1,2}),\s*([%fx0-9]+),\s*(%f[0-9]{1,2})/
1096 &unaes_round($1,$2,$3,$4,$5)
1098 s/\b(aes_kexpand[02])\s+(%f[0-9]{1,2}),\s*(%f[0-9]{1,2}),\s*(%f[0-9]{1,2})/
1099 &unaes_kexpand($1,$2,$3,$4)
1101 s/\b(camellia_f)\s+(%f[0-9]{1,2}),\s*(%f[0-9]{1,2}),\s*([%fx0-9]+),\s*(%f[0-9]{1,2})/
1102 &uncamellia_f($1,$2,$3,$4,$5)
1104 s/\b(camellia_[^s]+)\s+(%f[0-9]{1,2}),\s*(%f[0-9]{1,2}),\s*(%f[0-9]{1,2})/
1105 &uncamellia3($1,$2,$3,$4)
1107 s/\b(mov[ds]to\w+)\s+(%f[0-9]{1,2}),\s*(%[goli][0-7])/
1108 &unmovxtox($1,$2,$3)
1110 s/\b(mov[xw]to[ds])\s+(%[goli][0-7]),\s*(%f[0-9]{1,2})/
1111 &unmovxtox($1,$2,$3)
1113 s/\b(f[^\s]*)\s+(%f[0-9]{1,2}),\s*(%f[0-9]{1,2}),\s*(%f[0-9]{1,2})/
1116 s/\b(alignaddr[l]*)\s+(%[goli][0-7]),\s*(%[goli][0-7]),\s*(%[goli][0-7])/
1117 &unalignaddr($1,$2,$3,$4)