crypto/armcap.c: detect ARMv8 capabilities [in 32-bit build].
authorAndy Polyakov <appro@openssl.org>
Sun, 4 May 2014 08:55:49 +0000 (10:55 +0200)
committerAndy Polyakov <appro@openssl.org>
Sun, 4 May 2014 08:55:49 +0000 (10:55 +0200)
crypto/arm_arch.h
crypto/armcap.c
crypto/armv4cpuid.S

index 5a83107..d68318c 100644 (file)
@@ -46,6 +46,10 @@ extern unsigned int OPENSSL_armcap_P;
                                      
 #define ARMV7_NEON      (1<<0)
 #define ARMV7_TICK      (1<<1)
+#define ARMV8_AES       (1<<2)
+#define ARMV8_SHA1      (1<<3)
+#define ARMV8_SHA256    (1<<4)
+#define ARMV8_PMULL     (1<<5)
 #endif
 
 #endif
index 9abaf39..5504144 100644 (file)
@@ -19,6 +19,10 @@ static void ill_handler (int sig) { siglongjmp(ill_jmp,sig); }
  * ARM compilers support inline assembler...
  */
 void _armv7_neon_probe(void);
+void _armv8_aes_probe(void);
+void _armv8_sha1_probe(void);
+void _armv8_sha256_probe(void);
+void _armv8_pmull_probe(void);
 unsigned int _armv7_tick(void);
 
 unsigned int OPENSSL_rdtsc(void)
@@ -68,6 +72,26 @@ void OPENSSL_cpuid_setup(void)
                {
                _armv7_neon_probe();
                OPENSSL_armcap_P |= ARMV7_NEON;
+               if (sigsetjmp(ill_jmp,1) == 0)
+                       {
+                       _armv8_aes_probe();
+                       OPENSSL_armcap_P |= ARMV8_AES;
+                       }
+               if (sigsetjmp(ill_jmp,1) == 0)
+                       {
+                       _armv8_sha1_probe();
+                       OPENSSL_armcap_P |= ARMV8_SHA1;
+                       }
+               if (sigsetjmp(ill_jmp,1) == 0)
+                       {
+                       _armv8_sha256_probe();
+                       OPENSSL_armcap_P |= ARMV8_SHA256;
+                       }
+               if (sigsetjmp(ill_jmp,1) == 0)
+                       {
+                       _armv8_pmull_probe();
+                       OPENSSL_armcap_P |= ARMV8_PMULL;
+                       }
                }
        if (sigsetjmp(ill_jmp,1) == 0)
                {
index 2d618de..edd6198 100644 (file)
@@ -18,6 +18,34 @@ _armv7_tick:
        .word   0xe12fff1e      @ bx    lr
 .size  _armv7_tick,.-_armv7_tick
 
+.global        _armv8_aes_probe
+.type  _armv8_aes_probe,%function
+_armv8_aes_probe:
+       .word   0xf3b00300      @ aese.8        q0,q0
+       .word   0xe12fff1e      @ bx    lr
+.size  _armv8_aes_probe,.-_armv8_aes_probe
+
+.global        _armv8_sha1_probe
+.type  _armv8_sha1_probe,%function
+_armv8_sha1_probe:
+       .word   0xf2000c40      @ sha1c.32      q0,q0,q0
+       .word   0xe12fff1e      @ bx    lr
+.size  _armv8_sha1_probe,.-_armv8_sha1_probe
+
+.global        _armv8_sha256_probe
+.type  _armv8_sha256_probe,%function
+_armv8_sha256_probe:
+       .word   0xf3000c40      @ sha256h.32    q0,q0,q0
+       .word   0xe12fff1e      @ bx    lr
+.size  _armv8_sha256_probe,.-_armv8_sha256_probe
+.global        _armv8_pmull_probe
+.type  _armv8_pmull_probe,%function
+_armv8_pmull_probe:
+       .word   0xf2a00e00      @ vmull.p64     q0,d0,d0
+       .word   0xe12fff1e      @ bx    lr
+.size  _armv8_pmull_probe,.-_armv8_pmull_probe
+
+.align 5
 .global        OPENSSL_atomic_add
 .type  OPENSSL_atomic_add,%function
 OPENSSL_atomic_add: