e_padlock.c: last x86_64 commit didn't work with some optimizers.

[openssl.git] / engines / e_padlock.c

diff --git a/engines/e_padlock.c b/engines/e_padlock.c
index 240b1f9b575972aa3a1697685f31d6633b110a7d..f0142798f49564819165c9a4eb381b5b23b021cb 100644 (file)
--- a/engines/e_padlock.c
+++ b/engines/e_padlock.c
@@ -107,10 +107,14 @@
      ) || \
      (defined(_MSC_VER) && defined(_M_IX86))
 #  define COMPILE_HW_PADLOCK
+#  ifdef OPENSSL_NO_DYNAMIC_ENGINE
 static ENGINE *ENGINE_padlock (void);
+#  endif
 # endif
 #endif
 
+#ifdef OPENSSL_NO_DYNAMIC_ENGINE
+
 void ENGINE_load_padlock (void)
 {
 /* On non-x86 CPUs it just returns. */
@@ -123,6 +127,8 @@ void ENGINE_load_padlock (void)
 #endif
 }
 
+#endif
+
 #ifdef COMPILE_HW_PADLOCK
 /* We do these includes here to avoid header problems on platforms that
    do not have the VIA padlock anyway... */
@@ -196,6 +202,7 @@ padlock_bind_helper(ENGINE *e)
        return 1;
 }
 
+#ifdef OPENSSL_NO_DYNAMIC_ENGINE
 /* Constructor */
 static ENGINE *
 ENGINE_padlock(void)
@@ -213,6 +220,7 @@ ENGINE_padlock(void)
 
        return eng;
 }
+#endif
 
 /* Check availability of the engine */
 static int
@@ -445,30 +453,33 @@ padlock_available(void)
 {
        char vendor_string[16];
        unsigned int eax, edx;
+       size_t  scratch;
 
        /* Are we running on the Centaur (VIA) CPU? */
        eax = 0x00000000;
        vendor_string[12] = 0;
        asm volatile (
+               "movq   %%rbx,%1\n"
                "cpuid\n"
-               "movl   %%ebx,(%1)\n"
-               "movl   %%edx,4(%1)\n"
-               "movl   %%ecx,8(%1)\n"
-               : "+a"(eax) : "r"(vendor_string) : "rbx", "rcx", "rdx");
+               "movl   %%ebx,(%2)\n"
+               "movl   %%edx,4(%2)\n"
+               "movl   %%ecx,8(%2)\n"
+               "movq   %1,%%rbx"
+               : "+a"(eax), "=&r"(scratch) : "r"(vendor_string) : "rcx", "rdx");
        if (strcmp(vendor_string, "CentaurHauls") != 0)
                return 0;
 
        /* Check for Centaur Extended Feature Flags presence */
        eax = 0xC0000000;
-       asm volatile ("cpuid"
-               : "+a"(eax) : : "rbx", "rcx", "rdx");
+       asm volatile ("movq %%rbx,%1; cpuid; movq %1,%%rbx"
+               : "+a"(eax), "=&r"(scratch) : : "rcx", "rdx");
        if (eax < 0xC0000001)
                return 0;
 
        /* Read the Centaur Extended Feature Flags */
        eax = 0xC0000001;
-       asm volatile ("cpuid"
-               : "+a"(eax), "=d"(edx) : : "rbx", "rcx");
+       asm volatile ("movq %%rbx,%2; cpuid; movq %2,%%rbx"
+               : "+a"(eax), "=d"(edx), "=&r"(scratch) : : "rcx");
 
        /* Fill up some flags */
        padlock_use_ace = ((edx & (0x3<<6)) == (0x3<<6));
@@ -524,12 +535,15 @@ static inline void *name(size_t cnt,              \
        struct padlock_cipher_data *cdata,      \
        void *out, const void *inp)             \
 {      void *iv;                               \
-       asm volatile ( "leaq    16(%0),%%rdx\n" \
+       size_t scratch;                         \
+       asm volatile ( "movq    %%rbx,%4\n"     \
+               "       leaq    16(%0),%%rdx\n" \
                "       leaq    32(%0),%%rbx\n" \
                        rep_xcrypt "\n"         \
-               : "=a"(iv), "=c"(cnt), "=D"(out), "=S"(inp) \
+               "       movq    %%rbx,%4"       \
+               : "=a"(iv), "=c"(cnt), "=D"(out), "=S"(inp), "=&r"(scratch) \
                : "0"(cdata), "1"(cnt), "2"(out), "3"(inp)  \
-               : "rbx", "rdx", "cc", "memory");        \
+               : "rdx", "cc", "memory");       \
        return iv;                              \
 }
 #endif
@@ -1322,6 +1336,8 @@ static RAND_METHOD padlock_rand = {
 #else  /* !COMPILE_HW_PADLOCK */
 #ifndef OPENSSL_NO_DYNAMIC_ENGINE
 OPENSSL_EXPORT
+int bind_engine(ENGINE *e, const char *id, const dynamic_fns *fns);
+OPENSSL_EXPORT
 int bind_engine(ENGINE *e, const char *id, const dynamic_fns *fns) { return 0; }
 IMPLEMENT_DYNAMIC_CHECK_FN()
 #endif