EVP_PKEY_METHOD accessor functions.

[openssl.git] / crypto / x86cpuid.pl

diff --git a/crypto/x86cpuid.pl b/crypto/x86cpuid.pl
index c18b0e2486d6ead7578d88a0cb227995b93eb67f..90ed196c09cd1580fd4d3a4e7f2b69f98e99311c 100644 (file)
--- a/crypto/x86cpuid.pl
+++ b/crypto/x86cpuid.pl
@@ -20,6 +20,8 @@ for (@ARGV) { $sse2=1 if (/-DOPENSSL_IA32_SSE2/); }
        &pop    ("eax");
        &xor    ("ecx","eax");
        &xor    ("eax","eax");
+       &mov    ("esi",&wparam(0));
+       &mov    (&DWP(8,"esi"),"eax");  # clear extended feature flags
        &bt     ("ecx",21);
        &jnc    (&label("nocpuid"));
        &cpuid  ();
@@ -67,6 +69,7 @@ for (@ARGV) { $sse2=1 if (/-DOPENSSL_IA32_SSE2/); }
        &inc    ("esi");                # number of cores
 
        &mov    ("eax",1);
+       &xor    ("ecx","ecx");
        &cpuid  ();
        &bt     ("edx",28);
        &jnc    (&label("generic"));
@@ -79,18 +82,19 @@ for (@ARGV) { $sse2=1 if (/-DOPENSSL_IA32_SSE2/); }
        
 &set_label("intel");
        &cmp    ("edi",4);
-       &mov    ("edi",-1);
+       &mov    ("esi",-1);
        &jb     (&label("nocacheinfo"));
 
        &mov    ("eax",4);
        &mov    ("ecx",0);              # query L1D
        &cpuid  ();
-       &mov    ("edi","eax");
-       &shr    ("edi",14);
-       &and    ("edi",0xfff);          # number of cores -1 per L1D
+       &mov    ("esi","eax");
+       &shr    ("esi",14);
+       &and    ("esi",0xfff);          # number of cores -1 per L1D
 
 &set_label("nocacheinfo");
        &mov    ("eax",1);
+       &xor    ("ecx","ecx");
        &cpuid  ();
        &and    ("edx",0xbfefffff);     # force reserved bits #20, #30 to 0
        &cmp    ("ebp",0);
@@ -104,7 +108,7 @@ for (@ARGV) { $sse2=1 if (/-DOPENSSL_IA32_SSE2/); }
        &bt     ("edx",28);             # test hyper-threading bit
        &jnc    (&label("generic"));
        &and    ("edx",0xefffffff);
-       &cmp    ("edi",0);
+       &cmp    ("esi",0);
        &je     (&label("generic"));
 
        &or     ("edx",0x10000000);
@@ -116,10 +120,19 @@ for (@ARGV) { $sse2=1 if (/-DOPENSSL_IA32_SSE2/); }
 &set_label("generic");
        &and    ("ebp",1<<11);          # isolate AMD XOP flag
        &and    ("ecx",0xfffff7ff);     # force 11th bit to 0
-       &mov    ("esi","edx");
+       &mov    ("esi","edx");          # %ebp:%esi is copy of %ecx:%edx
        &or     ("ebp","ecx");          # merge AMD XOP flag
 
-       &bt     ("ecx",27);             # check OSXSAVE bit
+       &cmp    ("edi",7);
+       &mov    ("edi",&wparam(0));
+       &jb     (&label("no_extended_info"));
+       &mov    ("eax",7);
+       &xor    ("ecx","ecx");
+       &cpuid  ();
+       &mov    (&DWP(8,"edi"),"ebx");  # save extended feature flag
+&set_label("no_extended_info");
+
+       &bt     ("ebp",27);             # check OSXSAVE bit
        &jnc    (&label("clear_avx"));
        &xor    ("ecx","ecx");
        &data_byte(0x0f,0x01,0xd0);     # xgetbv
@@ -133,6 +146,7 @@ for (@ARGV) { $sse2=1 if (/-DOPENSSL_IA32_SSE2/); }
        &and    ("esi",0xfeffffff);     # clear FXSR
 &set_label("clear_avx");
        &and    ("ebp",0xefffe7ff);     # clear AVX, FMA and AMD XOP bits
+       &and    (&DWP(8,"edi"),0xffffffdf);     # clear AVX2
 &set_label("done");
        &mov    ("eax","esi");
        &mov    ("edx","ebp");
@@ -196,7 +210,7 @@ for (@ARGV) { $sse2=1 if (/-DOPENSSL_IA32_SSE2/); }
 
 &function_begin_B("OPENSSL_far_spin");
        &pushf  ();
-       &pop    ("eax")
+       &pop    ("eax");
        &bt     ("eax",9);
        &jnc    (&label("nospin"));     # interrupts are disabled
 
@@ -351,6 +365,21 @@ for (@ARGV) { $sse2=1 if (/-DOPENSSL_IA32_SSE2/); }
        &ret    ();
 &function_end_B("OPENSSL_ia32_rdrand");
 
+&function_begin_B("OPENSSL_ia32_rdseed");
+       &mov    ("ecx",8);
+&set_label("loop");
+       &rdseed ("eax");
+       &jc     (&label("break"));
+       &loop   (&label("loop"));
+&set_label("break");
+       &cmp    ("eax",0);
+       &cmove  ("eax","ecx");
+       &ret    ();
+&function_end_B("OPENSSL_ia32_rdseed");
+
 &initseg("OPENSSL_cpuid_setup");
 
+&hidden("OPENSSL_cpuid_setup");
+&hidden("OPENSSL_ia32cap_P");
+
 &asm_finish();