Fix memory leak in GENERAL_NAME_set0_othername.

[openssl.git] / crypto / x86_64cpuid.pl

diff --git a/crypto/x86_64cpuid.pl b/crypto/x86_64cpuid.pl
index 503ef019ee3155bb602f2027906c4955f96abf39..ef3608b13495e0e8c4733d0e13a4da94a060c8be 100644 (file)
--- a/crypto/x86_64cpuid.pl
+++ b/crypto/x86_64cpuid.pl
@@ -11,7 +11,8 @@ $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
 ( $xlate="${dir}perlasm/x86_64-xlate.pl" and -f $xlate) or
 die "can't locate x86_64-xlate.pl";
 
-open STDOUT,"| $^X $xlate $flavour $output";
+open OUT,"| \"$^X\" $xlate $flavour $output";
+*STDOUT=*OUT;
 
 ($arg1,$arg2,$arg3,$arg4)=$win64?("%rcx","%rdx","%r8", "%r9") :        # Win64 order
                                 ("%rdi","%rsi","%rdx","%rcx"); # Unix order
@@ -23,7 +24,7 @@ print<<___;
        call    OPENSSL_cpuid_setup
 
 .hidden        OPENSSL_ia32cap_P
-.comm  OPENSSL_ia32cap_P,8
+.comm  OPENSSL_ia32cap_P,16,4
 
 .text
 
@@ -52,12 +53,13 @@ OPENSSL_rdtsc:
 .size  OPENSSL_rdtsc,.-OPENSSL_rdtsc
 
 .globl OPENSSL_ia32_cpuid
-.type  OPENSSL_ia32_cpuid,\@abi-omnipotent
+.type  OPENSSL_ia32_cpuid,\@function,1
 .align 16
 OPENSSL_ia32_cpuid:
        mov     %rbx,%r8                # save %rbx
 
        xor     %eax,%eax
+       mov     %eax,8(%rdi)            # clear extended feature flags
        cpuid
        mov     %eax,%r11d              # max value for standard query level
 
@@ -134,8 +136,19 @@ OPENSSL_ia32_cpuid:
        or      \$0x40000000,%edx       # set reserved bit#30 on Intel CPUs
        and     \$15,%ah
        cmp     \$15,%ah                # examine Family ID
-       jne     .Lnotintel
+       jne     .LnotP4
        or      \$0x00100000,%edx       # set reserved bit#20 to engage RC4_CHAR
+.LnotP4:
+       cmp     \$6,%ah
+       jne     .Lnotintel
+       and     \$0x0fff0ff0,%eax
+       cmp     \$0x00050670,%eax       # Knights Landing
+       je      .Lknights
+       cmp     \$0x00080650,%eax       # Knights Mill (according to sde)
+       jne     .Lnotintel
+.Lknights:
+       and     \$0xfbffffff,%ecx       # clear XSAVE flag to mimic Silvermont
+
 .Lnotintel:
        bt      \$28,%edx               # test hyper-threading bit
        jnc     .Lgeneric
@@ -154,6 +167,19 @@ OPENSSL_ia32_cpuid:
        or      %ecx,%r9d               # merge AMD XOP flag
 
        mov     %edx,%r10d              # %r9d:%r10d is copy of %ecx:%edx
+
+       cmp     \$7,%r11d
+       jb      .Lno_extended_info
+       mov     \$7,%eax
+       xor     %ecx,%ecx
+       cpuid
+       bt      \$26,%r9d               # check XSAVE bit, cleared on Knights
+       jc      .Lnotknights
+       and     \$0xfff7ffff,%ebx       # clear ADCX/ADOX flag
+.Lnotknights:
+       mov     %ebx,8(%rdi)            # save extended feature flags
+.Lno_extended_info:
+
        bt      \$27,%r9d               # check OSXSAVE bit
        jnc     .Lclear_avx
        xor     %ecx,%ecx               # XCR0
@@ -164,6 +190,7 @@ OPENSSL_ia32_cpuid:
 .Lclear_avx:
        mov     \$0xefffe7ff,%eax       # ~(1<<28|1<<12|1<<11)
        and     %eax,%r9d               # clear AVX, FMA and AMD XOP bits
+       andl    \$0xffffffdf,8(%rdi)    # clear AVX2, ~(1<<5)
 .Ldone:
        shl     \$32,%r9
        mov     %r10d,%eax
@@ -263,4 +290,36 @@ OPENSSL_wipe_cpu:
 .size  OPENSSL_wipe_cpu,.-OPENSSL_wipe_cpu
 ___
 
+print<<___;
+.globl OPENSSL_ia32_rdrand
+.type  OPENSSL_ia32_rdrand,\@abi-omnipotent
+.align 16
+OPENSSL_ia32_rdrand:
+       mov     \$8,%ecx
+.Loop_rdrand:
+       rdrand  %rax
+       jc      .Lbreak_rdrand
+       loop    .Loop_rdrand
+.Lbreak_rdrand:
+       cmp     \$0,%rax
+       cmove   %rcx,%rax
+       ret
+.size  OPENSSL_ia32_rdrand,.-OPENSSL_ia32_rdrand
+
+.globl OPENSSL_ia32_rdseed
+.type  OPENSSL_ia32_rdseed,\@abi-omnipotent
+.align 16
+OPENSSL_ia32_rdseed:
+       mov     \$8,%ecx
+.Loop_rdseed:
+       rdseed  %rax
+       jc      .Lbreak_rdseed
+       loop    .Loop_rdseed
+.Lbreak_rdseed:
+       cmp     \$0,%rax
+       cmove   %rcx,%rax
+       ret
+.size  OPENSSL_ia32_rdseed,.-OPENSSL_ia32_rdseed
+___
+
 close STDOUT;  # flush