Extend OPENSSL_ia32cap_P with extra word to accomodate AVX2 capability.

[openssl.git] / crypto / x86_64cpuid.pl

diff --git a/crypto/x86_64cpuid.pl b/crypto/x86_64cpuid.pl
index 58c7bab1b65ba82d93695f1b80b0fde42c228535..3a1adeecccde79af8d0fb6e0e5870f34aa7469f7 100644 (file)
--- a/crypto/x86_64cpuid.pl
+++ b/crypto/x86_64cpuid.pl
@@ -23,7 +23,7 @@ print<<___;
        call    OPENSSL_cpuid_setup
 
 .hidden        OPENSSL_ia32cap_P
-.comm  OPENSSL_ia32cap_P,8,4
+.comm  OPENSSL_ia32cap_P,16,4
 
 .text
 
@@ -52,12 +52,13 @@ OPENSSL_rdtsc:
 .size  OPENSSL_rdtsc,.-OPENSSL_rdtsc
 
 .globl OPENSSL_ia32_cpuid
-.type  OPENSSL_ia32_cpuid,\@abi-omnipotent
+.type  OPENSSL_ia32_cpuid,\@function,1
 .align 16
 OPENSSL_ia32_cpuid:
        mov     %rbx,%r8                # save %rbx
 
        xor     %eax,%eax
+       mov     %eax,8(%rdi)            # clear 3rd word
        cpuid
        mov     %eax,%r11d              # max value for standard query level
 
@@ -125,6 +126,14 @@ OPENSSL_ia32_cpuid:
        shr     \$14,%r10d
        and     \$0xfff,%r10d           # number of cores -1 per L1D
 
+       cmp     \$7,%r11d
+       jb      .Lnocacheinfo
+
+       mov     \$7,%eax
+       xor     %ecx,%ecx
+       cpuid
+       mov     %ebx,8(%rdi)
+
 .Lnocacheinfo:
        mov     \$1,%eax
        cpuid
@@ -164,6 +173,7 @@ OPENSSL_ia32_cpuid:
 .Lclear_avx:
        mov     \$0xefffe7ff,%eax       # ~(1<<28|1<<12|1<<11)
        and     %eax,%r9d               # clear AVX, FMA and AMD XOP bits
+       andl    \$0xffffffdf,8(%rdi)    # cleax AVX2, ~(1<<5)
 .Ldone:
        shl     \$32,%r9
        mov     %r10d,%eax