crypto/sha/asm/sha512-mips.pl

   1 #! /usr/bin/env perl
   2 # Copyright 2010-2018 The OpenSSL Project Authors. All Rights Reserved.
   3 #
   4 # Licensed under the OpenSSL license (the "License").  You may not use
   5 # this file except in compliance with the License.  You can obtain a copy
   6 # in the file LICENSE in the source distribution or at
   7 # https://www.openssl.org/source/license.html
   8
   9
  10 # ====================================================================
  11 # Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
  12 # project. The module is, however, dual licensed under OpenSSL and
  13 # CRYPTOGAMS licenses depending on where you obtain it. For further
  14 # details see http://www.openssl.org/~appro/cryptogams/.
  15 # ====================================================================
  16
  17 # SHA2 block procedures for MIPS.
  18
  19 # October 2010.
  20 #
  21 # SHA256 performance improvement on MIPS R5000 CPU is ~27% over gcc-
  22 # generated code in o32 build and ~55% in n32/64 build. SHA512 [which
  23 # for now can only be compiled for MIPS64 ISA] improvement is modest
  24 # ~17%, but it comes for free, because it's same instruction sequence.
  25 # Improvement coefficients are for aligned input.
  26
  27 # September 2012.
  28 #
  29 # Add MIPS[32|64]R2 code (>25% less instructions).
  30
  31 ######################################################################
  32 # There is a number of MIPS ABI in use, O32 and N32/64 are most
  33 # widely used. Then there is a new contender: NUBI. It appears that if
  34 # one picks the latter, it's possible to arrange code in ABI neutral
  35 # manner. Therefore let's stick to NUBI register layout:
  36 #
  37 ($zero,$at,$t0,$t1,$t2)=map("\$$_",(0..2,24,25));
  38 ($a0,$a1,$a2,$a3,$a4,$a5,$a6,$a7)=map("\$$_",(4..11));
  39 ($s0,$s1,$s2,$s3,$s4,$s5,$s6,$s7,$s8,$s9,$s10,$s11)=map("\$$_",(12..23));
  40 ($gp,$tp,$sp,$fp,$ra)=map("\$$_",(3,28..31));
  41 #
  42 # The return value is placed in $a0. Following coding rules facilitate
  43 # interoperability:
  44 #
  45 # - never ever touch $tp, "thread pointer", former $gp [o32 can be
  46 #   excluded from the rule, because it's specified volatile];
  47 # - copy return value to $t0, former $v0 [or to $a0 if you're adapting
  48 #   old code];
  49 # - on O32 populate $a4-$a7 with 'lw $aN,4*N($sp)' if necessary;
  50 #
  51 # For reference here is register layout for N32/64 MIPS ABIs:
  52 #
  53 # ($zero,$at,$v0,$v1)=map("\$$_",(0..3));
  54 # ($a0,$a1,$a2,$a3,$a4,$a5,$a6,$a7)=map("\$$_",(4..11));
  55 # ($t0,$t1,$t2,$t3,$t8,$t9)=map("\$$_",(12..15,24,25));
  56 # ($s0,$s1,$s2,$s3,$s4,$s5,$s6,$s7)=map("\$$_",(16..23));
  57 # ($gp,$sp,$fp,$ra)=map("\$$_",(28..31));
  58 #
  59 $flavour = shift || "o32"; # supported flavours are o32,n32,64,nubi32,nubi64
  60
  61 if ($flavour =~ /64|n32/i) {
  62         $PTR_LA="dla";
  63         $PTR_ADD="daddu";       # incidentally works even on n32
  64         $PTR_SUB="dsubu";       # incidentally works even on n32
  65         $REG_S="sd";
  66         $REG_L="ld";
  67         $PTR_SLL="dsll";        # incidentally works even on n32
  68         $SZREG=8;
  69 } else {
  70         $PTR_LA="la";
  71         $PTR_ADD="addu";
  72         $PTR_SUB="subu";
  73         $REG_S="sw";
  74         $REG_L="lw";
  75         $PTR_SLL="sll";
  76         $SZREG=4;
  77 }
  78 $pf = ($flavour =~ /nubi/i) ? $t0 : $t2;
  79 #
  80 # <appro@openssl.org>
  81 #
  82 ######################################################################
  83
  84 $big_endian=(`echo MIPSEB | $ENV{CC} -E -`=~/MIPSEB/)?0:1 if ($ENV{CC});
  85
  86 for (@ARGV) {   $output=$_ if (/\w[\w\-]*\.\w+$/);      }
  87 open STDOUT,">$output";
  88
  89 if (!defined($big_endian)) { $big_endian=(unpack('L',pack('N',1))==1); }
  90
  91 if ($output =~ /512/) {
  92         $label="512";
  93         $SZ=8;
  94         $LD="ld";               # load from memory
  95         $ST="sd";               # store to memory
  96         $SLL="dsll";            # shift left logical
  97         $SRL="dsrl";            # shift right logical
  98         $ADDU="daddu";
  99         $ROTR="drotr";
 100         @Sigma0=(28,34,39);
 101         @Sigma1=(14,18,41);
 102         @sigma0=( 7, 1, 8);     # right shift first
 103         @sigma1=( 6,19,61);     # right shift first
 104         $lastK=0x817;
 105         $rounds=80;
 106 } else {
 107         $label="256";
 108         $SZ=4;
 109         $LD="lw";               # load from memory
 110         $ST="sw";               # store to memory
 111         $SLL="sll";             # shift left logical
 112         $SRL="srl";             # shift right logical
 113         $ADDU="addu";
 114         $ROTR="rotr";
 115         @Sigma0=( 2,13,22);
 116         @Sigma1=( 6,11,25);
 117         @sigma0=( 3, 7,18);     # right shift first
 118         @sigma1=(10,17,19);     # right shift first
 119         $lastK=0x8f2;
 120         $rounds=64;
 121 }
 122
 123 $MSB = $big_endian ? 0 : ($SZ-1);
 124 $LSB = ($SZ-1)&~$MSB;
 125
 126 @V=($A,$B,$C,$D,$E,$F,$G,$H)=map("\$$_",(1,2,3,7,24,25,30,31));
 127 @X=map("\$$_",(8..23));
 128
 129 $ctx=$a0;
 130 $inp=$a1;
 131 $len=$a2;       $Ktbl=$len;
 132
 133 sub BODY_00_15 {
 134 my ($i,$a,$b,$c,$d,$e,$f,$g,$h)=@_;
 135 my ($T1,$tmp0,$tmp1,$tmp2)=(@X[4],@X[5],@X[6],@X[7]);
 136
 137 $code.=<<___ if ($i<15);
 138 #if defined(_MIPS_ARCH_MIPS32R6) || defined(_MIPS_ARCH_MIPS64R6)
 139         ${LD}   @X[1],`($i+1)*$SZ`($inp)
 140 #else
 141         ${LD}l  @X[1],`($i+1)*$SZ+$MSB`($inp)
 142         ${LD}r  @X[1],`($i+1)*$SZ+$LSB`($inp)
 143 #endif
 144 ___
 145 $code.=<<___    if (!$big_endian && $i<16 && $SZ==4);
 146 #if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
 147         wsbh    @X[0],@X[0]             # byte swap($i)
 148         rotr    @X[0],@X[0],16
 149 #else
 150         srl     $tmp0,@X[0],24          # byte swap($i)
 151         srl     $tmp1,@X[0],8
 152         andi    $tmp2,@X[0],0xFF00
 153         sll     @X[0],@X[0],24
 154         andi    $tmp1,0xFF00
 155         sll     $tmp2,$tmp2,8
 156         or      @X[0],$tmp0
 157         or      $tmp1,$tmp2
 158         or      @X[0],$tmp1
 159 #endif
 160 ___
 161 $code.=<<___    if (!$big_endian && $i<16 && $SZ==8);
 162 #if defined(_MIPS_ARCH_MIPS64R2)
 163         dsbh    @X[0],@X[0]             # byte swap($i)
 164         dshd    @X[0],@X[0]
 165 #else
 166         ori     $tmp0,$zero,0xFF
 167         dsll    $tmp2,$tmp0,32
 168         or      $tmp0,$tmp2             # 0x000000FF000000FF
 169         and     $tmp1,@X[0],$tmp0       # byte swap($i)
 170         dsrl    $tmp2,@X[0],24
 171         dsll    $tmp1,24
 172         and     $tmp2,$tmp0
 173         dsll    $tmp0,8                 # 0x0000FF000000FF00
 174         or      $tmp1,$tmp2
 175         and     $tmp2,@X[0],$tmp0
 176         dsrl    @X[0],8
 177         dsll    $tmp2,8
 178         and     @X[0],$tmp0
 179         or      $tmp1,$tmp2
 180         or      @X[0],$tmp1
 181         dsrl    $tmp1,@X[0],32
 182         dsll    @X[0],32
 183         or      @X[0],$tmp1
 184 #endif
 185 ___
 186 $code.=<<___;
 187 #if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
 188         xor     $tmp2,$f,$g                     # $i
 189         $ROTR   $tmp0,$e,@Sigma1[0]
 190         $ADDU   $T1,$X[0],$h
 191         $ROTR   $tmp1,$e,@Sigma1[1]
 192         and     $tmp2,$e
 193         $ROTR   $h,$e,@Sigma1[2]
 194         xor     $tmp0,$tmp1
 195         $ROTR   $tmp1,$a,@Sigma0[0]
 196         xor     $tmp2,$g                        # Ch(e,f,g)
 197         xor     $tmp0,$h                        # Sigma1(e)
 198
 199         $ROTR   $h,$a,@Sigma0[1]
 200         $ADDU   $T1,$tmp2
 201         $LD     $tmp2,`$i*$SZ`($Ktbl)           # K[$i]
 202         xor     $h,$tmp1
 203         $ROTR   $tmp1,$a,@Sigma0[2]
 204         $ADDU   $T1,$tmp0
 205         and     $tmp0,$b,$c
 206         xor     $h,$tmp1                        # Sigma0(a)
 207         xor     $tmp1,$b,$c
 208 #else
 209         $ADDU   $T1,$X[0],$h                    # $i
 210         $SRL    $h,$e,@Sigma1[0]
 211         xor     $tmp2,$f,$g
 212         $SLL    $tmp1,$e,`$SZ*8-@Sigma1[2]`
 213         and     $tmp2,$e
 214         $SRL    $tmp0,$e,@Sigma1[1]
 215         xor     $h,$tmp1
 216         $SLL    $tmp1,$e,`$SZ*8-@Sigma1[1]`
 217         xor     $h,$tmp0
 218         $SRL    $tmp0,$e,@Sigma1[2]
 219         xor     $h,$tmp1
 220         $SLL    $tmp1,$e,`$SZ*8-@Sigma1[0]`
 221         xor     $h,$tmp0
 222         xor     $tmp2,$g                        # Ch(e,f,g)
 223         xor     $tmp0,$tmp1,$h                  # Sigma1(e)
 224
 225         $SRL    $h,$a,@Sigma0[0]
 226         $ADDU   $T1,$tmp2
 227         $LD     $tmp2,`$i*$SZ`($Ktbl)           # K[$i]
 228         $SLL    $tmp1,$a,`$SZ*8-@Sigma0[2]`
 229         $ADDU   $T1,$tmp0
 230         $SRL    $tmp0,$a,@Sigma0[1]
 231         xor     $h,$tmp1
 232         $SLL    $tmp1,$a,`$SZ*8-@Sigma0[1]`
 233         xor     $h,$tmp0
 234         $SRL    $tmp0,$a,@Sigma0[2]
 235         xor     $h,$tmp1
 236         $SLL    $tmp1,$a,`$SZ*8-@Sigma0[0]`
 237         xor     $h,$tmp0
 238         and     $tmp0,$b,$c
 239         xor     $h,$tmp1                        # Sigma0(a)
 240         xor     $tmp1,$b,$c
 241 #endif
 242         $ST     @X[0],`($i%16)*$SZ`($sp)        # offload to ring buffer
 243         $ADDU   $h,$tmp0
 244         and     $tmp1,$a
 245         $ADDU   $T1,$tmp2                       # +=K[$i]
 246         $ADDU   $h,$tmp1                        # +=Maj(a,b,c)
 247         $ADDU   $d,$T1
 248         $ADDU   $h,$T1
 249 ___
 250 $code.=<<___ if ($i>=13);
 251         $LD     @X[3],`(($i+3)%16)*$SZ`($sp)    # prefetch from ring buffer
 252 ___
 253 }
 254
 255 sub BODY_16_XX {
 256 my $i=@_[0];
 257 my ($tmp0,$tmp1,$tmp2,$tmp3)=(@X[4],@X[5],@X[6],@X[7]);
 258
 259 $code.=<<___;
 260 #if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
 261         $SRL    $tmp2,@X[1],@sigma0[0]          # Xupdate($i)
 262         $ROTR   $tmp0,@X[1],@sigma0[1]
 263         $ADDU   @X[0],@X[9]                     # +=X[i+9]
 264         xor     $tmp2,$tmp0
 265         $ROTR   $tmp0,@X[1],@sigma0[2]
 266
 267         $SRL    $tmp3,@X[14],@sigma1[0]
 268         $ROTR   $tmp1,@X[14],@sigma1[1]
 269         xor     $tmp2,$tmp0                     # sigma0(X[i+1])
 270         $ROTR   $tmp0,@X[14],@sigma1[2]
 271         xor     $tmp3,$tmp1
 272         $ADDU   @X[0],$tmp2
 273 #else
 274         $SRL    $tmp2,@X[1],@sigma0[0]          # Xupdate($i)
 275         $ADDU   @X[0],@X[9]                     # +=X[i+9]
 276         $SLL    $tmp1,@X[1],`$SZ*8-@sigma0[2]`
 277         $SRL    $tmp0,@X[1],@sigma0[1]
 278         xor     $tmp2,$tmp1
 279         $SLL    $tmp1,`@sigma0[2]-@sigma0[1]`
 280         xor     $tmp2,$tmp0
 281         $SRL    $tmp0,@X[1],@sigma0[2]
 282         xor     $tmp2,$tmp1
 283
 284         $SRL    $tmp3,@X[14],@sigma1[0]
 285         xor     $tmp2,$tmp0                     # sigma0(X[i+1])
 286         $SLL    $tmp1,@X[14],`$SZ*8-@sigma1[2]`
 287         $ADDU   @X[0],$tmp2
 288         $SRL    $tmp0,@X[14],@sigma1[1]
 289         xor     $tmp3,$tmp1
 290         $SLL    $tmp1,`@sigma1[2]-@sigma1[1]`
 291         xor     $tmp3,$tmp0
 292         $SRL    $tmp0,@X[14],@sigma1[2]
 293         xor     $tmp3,$tmp1
 294 #endif
 295         xor     $tmp3,$tmp0                     # sigma1(X[i+14])
 296         $ADDU   @X[0],$tmp3
 297 ___
 298         &BODY_00_15(@_);
 299 }
 300
 301 $FRAMESIZE=16*$SZ+16*$SZREG;
 302 $SAVED_REGS_MASK = ($flavour =~ /nubi/i) ? "0xc0fff008" : "0xc0ff0000";
 303
 304 $code.=<<___;
 305 #include "mips_arch.h"
 306
 307 .text
 308 .set    noat
 309 #if !defined(__mips_eabi) && (!defined(__vxworks) || defined(__pic__))
 310 .option pic2
 311 #endif
 312
 313 .align  5
 314 .globl  sha${label}_block_data_order
 315 .ent    sha${label}_block_data_order
 316 sha${label}_block_data_order:
 317         .frame  $sp,$FRAMESIZE,$ra
 318         .mask   $SAVED_REGS_MASK,-$SZREG
 319         .set    noreorder
 320 ___
 321 $code.=<<___ if ($flavour =~ /o32/i);   # o32 PIC-ification
 322         .cpload $pf
 323 ___
 324 $code.=<<___;
 325         $PTR_SUB $sp,$FRAMESIZE
 326         $REG_S  $ra,$FRAMESIZE-1*$SZREG($sp)
 327         $REG_S  $fp,$FRAMESIZE-2*$SZREG($sp)
 328         $REG_S  $s11,$FRAMESIZE-3*$SZREG($sp)
 329         $REG_S  $s10,$FRAMESIZE-4*$SZREG($sp)
 330         $REG_S  $s9,$FRAMESIZE-5*$SZREG($sp)
 331         $REG_S  $s8,$FRAMESIZE-6*$SZREG($sp)
 332         $REG_S  $s7,$FRAMESIZE-7*$SZREG($sp)
 333         $REG_S  $s6,$FRAMESIZE-8*$SZREG($sp)
 334         $REG_S  $s5,$FRAMESIZE-9*$SZREG($sp)
 335         $REG_S  $s4,$FRAMESIZE-10*$SZREG($sp)
 336 ___
 337 $code.=<<___ if ($flavour =~ /nubi/i);  # optimize non-nubi prologue
 338         $REG_S  $s3,$FRAMESIZE-11*$SZREG($sp)
 339         $REG_S  $s2,$FRAMESIZE-12*$SZREG($sp)
 340         $REG_S  $s1,$FRAMESIZE-13*$SZREG($sp)
 341         $REG_S  $s0,$FRAMESIZE-14*$SZREG($sp)
 342         $REG_S  $gp,$FRAMESIZE-15*$SZREG($sp)
 343 ___
 344 $code.=<<___;
 345         $PTR_SLL @X[15],$len,`log(16*$SZ)/log(2)`
 346 ___
 347 $code.=<<___ if ($flavour !~ /o32/i);   # non-o32 PIC-ification
 348         .cplocal        $Ktbl
 349         .cpsetup        $pf,$zero,sha${label}_block_data_order
 350 ___
 351 $code.=<<___;
 352         .set    reorder
 353         $PTR_LA $Ktbl,K${label}         # PIC-ified 'load address'
 354
 355         $LD     $A,0*$SZ($ctx)          # load context
 356         $LD     $B,1*$SZ($ctx)
 357         $LD     $C,2*$SZ($ctx)
 358         $LD     $D,3*$SZ($ctx)
 359         $LD     $E,4*$SZ($ctx)
 360         $LD     $F,5*$SZ($ctx)
 361         $LD     $G,6*$SZ($ctx)
 362         $LD     $H,7*$SZ($ctx)
 363
 364         $PTR_ADD @X[15],$inp            # pointer to the end of input
 365         $REG_S  @X[15],16*$SZ($sp)
 366         b       .Loop
 367
 368 .align  5
 369 .Loop:
 370 #if defined(_MIPS_ARCH_MIPS32R6) || defined(_MIPS_ARCH_MIPS64R6)
 371         ${LD}   @X[0],($inp)
 372 #else
 373         ${LD}l  @X[0],$MSB($inp)
 374         ${LD}r  @X[0],$LSB($inp)
 375 #endif
 376 ___
 377 for ($i=0;$i<16;$i++)
 378 { &BODY_00_15($i,@V); unshift(@V,pop(@V)); push(@X,shift(@X)); }
 379 $code.=<<___;
 380         b       .L16_xx
 381 .align  4
 382 .L16_xx:
 383 ___
 384 for (;$i<32;$i++)
 385 { &BODY_16_XX($i,@V); unshift(@V,pop(@V)); push(@X,shift(@X)); }
 386 $code.=<<___;
 387         and     @X[6],0xfff
 388         li      @X[7],$lastK
 389         .set    noreorder
 390         bne     @X[6],@X[7],.L16_xx
 391         $PTR_ADD $Ktbl,16*$SZ           # Ktbl+=16
 392
 393         $REG_L  @X[15],16*$SZ($sp)      # restore pointer to the end of input
 394         $LD     @X[0],0*$SZ($ctx)
 395         $LD     @X[1],1*$SZ($ctx)
 396         $LD     @X[2],2*$SZ($ctx)
 397         $PTR_ADD $inp,16*$SZ
 398         $LD     @X[3],3*$SZ($ctx)
 399         $ADDU   $A,@X[0]
 400         $LD     @X[4],4*$SZ($ctx)
 401         $ADDU   $B,@X[1]
 402         $LD     @X[5],5*$SZ($ctx)
 403         $ADDU   $C,@X[2]
 404         $LD     @X[6],6*$SZ($ctx)
 405         $ADDU   $D,@X[3]
 406         $LD     @X[7],7*$SZ($ctx)
 407         $ADDU   $E,@X[4]
 408         $ST     $A,0*$SZ($ctx)
 409         $ADDU   $F,@X[5]
 410         $ST     $B,1*$SZ($ctx)
 411         $ADDU   $G,@X[6]
 412         $ST     $C,2*$SZ($ctx)
 413         $ADDU   $H,@X[7]
 414         $ST     $D,3*$SZ($ctx)
 415         $ST     $E,4*$SZ($ctx)
 416         $ST     $F,5*$SZ($ctx)
 417         $ST     $G,6*$SZ($ctx)
 418         $ST     $H,7*$SZ($ctx)
 419
 420         bne     $inp,@X[15],.Loop
 421         $PTR_SUB $Ktbl,`($rounds-16)*$SZ`       # rewind $Ktbl
 422
 423         $REG_L  $ra,$FRAMESIZE-1*$SZREG($sp)
 424         $REG_L  $fp,$FRAMESIZE-2*$SZREG($sp)
 425         $REG_L  $s11,$FRAMESIZE-3*$SZREG($sp)
 426         $REG_L  $s10,$FRAMESIZE-4*$SZREG($sp)
 427         $REG_L  $s9,$FRAMESIZE-5*$SZREG($sp)
 428         $REG_L  $s8,$FRAMESIZE-6*$SZREG($sp)
 429         $REG_L  $s7,$FRAMESIZE-7*$SZREG($sp)
 430         $REG_L  $s6,$FRAMESIZE-8*$SZREG($sp)
 431         $REG_L  $s5,$FRAMESIZE-9*$SZREG($sp)
 432         $REG_L  $s4,$FRAMESIZE-10*$SZREG($sp)
 433 ___
 434 $code.=<<___ if ($flavour =~ /nubi/i);
 435         $REG_L  $s3,$FRAMESIZE-11*$SZREG($sp)
 436         $REG_L  $s2,$FRAMESIZE-12*$SZREG($sp)
 437         $REG_L  $s1,$FRAMESIZE-13*$SZREG($sp)
 438         $REG_L  $s0,$FRAMESIZE-14*$SZREG($sp)
 439         $REG_L  $gp,$FRAMESIZE-15*$SZREG($sp)
 440 ___
 441 $code.=<<___;
 442         jr      $ra
 443         $PTR_ADD $sp,$FRAMESIZE
 444 .end    sha${label}_block_data_order
 445
 446 .rdata
 447 .align  5
 448 K${label}:
 449 ___
 450 if ($SZ==4) {
 451 $code.=<<___;
 452         .word   0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5
 453         .word   0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5
 454         .word   0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3
 455         .word   0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174
 456         .word   0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc
 457         .word   0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da
 458         .word   0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7
 459         .word   0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967
 460         .word   0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13
 461         .word   0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85
 462         .word   0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3
 463         .word   0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070
 464         .word   0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5
 465         .word   0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3
 466         .word   0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208
 467         .word   0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2
 468 ___
 469 } else {
 470 $code.=<<___;
 471         .dword  0x428a2f98d728ae22, 0x7137449123ef65cd
 472         .dword  0xb5c0fbcfec4d3b2f, 0xe9b5dba58189dbbc
 473         .dword  0x3956c25bf348b538, 0x59f111f1b605d019
 474         .dword  0x923f82a4af194f9b, 0xab1c5ed5da6d8118
 475         .dword  0xd807aa98a3030242, 0x12835b0145706fbe
 476         .dword  0x243185be4ee4b28c, 0x550c7dc3d5ffb4e2
 477         .dword  0x72be5d74f27b896f, 0x80deb1fe3b1696b1
 478         .dword  0x9bdc06a725c71235, 0xc19bf174cf692694
 479         .dword  0xe49b69c19ef14ad2, 0xefbe4786384f25e3
 480         .dword  0x0fc19dc68b8cd5b5, 0x240ca1cc77ac9c65
 481         .dword  0x2de92c6f592b0275, 0x4a7484aa6ea6e483
 482         .dword  0x5cb0a9dcbd41fbd4, 0x76f988da831153b5
 483         .dword  0x983e5152ee66dfab, 0xa831c66d2db43210
 484         .dword  0xb00327c898fb213f, 0xbf597fc7beef0ee4
 485         .dword  0xc6e00bf33da88fc2, 0xd5a79147930aa725
 486         .dword  0x06ca6351e003826f, 0x142929670a0e6e70
 487         .dword  0x27b70a8546d22ffc, 0x2e1b21385c26c926
 488         .dword  0x4d2c6dfc5ac42aed, 0x53380d139d95b3df
 489         .dword  0x650a73548baf63de, 0x766a0abb3c77b2a8
 490         .dword  0x81c2c92e47edaee6, 0x92722c851482353b
 491         .dword  0xa2bfe8a14cf10364, 0xa81a664bbc423001
 492         .dword  0xc24b8b70d0f89791, 0xc76c51a30654be30
 493         .dword  0xd192e819d6ef5218, 0xd69906245565a910
 494         .dword  0xf40e35855771202a, 0x106aa07032bbd1b8
 495         .dword  0x19a4c116b8d2d0c8, 0x1e376c085141ab53
 496         .dword  0x2748774cdf8eeb99, 0x34b0bcb5e19b48a8
 497         .dword  0x391c0cb3c5c95a63, 0x4ed8aa4ae3418acb
 498         .dword  0x5b9cca4f7763e373, 0x682e6ff3d6b2b8a3
 499         .dword  0x748f82ee5defb2fc, 0x78a5636f43172f60
 500         .dword  0x84c87814a1f0ab72, 0x8cc702081a6439ec
 501         .dword  0x90befffa23631e28, 0xa4506cebde82bde9
 502         .dword  0xbef9a3f7b2c67915, 0xc67178f2e372532b
 503         .dword  0xca273eceea26619c, 0xd186b8c721c0c207
 504         .dword  0xeada7dd6cde0eb1e, 0xf57d4f7fee6ed178
 505         .dword  0x06f067aa72176fba, 0x0a637dc5a2c898a6
 506         .dword  0x113f9804bef90dae, 0x1b710b35131c471b
 507         .dword  0x28db77f523047d84, 0x32caab7b40c72493
 508         .dword  0x3c9ebe0a15c9bebc, 0x431d67c49c100d4c
 509         .dword  0x4cc5d4becb3e42b6, 0x597f299cfc657e2a
 510         .dword  0x5fcb6fab3ad6faec, 0x6c44198c4a475817
 511 ___
 512 }
 513 $code.=<<___;
 514 .asciiz "SHA${label} for MIPS, CRYPTOGAMS by <appro\@openssl.org>"
 515 .align  5
 516
 517 ___
 518
 519 $code =~ s/\`([^\`]*)\`/eval $1/gem;
 520 print $code;
 521 close STDOUT;