MIPS assembly pack: fix MIPS64 assembler warnings.
[openssl.git] / crypto / sha / asm / sha512-mips.pl
1 #!/usr/bin/env perl
2
3 # ====================================================================
4 # Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
5 # project. The module is, however, dual licensed under OpenSSL and
6 # CRYPTOGAMS licenses depending on where you obtain it. For further
7 # details see http://www.openssl.org/~appro/cryptogams/.
8 # ====================================================================
9
10 # SHA2 block procedures for MIPS.
11
12 # October 2010.
13 #
14 # SHA256 performance improvement on MIPS R5000 CPU is ~27% over gcc-
15 # generated code in o32 build and ~55% in n32/64 build. SHA512 [which
16 # for now can only be compiled for MIPS64 ISA] improvement is modest
17 # ~17%, but it comes for free, because it's same instruction sequence.
18 # Improvement coefficients are for aligned input.
19
20 # September 2012.
21 #
22 # Add MIPS[32|64]R2 code (>25% less instructions).
23
24 ######################################################################
25 # There is a number of MIPS ABI in use, O32 and N32/64 are most
26 # widely used. Then there is a new contender: NUBI. It appears that if
27 # one picks the latter, it's possible to arrange code in ABI neutral
28 # manner. Therefore let's stick to NUBI register layout:
29 #
30 ($zero,$at,$t0,$t1,$t2)=map("\$$_",(0..2,24,25));
31 ($a0,$a1,$a2,$a3,$a4,$a5,$a6,$a7)=map("\$$_",(4..11));
32 ($s0,$s1,$s2,$s3,$s4,$s5,$s6,$s7,$s8,$s9,$s10,$s11)=map("\$$_",(12..23));
33 ($gp,$tp,$sp,$fp,$ra)=map("\$$_",(3,28..31));
34 #
35 # The return value is placed in $a0. Following coding rules facilitate
36 # interoperability:
37 #
38 # - never ever touch $tp, "thread pointer", former $gp [o32 can be
39 #   excluded from the rule, because it's specified volatile];
40 # - copy return value to $t0, former $v0 [or to $a0 if you're adapting
41 #   old code];
42 # - on O32 populate $a4-$a7 with 'lw $aN,4*N($sp)' if necessary;
43 #
44 # For reference here is register layout for N32/64 MIPS ABIs:
45 #
46 # ($zero,$at,$v0,$v1)=map("\$$_",(0..3));
47 # ($a0,$a1,$a2,$a3,$a4,$a5,$a6,$a7)=map("\$$_",(4..11));
48 # ($t0,$t1,$t2,$t3,$t8,$t9)=map("\$$_",(12..15,24,25));
49 # ($s0,$s1,$s2,$s3,$s4,$s5,$s6,$s7)=map("\$$_",(16..23));
50 # ($gp,$sp,$fp,$ra)=map("\$$_",(28..31));
51 #
52 $flavour = shift || "o32"; # supported flavours are o32,n32,64,nubi32,nubi64
53
54 if ($flavour =~ /64|n32/i) {
55         $PTR_LA="dla";
56         $PTR_ADD="dadd";        # incidentally works even on n32
57         $PTR_SUB="dsub";        # incidentally works even on n32
58         $REG_S="sd";
59         $REG_L="ld";
60         $PTR_SLL="dsll";        # incidentally works even on n32
61         $SZREG=8;
62 } else {
63         $PTR_LA="la";
64         $PTR_ADD="add";
65         $PTR_SUB="sub";
66         $REG_S="sw";
67         $REG_L="lw";
68         $PTR_SLL="sll";
69         $SZREG=4;
70 }
71 $pf = ($flavour =~ /nubi/i) ? $t0 : $t2;
72 #
73 # <appro@openssl.org>
74 #
75 ######################################################################
76
77 $big_endian=(`echo MIPSEL | $ENV{CC} -E -`=~/MIPSEL/)?1:0 if ($ENV{CC});
78
79 for (@ARGV) {   $output=$_ if (/\w[\w\-]*\.\w+$/);      }
80 open STDOUT,">$output";
81
82 if (!defined($big_endian)) { $big_endian=(unpack('L',pack('N',1))==1); }
83
84 if ($output =~ /512/) {
85         $label="512";
86         $SZ=8;
87         $LD="ld";               # load from memory
88         $ST="sd";               # store to memory
89         $SLL="dsll";            # shift left logical
90         $SRL="dsrl";            # shift right logical
91         $ADDU="daddu";
92         $ROTR="drotr";
93         @Sigma0=(28,34,39);
94         @Sigma1=(14,18,41);
95         @sigma0=( 7, 1, 8);     # right shift first
96         @sigma1=( 6,19,61);     # right shift first
97         $lastK=0x817;
98         $rounds=80;
99 } else {
100         $label="256";
101         $SZ=4;
102         $LD="lw";               # load from memory
103         $ST="sw";               # store to memory
104         $SLL="sll";             # shift left logical
105         $SRL="srl";             # shift right logical
106         $ADDU="addu";
107         $ROTR="rotr";
108         @Sigma0=( 2,13,22);
109         @Sigma1=( 6,11,25);
110         @sigma0=( 3, 7,18);     # right shift first
111         @sigma1=(10,17,19);     # right shift first
112         $lastK=0x8f2;
113         $rounds=64;
114 }
115
116 $MSB = $big_endian ? 0 : ($SZ-1);
117 $LSB = ($SZ-1)&~$MSB;
118
119 @V=($A,$B,$C,$D,$E,$F,$G,$H)=map("\$$_",(1,2,3,7,24,25,30,31));
120 @X=map("\$$_",(8..23));
121
122 $ctx=$a0;
123 $inp=$a1;
124 $len=$a2;       $Ktbl=$len;
125
126 sub BODY_00_15 {
127 my ($i,$a,$b,$c,$d,$e,$f,$g,$h)=@_;
128 my ($T1,$tmp0,$tmp1,$tmp2)=(@X[4],@X[5],@X[6],@X[7]);
129
130 $code.=<<___ if ($i<15);
131         ${LD}l  @X[1],`($i+1)*$SZ+$MSB`($inp)
132         ${LD}r  @X[1],`($i+1)*$SZ+$LSB`($inp)
133 ___
134 $code.=<<___    if (!$big_endian && $i<16 && $SZ==4);
135 #if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
136         wsbh    @X[0],@X[0]             # byte swap($i)
137         rotr    @X[0],@X[0],16
138 #else
139         srl     $tmp0,@X[0],24          # byte swap($i)
140         srl     $tmp1,@X[0],8
141         andi    $tmp2,@X[0],0xFF00
142         sll     @X[0],@X[0],24
143         andi    $tmp1,0xFF00
144         sll     $tmp2,$tmp2,8
145         or      @X[0],$tmp0
146         or      $tmp1,$tmp2
147         or      @X[0],$tmp1
148 #endif
149 ___
150 $code.=<<___    if (!$big_endian && $i<16 && $SZ==8);
151 #if defined(_MIPS_ARCH_MIPS64R2)
152         dsbh    @X[0],@X[0]             # byte swap($i)
153         dshd    @X[0],@X[0]
154 #else
155         ori     $tmp0,$zero,0xFF
156         dsll    $tmp2,$tmp0,32
157         or      $tmp0,$tmp2             # 0x000000FF000000FF
158         and     $tmp1,@X[0],$tmp0       # byte swap($i)
159         dsrl    $tmp2,@X[0],24
160         dsll    $tmp1,24
161         and     $tmp2,$tmp0
162         dsll    $tmp0,8                 # 0x0000FF000000FF00
163         or      $tmp1,$tmp2
164         and     $tmp2,@X[0],$tmp0
165         dsrl    @X[0],8
166         dsll    $tmp2,8
167         and     @X[0],$tmp0
168         or      $tmp1,$tmp2
169         or      @X[0],$tmp1
170         dsrl    $tmp1,@X[0],32
171         dsll    @X[0],32
172         or      @X[0],$tmp1
173 #endif
174 ___
175 $code.=<<___;
176 #if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
177         xor     $tmp2,$f,$g                     # $i
178         $ROTR   $tmp0,$e,@Sigma1[0]
179         $ADDU   $T1,$X[0],$h
180         $ROTR   $tmp1,$e,@Sigma1[1]
181         and     $tmp2,$e
182         $ROTR   $h,$e,@Sigma1[2]
183         xor     $tmp0,$tmp1
184         $ROTR   $tmp1,$a,@Sigma0[0]
185         xor     $tmp2,$g                        # Ch(e,f,g)
186         xor     $tmp0,$h                        # Sigma1(e)
187
188         $ROTR   $h,$a,@Sigma0[1]
189         $ADDU   $T1,$tmp2
190         $LD     $tmp2,`$i*$SZ`($Ktbl)           # K[$i]
191         xor     $h,$tmp1
192         $ROTR   $tmp1,$a,@Sigma0[2]
193         $ADDU   $T1,$tmp0
194         and     $tmp0,$b,$c
195         xor     $h,$tmp1                        # Sigma0(a)
196         xor     $tmp1,$b,$c
197 #else
198         $ADDU   $T1,$X[0],$h                    # $i
199         $SRL    $h,$e,@Sigma1[0]
200         xor     $tmp2,$f,$g
201         $SLL    $tmp1,$e,`$SZ*8-@Sigma1[2]`
202         and     $tmp2,$e
203         $SRL    $tmp0,$e,@Sigma1[1]
204         xor     $h,$tmp1
205         $SLL    $tmp1,$e,`$SZ*8-@Sigma1[1]`
206         xor     $h,$tmp0
207         $SRL    $tmp0,$e,@Sigma1[2]
208         xor     $h,$tmp1
209         $SLL    $tmp1,$e,`$SZ*8-@Sigma1[0]`
210         xor     $h,$tmp0
211         xor     $tmp2,$g                        # Ch(e,f,g)
212         xor     $tmp0,$tmp1,$h                  # Sigma1(e)
213
214         $SRL    $h,$a,@Sigma0[0]
215         $ADDU   $T1,$tmp2
216         $LD     $tmp2,`$i*$SZ`($Ktbl)           # K[$i]
217         $SLL    $tmp1,$a,`$SZ*8-@Sigma0[2]`
218         $ADDU   $T1,$tmp0
219         $SRL    $tmp0,$a,@Sigma0[1]
220         xor     $h,$tmp1
221         $SLL    $tmp1,$a,`$SZ*8-@Sigma0[1]`
222         xor     $h,$tmp0
223         $SRL    $tmp0,$a,@Sigma0[2]
224         xor     $h,$tmp1
225         $SLL    $tmp1,$a,`$SZ*8-@Sigma0[0]`
226         xor     $h,$tmp0
227         and     $tmp0,$b,$c
228         xor     $h,$tmp1                        # Sigma0(a)
229         xor     $tmp1,$b,$c
230 #endif
231         $ST     @X[0],`($i%16)*$SZ`($sp)        # offload to ring buffer
232         $ADDU   $h,$tmp0
233         and     $tmp1,$a
234         $ADDU   $T1,$tmp2                       # +=K[$i]
235         $ADDU   $h,$tmp1                        # +=Maj(a,b,c)
236         $ADDU   $d,$T1
237         $ADDU   $h,$T1
238 ___
239 $code.=<<___ if ($i>=13);
240         $LD     @X[3],`(($i+3)%16)*$SZ`($sp)    # prefetch from ring buffer
241 ___
242 }
243
244 sub BODY_16_XX {
245 my $i=@_[0];
246 my ($tmp0,$tmp1,$tmp2,$tmp3)=(@X[4],@X[5],@X[6],@X[7]);
247
248 $code.=<<___;
249 #if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
250         $SRL    $tmp2,@X[1],@sigma0[0]          # Xupdate($i)
251         $ROTR   $tmp0,@X[1],@sigma0[1]
252         $ADDU   @X[0],@X[9]                     # +=X[i+9]
253         xor     $tmp2,$tmp0
254         $ROTR   $tmp0,@X[1],@sigma0[2]
255
256         $SRL    $tmp3,@X[14],@sigma1[0]
257         $ROTR   $tmp1,@X[14],@sigma1[1]
258         xor     $tmp2,$tmp0                     # sigma0(X[i+1])
259         $ROTR   $tmp0,@X[14],@sigma1[2]
260         xor     $tmp3,$tmp1
261         $ADDU   @X[0],$tmp2
262 #else
263         $SRL    $tmp2,@X[1],@sigma0[0]          # Xupdate($i)
264         $ADDU   @X[0],@X[9]                     # +=X[i+9]
265         $SLL    $tmp1,@X[1],`$SZ*8-@sigma0[2]`
266         $SRL    $tmp0,@X[1],@sigma0[1]
267         xor     $tmp2,$tmp1
268         $SLL    $tmp1,`@sigma0[2]-@sigma0[1]`
269         xor     $tmp2,$tmp0
270         $SRL    $tmp0,@X[1],@sigma0[2]
271         xor     $tmp2,$tmp1
272
273         $SRL    $tmp3,@X[14],@sigma1[0]
274         xor     $tmp2,$tmp0                     # sigma0(X[i+1])
275         $SLL    $tmp1,@X[14],`$SZ*8-@sigma1[2]`
276         $ADDU   @X[0],$tmp2
277         $SRL    $tmp0,@X[14],@sigma1[1]
278         xor     $tmp3,$tmp1
279         $SLL    $tmp1,`@sigma1[2]-@sigma1[1]`
280         xor     $tmp3,$tmp0
281         $SRL    $tmp0,@X[14],@sigma1[2]
282         xor     $tmp3,$tmp1
283 #endif
284         xor     $tmp3,$tmp0                     # sigma1(X[i+14])
285         $ADDU   @X[0],$tmp3
286 ___
287         &BODY_00_15(@_);
288 }
289
290 $FRAMESIZE=16*$SZ+16*$SZREG;
291 $SAVED_REGS_MASK = ($flavour =~ /nubi/i) ? "0xc0fff008" : "0xc0ff0000";
292
293 $code.=<<___;
294 #ifdef OPENSSL_FIPSCANISTER
295 # include <openssl/fipssyms.h>
296 #endif
297
298 #if defined(__mips_smartmips) && !defined(_MIPS_ARCH_MIPS32R2)
299 #define _MIPS_ARCH_MIPS32R2
300 #endif
301
302 .text
303 .set    noat
304 #if !defined(__mips_eabi) && (!defined(__vxworks) || defined(__pic__))
305 .option pic2
306 #endif
307
308 .align  5
309 .globl  sha${label}_block_data_order
310 .ent    sha${label}_block_data_order
311 sha${label}_block_data_order:
312         .frame  $sp,$FRAMESIZE,$ra
313         .mask   $SAVED_REGS_MASK,-$SZREG
314         .set    noreorder
315 ___
316 $code.=<<___ if ($flavour =~ /o32/i);   # o32 PIC-ification
317         .cpload $pf
318 ___
319 $code.=<<___;
320         $PTR_SUB $sp,$FRAMESIZE
321         $REG_S  $ra,$FRAMESIZE-1*$SZREG($sp)
322         $REG_S  $fp,$FRAMESIZE-2*$SZREG($sp)
323         $REG_S  $s11,$FRAMESIZE-3*$SZREG($sp)
324         $REG_S  $s10,$FRAMESIZE-4*$SZREG($sp)
325         $REG_S  $s9,$FRAMESIZE-5*$SZREG($sp)
326         $REG_S  $s8,$FRAMESIZE-6*$SZREG($sp)
327         $REG_S  $s7,$FRAMESIZE-7*$SZREG($sp)
328         $REG_S  $s6,$FRAMESIZE-8*$SZREG($sp)
329         $REG_S  $s5,$FRAMESIZE-9*$SZREG($sp)
330         $REG_S  $s4,$FRAMESIZE-10*$SZREG($sp)
331 ___
332 $code.=<<___ if ($flavour =~ /nubi/i);  # optimize non-nubi prologue
333         $REG_S  $s3,$FRAMESIZE-11*$SZREG($sp)
334         $REG_S  $s2,$FRAMESIZE-12*$SZREG($sp)
335         $REG_S  $s1,$FRAMESIZE-13*$SZREG($sp)
336         $REG_S  $s0,$FRAMESIZE-14*$SZREG($sp)
337         $REG_S  $gp,$FRAMESIZE-15*$SZREG($sp)
338 ___
339 $code.=<<___;
340         $PTR_SLL @X[15],$len,`log(16*$SZ)/log(2)`
341 ___
342 $code.=<<___ if ($flavour !~ /o32/i);   # non-o32 PIC-ification
343         .cplocal        $Ktbl
344         .cpsetup        $pf,$zero,sha${label}_block_data_order
345 ___
346 $code.=<<___;
347         .set    reorder
348         $PTR_LA $Ktbl,K${label}         # PIC-ified 'load address'
349
350         $LD     $A,0*$SZ($ctx)          # load context
351         $LD     $B,1*$SZ($ctx)
352         $LD     $C,2*$SZ($ctx)
353         $LD     $D,3*$SZ($ctx)
354         $LD     $E,4*$SZ($ctx)
355         $LD     $F,5*$SZ($ctx)
356         $LD     $G,6*$SZ($ctx)
357         $LD     $H,7*$SZ($ctx)
358
359         $PTR_ADD @X[15],$inp            # pointer to the end of input
360         $REG_S  @X[15],16*$SZ($sp)
361         b       .Loop
362
363 .align  5
364 .Loop:
365         ${LD}l  @X[0],$MSB($inp)
366         ${LD}r  @X[0],$LSB($inp)
367 ___
368 for ($i=0;$i<16;$i++)
369 { &BODY_00_15($i,@V); unshift(@V,pop(@V)); push(@X,shift(@X)); }
370 $code.=<<___;
371         b       .L16_xx
372 .align  4
373 .L16_xx:
374 ___
375 for (;$i<32;$i++)
376 { &BODY_16_XX($i,@V); unshift(@V,pop(@V)); push(@X,shift(@X)); }
377 $code.=<<___;
378         and     @X[6],0xfff
379         li      @X[7],$lastK
380         .set    noreorder
381         bne     @X[6],@X[7],.L16_xx
382         $PTR_ADD $Ktbl,16*$SZ           # Ktbl+=16
383
384         $REG_L  @X[15],16*$SZ($sp)      # restore pointer to the end of input
385         $LD     @X[0],0*$SZ($ctx)
386         $LD     @X[1],1*$SZ($ctx)
387         $LD     @X[2],2*$SZ($ctx)
388         $PTR_ADD $inp,16*$SZ
389         $LD     @X[3],3*$SZ($ctx)
390         $ADDU   $A,@X[0]
391         $LD     @X[4],4*$SZ($ctx)
392         $ADDU   $B,@X[1]
393         $LD     @X[5],5*$SZ($ctx)
394         $ADDU   $C,@X[2]
395         $LD     @X[6],6*$SZ($ctx)
396         $ADDU   $D,@X[3]
397         $LD     @X[7],7*$SZ($ctx)
398         $ADDU   $E,@X[4]
399         $ST     $A,0*$SZ($ctx)
400         $ADDU   $F,@X[5]
401         $ST     $B,1*$SZ($ctx)
402         $ADDU   $G,@X[6]
403         $ST     $C,2*$SZ($ctx)
404         $ADDU   $H,@X[7]
405         $ST     $D,3*$SZ($ctx)
406         $ST     $E,4*$SZ($ctx)
407         $ST     $F,5*$SZ($ctx)
408         $ST     $G,6*$SZ($ctx)
409         $ST     $H,7*$SZ($ctx)
410
411         bne     $inp,@X[15],.Loop
412         $PTR_SUB $Ktbl,`($rounds-16)*$SZ`       # rewind $Ktbl
413
414         $REG_L  $ra,$FRAMESIZE-1*$SZREG($sp)
415         $REG_L  $fp,$FRAMESIZE-2*$SZREG($sp)
416         $REG_L  $s11,$FRAMESIZE-3*$SZREG($sp)
417         $REG_L  $s10,$FRAMESIZE-4*$SZREG($sp)
418         $REG_L  $s9,$FRAMESIZE-5*$SZREG($sp)
419         $REG_L  $s8,$FRAMESIZE-6*$SZREG($sp)
420         $REG_L  $s7,$FRAMESIZE-7*$SZREG($sp)
421         $REG_L  $s6,$FRAMESIZE-8*$SZREG($sp)
422         $REG_L  $s5,$FRAMESIZE-9*$SZREG($sp)
423         $REG_L  $s4,$FRAMESIZE-10*$SZREG($sp)
424 ___
425 $code.=<<___ if ($flavour =~ /nubi/i);
426         $REG_L  $s3,$FRAMESIZE-11*$SZREG($sp)
427         $REG_L  $s2,$FRAMESIZE-12*$SZREG($sp)
428         $REG_L  $s1,$FRAMESIZE-13*$SZREG($sp)
429         $REG_L  $s0,$FRAMESIZE-14*$SZREG($sp)
430         $REG_L  $gp,$FRAMESIZE-15*$SZREG($sp)
431 ___
432 $code.=<<___;
433         jr      $ra
434         $PTR_ADD $sp,$FRAMESIZE
435 .end    sha${label}_block_data_order
436
437 .rdata
438 .align  5
439 K${label}:
440 ___
441 if ($SZ==4) {
442 $code.=<<___;
443         .word   0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5
444         .word   0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5
445         .word   0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3
446         .word   0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174
447         .word   0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc
448         .word   0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da
449         .word   0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7
450         .word   0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967
451         .word   0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13
452         .word   0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85
453         .word   0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3
454         .word   0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070
455         .word   0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5
456         .word   0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3
457         .word   0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208
458         .word   0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2
459 ___
460 } else {
461 $code.=<<___;
462         .dword  0x428a2f98d728ae22, 0x7137449123ef65cd
463         .dword  0xb5c0fbcfec4d3b2f, 0xe9b5dba58189dbbc
464         .dword  0x3956c25bf348b538, 0x59f111f1b605d019
465         .dword  0x923f82a4af194f9b, 0xab1c5ed5da6d8118
466         .dword  0xd807aa98a3030242, 0x12835b0145706fbe
467         .dword  0x243185be4ee4b28c, 0x550c7dc3d5ffb4e2
468         .dword  0x72be5d74f27b896f, 0x80deb1fe3b1696b1
469         .dword  0x9bdc06a725c71235, 0xc19bf174cf692694
470         .dword  0xe49b69c19ef14ad2, 0xefbe4786384f25e3
471         .dword  0x0fc19dc68b8cd5b5, 0x240ca1cc77ac9c65
472         .dword  0x2de92c6f592b0275, 0x4a7484aa6ea6e483
473         .dword  0x5cb0a9dcbd41fbd4, 0x76f988da831153b5
474         .dword  0x983e5152ee66dfab, 0xa831c66d2db43210
475         .dword  0xb00327c898fb213f, 0xbf597fc7beef0ee4
476         .dword  0xc6e00bf33da88fc2, 0xd5a79147930aa725
477         .dword  0x06ca6351e003826f, 0x142929670a0e6e70
478         .dword  0x27b70a8546d22ffc, 0x2e1b21385c26c926
479         .dword  0x4d2c6dfc5ac42aed, 0x53380d139d95b3df
480         .dword  0x650a73548baf63de, 0x766a0abb3c77b2a8
481         .dword  0x81c2c92e47edaee6, 0x92722c851482353b
482         .dword  0xa2bfe8a14cf10364, 0xa81a664bbc423001
483         .dword  0xc24b8b70d0f89791, 0xc76c51a30654be30
484         .dword  0xd192e819d6ef5218, 0xd69906245565a910
485         .dword  0xf40e35855771202a, 0x106aa07032bbd1b8
486         .dword  0x19a4c116b8d2d0c8, 0x1e376c085141ab53
487         .dword  0x2748774cdf8eeb99, 0x34b0bcb5e19b48a8
488         .dword  0x391c0cb3c5c95a63, 0x4ed8aa4ae3418acb
489         .dword  0x5b9cca4f7763e373, 0x682e6ff3d6b2b8a3
490         .dword  0x748f82ee5defb2fc, 0x78a5636f43172f60
491         .dword  0x84c87814a1f0ab72, 0x8cc702081a6439ec
492         .dword  0x90befffa23631e28, 0xa4506cebde82bde9
493         .dword  0xbef9a3f7b2c67915, 0xc67178f2e372532b
494         .dword  0xca273eceea26619c, 0xd186b8c721c0c207
495         .dword  0xeada7dd6cde0eb1e, 0xf57d4f7fee6ed178
496         .dword  0x06f067aa72176fba, 0x0a637dc5a2c898a6
497         .dword  0x113f9804bef90dae, 0x1b710b35131c471b
498         .dword  0x28db77f523047d84, 0x32caab7b40c72493
499         .dword  0x3c9ebe0a15c9bebc, 0x431d67c49c100d4c
500         .dword  0x4cc5d4becb3e42b6, 0x597f299cfc657e2a
501         .dword  0x5fcb6fab3ad6faec, 0x6c44198c4a475817
502 ___
503 }
504 $code.=<<___;
505 .asciiz "SHA${label} for MIPS, CRYPTOGAMS by <appro\@openssl.org>"
506 .align  5
507
508 ___
509
510 $code =~ s/\`([^\`]*)\`/eval $1/gem;
511 print $code;
512 close STDOUT;