2 # Copyright 2005-2016 The OpenSSL Project Authors. All Rights Reserved.
4 # Licensed under the OpenSSL license (the "License"). You may not use
5 # this file except in compliance with the License. You can obtain a copy
6 # in the file LICENSE in the source distribution or at
7 # https://www.openssl.org/source/license.html
10 # ====================================================================
11 # Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
12 # project. The module is, however, dual licensed under OpenSSL and
13 # CRYPTOGAMS licenses depending on where you obtain it. For further
14 # details see http://www.openssl.org/~appro/cryptogams/.
15 # ====================================================================
19 # 2.22x RC4 tune-up:-) It should be noted though that my hand [as in
20 # "hand-coded assembler"] doesn't stand for the whole improvement
21 # coefficient. It turned out that eliminating RC4_CHAR from config
22 # line results in ~40% improvement (yes, even for C implementation).
23 # Presumably it has everything to do with AMD cache architecture and
24 # RAW or whatever penalties. Once again! The module *requires* config
25 # line *without* RC4_CHAR! As for coding "secret," I bet on partial
26 # register arithmetics. For example instead of 'inc %r8; and $255,%r8'
27 # I simply 'inc %r8b'. Even though optimization manual discourages
28 # to operate on partial registers, it turned out to be the best bet.
29 # At least for AMD... How IA32E would perform remains to be seen...
33 # As was shown by Marc Bevand reordering of couple of load operations
34 # results in even higher performance gain of 3.3x:-) At least on
35 # Opteron... For reference, 1x in this case is RC4_CHAR C-code
36 # compiled with gcc 3.3.2, which performs at ~54MBps per 1GHz clock.
37 # Latter means that if you want to *estimate* what to expect from
38 # *your* Opteron, then multiply 54 by 3.3 and clock frequency in GHz.
42 # Intel P4 EM64T core was found to run the AMD64 code really slow...
43 # The only way to achieve comparable performance on P4 was to keep
44 # RC4_CHAR. Kind of ironic, huh? As it's apparently impossible to
45 # compose blended code, which would perform even within 30% marginal
46 # on either AMD and Intel platforms, I implement both cases. See
47 # rc4_skey.c for further details...
51 # P4 EM64T core appears to be "allergic" to 64-bit inc/dec. Replacing
52 # those with add/sub results in 50% performance improvement of folded
57 # As was shown by Zou Nanhai loop unrolling can improve Intel EM64T
58 # performance by >30% [unlike P4 32-bit case that is]. But this is
59 # provided that loads are reordered even more aggressively! Both code
60 # paths, AMD64 and EM64T, reorder loads in essentially same manner
61 # as my IA-64 implementation. On Opteron this resulted in modest 5%
62 # improvement [I had to test it], while final Intel P4 performance
63 # achieves respectful 432MBps on 2.8GHz processor now. For reference.
64 # If executed on Xeon, current RC4_CHAR code-path is 2.7x faster than
65 # RC4_INT code-path. While if executed on Opteron, it's only 25%
66 # slower than the RC4_INT one [meaning that if CPU ยต-arch detection
67 # is not implemented, then this final RC4_CHAR code-path should be
68 # preferred, as it provides better *all-round* performance].
72 # Intel Core2 was observed to perform poorly on both code paths:-( It
73 # apparently suffers from some kind of partial register stall, which
74 # occurs in 64-bit mode only [as virtually identical 32-bit loop was
75 # observed to outperform 64-bit one by almost 50%]. Adding two movzb to
76 # cloop1 boosts its performance by 80%! This loop appears to be optimal
77 # fit for Core2 and therefore the code was modified to skip cloop8 on
82 # Intel Westmere was observed to perform suboptimally. Adding yet
83 # another movzb to cloop1 improved performance by almost 50%! Core2
84 # performance is improved too, but nominally...
88 # The only code path that was not modified is P4-specific one. Non-P4
89 # Intel code path optimization is heavily based on submission by Maxim
90 # Perminov, Maxim Locktyukhin and Jim Guilford of Intel. I've used
91 # some of the ideas even in attempt to optmize the original RC4_INT
92 # code path... Current performance in cycles per processed byte (less
93 # is better) and improvement coefficients relative to previous
94 # version of this module are:
100 # Sandy Bridge 4.2/+120%
103 # Ivy Bridge 4.1/+30%
104 # Bulldozer 4.5/+30%(*)
106 # (*) But corresponding loop has less instructions, which should have
107 # positive effect on upcoming Bulldozer, which has one less ALU.
108 # For reference, Intel code runs at 6.8 cpb rate on Opteron.
109 # (**) Note that Core2 result is ~15% lower than corresponding result
110 # for 32-bit code, meaning that it's possible to improve it,
111 # but more than likely at the cost of the others (see rc4-586.pl
112 # to get the idea)...
116 if ($flavour =~ /\./) { $output = $flavour; undef $flavour; }
118 $win64=0; $win64=1 if ($flavour =~ /[nm]asm|mingw64/ || $output =~ /\.asm$/);
120 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
121 ( $xlate="${dir}x86_64-xlate.pl" and -f $xlate ) or
122 ( $xlate="${dir}../../perlasm/x86_64-xlate.pl" and -f $xlate) or
123 die "can't locate x86_64-xlate.pl";
125 open OUT,"| \"$^X\" \"$xlate\" $flavour \"$output\"";
136 .extern OPENSSL_ia32cap_P
139 .type RC4,\@function,4
153 my $len="%r11"; # reassign input arguments
157 my @XX=("%r10","%rsi");
158 my @TX=("%rax","%rbx");
167 mov -8($dat),$XX[0]#b
171 mov OPENSSL_ia32cap_P(%rip),%r8d
176 movl ($dat,$XX[0],4),$TX[0]#d
179 bt \$30,%r8d # Intel CPU?
187 movl ($dat,$YY,4),$TY#d
188 movl $TX[0]#d,($dat,$YY,4)
189 movl $TY#d,($dat,$XX[0],4)
192 movl ($dat,$TX[0],4),$TY#d
193 movl ($dat,$XX[0],4),$TX[0]#d
195 movb $TY#b,($out,$inp)
205 for ($i=0;$i<8;$i++) {
206 $code.=<<___ if ($i==7);
211 movl ($dat,$YY,4),$TY#d
212 movl $TX[0]#d,($dat,$YY,4)
213 movl `4*($i==7?-1:$i)`($dat,$XX[1],4),$TX[1]#d
214 ror \$8,%r8 # ror is redundant when $i=0
215 movl $TY#d,4*$i($dat,$XX[0],4)
217 movb ($dat,$TY,4),%r8b
219 push(@TX,shift(@TX)); #push(@XX,shift(@XX)); # "rotate" registers
245 movl ($dat,$YY,4),$TY#d
246 movl $TX[0]#d,($dat,$YY,4)
247 movl $TY#d,($dat,$XX[0],4)
250 movl ($dat,$TX[0],4),$TY#d
251 movl ($dat,$XX[0],4),$TX[0]#d
253 movb $TY#b,($out,$inp)
263 lea ($dat,$XX[0],4),$XX[1]
268 my $xmm="%xmm".($j&1);
270 $code.=" add \$16,$XX[0]#b\n" if ($i==15);
271 $code.=" movdqu ($inp),%xmm2\n" if ($i==15);
272 $code.=" add $TX[0]#b,$YY#b\n" if ($i<=0);
273 $code.=" movl ($dat,$YY,4),$TY#d\n";
274 $code.=" pxor %xmm0,%xmm2\n" if ($i==0);
275 $code.=" psllq \$8,%xmm1\n" if ($i==0);
276 $code.=" pxor $xmm,$xmm\n" if ($i<=1);
277 $code.=" movl $TX[0]#d,($dat,$YY,4)\n";
278 $code.=" add $TY#b,$TX[0]#b\n";
279 $code.=" movl `4*($j+1)`($XX[1]),$TX[1]#d\n" if ($i<15);
280 $code.=" movz $TX[0]#b,$TX[0]#d\n";
281 $code.=" movl $TY#d,4*$j($XX[1])\n";
282 $code.=" pxor %xmm1,%xmm2\n" if ($i==0);
283 $code.=" lea ($dat,$XX[0],4),$XX[1]\n" if ($i==15);
284 $code.=" add $TX[1]#b,$YY#b\n" if ($i<15);
285 $code.=" pinsrw \$`($j>>1)&7`,($dat,$TX[0],4),$xmm\n";
286 $code.=" movdqu %xmm2,($out,$inp)\n" if ($i==0);
287 $code.=" lea 16($inp),$inp\n" if ($i==0);
288 $code.=" movl ($XX[1]),$TX[1]#d\n" if ($i==15);
297 for ($i=0;$i<16;$i++) {
298 $code.=".Loop16_enter:\n" if ($i==1);
300 push(@TX,shift(@TX)); # "rotate" registers
304 xor $YY,$YY # keyword to partial register
313 movdqu %xmm2,($out,$inp)
323 movl ($dat,$YY,4),$TY#d
324 movl $TX[0]#d,($dat,$YY,4)
325 movl $TY#d,($dat,$XX[0],4)
328 movl ($dat,$TX[0],4),$TY#d
329 movl ($dat,$XX[0],4),$TX[0]#d
331 movb $TY#b,($out,$inp)
340 movzb ($dat,$XX[0]),$TX[0]#d
349 # unroll 2x4-wise, because 64-bit rotates kill Intel P4...
350 for ($i=0;$i<4;$i++) {
354 movzb ($dat,$YY),$TY#d
355 movzb $XX[1]#b,$XX[1]#d
356 movzb ($dat,$XX[1]),$TX[1]#d
357 movb $TX[0]#b,($dat,$YY)
359 movb $TY#b,($dat,$XX[0])
360 jne .Lcmov$i # Intel cmov is sloooow...
367 push(@TX,shift(@TX)); push(@XX,shift(@XX)); # "rotate" registers
369 for ($i=4;$i<8;$i++) {
373 movzb ($dat,$YY),$TY#d
374 movzb $XX[1]#b,$XX[1]#d
375 movzb ($dat,$XX[1]),$TX[1]#d
376 movb $TX[0]#b,($dat,$YY)
378 movb $TY#b,($dat,$XX[0])
379 jne .Lcmov$i # Intel cmov is sloooow...
386 push(@TX,shift(@TX)); push(@XX,shift(@XX)); # "rotate" registers
406 movzb ($dat,$YY),$TY#d
407 movb $TX[0]#b,($dat,$YY)
408 movb $TY#b,($dat,$XX[0])
412 movzb $XX[0]#b,$XX[0]#d
413 movzb ($dat,$TY),$TY#d
414 movzb ($dat,$XX[0]),$TX[0]#d
426 movl $XX[0]#d,-8($dat)
444 .type RC4_set_key,\@function,3
456 mov OPENSSL_ia32cap_P(%rip),$idx#d
457 bt \$20,$idx#d # RC4_CHAR?
463 mov %eax,($dat,%rax,4)
471 mov ($dat,$ido,4),%r10d
472 add ($inp,$len,1),$idx#b
475 mov ($dat,$idx,4),%r11d
477 mov %r10d,($dat,$idx,4)
478 mov %r11d,($dat,$ido,4)
493 mov ($dat,$ido),%r10b
494 add ($inp,$len),$idx#b
497 mov ($dat,$idx),%r11b
501 mov %r10b,($dat,$idx)
502 mov %r11b,($dat,$ido)
513 .size RC4_set_key,.-RC4_set_key
516 .type RC4_options,\@abi-omnipotent
519 lea .Lopts(%rip),%rax
520 mov OPENSSL_ia32cap_P(%rip),%edx
534 .asciz "rc4(8x,char)"
535 .asciz "rc4(16x,int)"
536 .asciz "RC4 for x86_64, CRYPTOGAMS by <appro\@openssl.org>"
538 .size RC4_options,.-RC4_options
541 # EXCEPTION_DISPOSITION handler (EXCEPTION_RECORD *rec,ULONG64 frame,
542 # CONTEXT *context,DISPATCHER_CONTEXT *disp)
550 .extern __imp_RtlVirtualUnwind
551 .type stream_se_handler,\@abi-omnipotent
565 mov 120($context),%rax # pull context->Rax
566 mov 248($context),%rbx # pull context->Rip
568 lea .Lprologue(%rip),%r10
569 cmp %r10,%rbx # context->Rip<prologue label
572 mov 152($context),%rax # pull context->Rsp
574 lea .Lepilogue(%rip),%r10
575 cmp %r10,%rbx # context->Rip>=epilogue label
583 mov %rbx,144($context) # restore context->Rbx
584 mov %r12,216($context) # restore context->R12
585 mov %r13,224($context) # restore context->R13
590 mov %rax,152($context) # restore context->Rsp
591 mov %rsi,168($context) # restore context->Rsi
592 mov %rdi,176($context) # restore context->Rdi
594 jmp .Lcommon_seh_exit
595 .size stream_se_handler,.-stream_se_handler
597 .type key_se_handler,\@abi-omnipotent
611 mov 152($context),%rax # pull context->Rsp
614 mov %rsi,168($context) # restore context->Rsi
615 mov %rdi,176($context) # restore context->Rdi
619 mov 40($disp),%rdi # disp->ContextRecord
620 mov $context,%rsi # context
621 mov \$154,%ecx # sizeof(CONTEXT)
622 .long 0xa548f3fc # cld; rep movsq
625 xor %rcx,%rcx # arg1, UNW_FLAG_NHANDLER
626 mov 8(%rsi),%rdx # arg2, disp->ImageBase
627 mov 0(%rsi),%r8 # arg3, disp->ControlPc
628 mov 16(%rsi),%r9 # arg4, disp->FunctionEntry
629 mov 40(%rsi),%r10 # disp->ContextRecord
630 lea 56(%rsi),%r11 # &disp->HandlerData
631 lea 24(%rsi),%r12 # &disp->EstablisherFrame
632 mov %r10,32(%rsp) # arg5
633 mov %r11,40(%rsp) # arg6
634 mov %r12,48(%rsp) # arg7
635 mov %rcx,56(%rsp) # arg8, (NULL)
636 call *__imp_RtlVirtualUnwind(%rip)
638 mov \$1,%eax # ExceptionContinueSearch
650 .size key_se_handler,.-key_se_handler
658 .rva .LSEH_begin_RC4_set_key
659 .rva .LSEH_end_RC4_set_key
660 .rva .LSEH_info_RC4_set_key
666 .rva stream_se_handler
667 .LSEH_info_RC4_set_key:
675 if ($reg =~ /%r[0-9]+/) { $reg .= $conv; }
676 elsif ($conv eq "b") { $reg =~ s/%[er]([^x]+)x?/%$1l/; }
677 elsif ($conv eq "w") { $reg =~ s/%[er](.+)/%$1/; }
678 elsif ($conv eq "d") { $reg =~ s/%[er](.+)/%e$1/; }
682 $code =~ s/(%[a-z0-9]+)#([bwd])/reg_part($1,$2)/gem;
683 $code =~ s/\`([^\`]*)\`/eval $1/gem;