3 # ====================================================================
4 # [Re]written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
5 # project. The module is, however, dual licensed under OpenSSL and
6 # CRYPTOGAMS licenses depending on where you obtain it. For further
7 # details see http://www.openssl.org/~appro/cryptogams/.
8 # ====================================================================
10 # At some point it became apparent that the original SSLeay RC4
11 # assembler implementation performs suboptimally on latest IA-32
12 # microarchitectures. After re-tuning performance has changed as
20 # (*) This number is actually a trade-off:-) It's possible to
21 # achieve +72%, but at the cost of -48% off PIII performance.
22 # In other words code performing further 13% faster on AMD
23 # would perform almost 2 times slower on Intel PIII...
24 # For reference! This code delivers ~80% of rc4-amd64.pl
25 # performance on the same Opteron machine.
26 # (**) This number requires compressed key schedule set up by
27 # RC4_set_key [see commentary below for further details].
29 # <appro@fy.chalmers.se>
33 # Optimize for Core2 and Westmere [and incidentally Opteron]. Current
34 # performance in cycles per processed byte (less is better) is:
36 # Pentium 10.2 # original numbers
40 # Opteron 6.1/+20% # new MMX numbers
42 # Westmere 5.1/+94%(**)
43 # Sandy Bridge 5.0/+8%
45 # (*) PIII can actually deliver 6.6 cycles per byte with MMX code,
46 # but this specific code performs poorly on Core2. And vice
47 # versa, below MMX/SSE code delivering 5.8/7.1 on Core2 performs
48 # poorly on PIII, at 8.0/14.5:-( As PIII is not a "hot" CPU
49 # [anymore], I chose to discard PIII-specific code path and opt
50 # for original IALU-only code, which is why MMX/SSE code path
51 # is guarded by SSE2 bit (see below), not MMX/SSE.
52 # (**) Performance vs. block size on Core2 and Westmere had a maximum
53 # at ... 64 bytes block size. And it was quite a maximum, 40-60%
54 # in comparison to largest 8KB block size. Above improvement
55 # coefficients are for the largest block size.
57 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
58 push(@INC,"${dir}","${dir}../../perlasm");
61 &asm_init($ARGV[0],"rc4-586.pl");
73 my $func = ($i==0)?*mov:*or;
75 &add (&LB($yy),&LB($tx));
76 &mov ($ty,&DWP(0,$dat,$yy,4));
77 &mov (&DWP(0,$dat,$yy,4),$tx);
78 &mov (&DWP(0,$dat,$xx,4),$ty);
82 &ror ($out,8) if ($i!=0);
84 &mov ($tx,&DWP(0,$dat,$xx,4));
86 &mov ($tx,&wparam(3)); # reload [re-biased] out
88 &$func ($out,&DWP(0,$dat,$ty,4));
92 # >20% faster on Atom and Sandy Bridge[!], 8% faster on Opteron,
93 # but ~40% slower on Core2 and Westmere... Attempt to add movz
94 # brings down Opteron by 25%, Atom and Sandy Bridge by 15%, yet
95 # on Core2 with movz it's almost 20% slower than below alternative
96 # code... Yes, it's a total mess...
98 $RC4_loop_mmx = sub { # SSE actually...
101 my $mm=$i<=0?"mm0":"mm".($i&1);
103 &add (&LB($yy),&LB($tx));
104 &lea (@XX[1],&DWP(1,@XX[0]));
105 &pxor ("mm2","mm0") if ($i==0);
106 &psllq ("mm1",8) if ($i==0);
108 &pxor ("mm0","mm0") if ($i<=0);
109 &mov ($ty,&DWP(0,$dat,$yy,4));
110 &mov (&DWP(0,$dat,$yy,4),$tx);
111 &pxor ("mm1","mm2") if ($i==0);
112 &mov (&DWP(0,$dat,$XX[0],4),$ty);
113 &add (&LB($ty),&LB($tx));
114 &movd (@XX[0],"mm7") if ($i==0);
115 &mov ($tx,&DWP(0,$dat,@XX[1],4));
116 &pxor ("mm1","mm1") if ($i==1);
117 &movq ("mm2",&QWP(0,$inp)) if ($i==1);
118 &movq (&QWP(-8,(@XX[0],$inp)),"mm1") if ($i==0);
119 &pinsrw ($mm,&DWP(0,$dat,$ty,4),$j);
121 push (@XX,shift(@XX)) if ($i>=0);
124 # Using pinsrw here improves performane on Intel CPUs by 2-3%, but
125 # brings down AMD by 7%...
126 $RC4_loop_mmx = sub {
129 &add (&LB($yy),&LB($tx));
130 &psllq ("mm1",8*(($i-1)&7)) if (abs($i)!=1);
131 &mov ($ty,&DWP(0,$dat,$yy,4));
132 &mov (&DWP(0,$dat,$yy,4),$tx);
133 &mov (&DWP(0,$dat,$xx,4),$ty);
136 &movz ($xx,&LB($xx)); # (*)
137 &movz ($ty,&LB($ty)); # (*)
138 &pxor ("mm2",$i==1?"mm0":"mm1") if ($i>=0);
139 &movq ("mm0",&QWP(0,$inp)) if ($i<=0);
140 &movq (&QWP(-8,($out,$inp)),"mm2") if ($i==0);
141 &mov ($tx,&DWP(0,$dat,$xx,4));
142 &movd ($i>0?"mm1":"mm2",&DWP(0,$dat,$ty,4));
144 # (*) This is the key to Core2 and Westmere performance.
145 # Whithout movz out-of-order execution logic confuses
146 # itself and fails to reorder loads and stores. Problem
147 # appears to be fixed in Sandy Bridge...
151 &external_label("OPENSSL_ia32cap_P");
153 # void RC4(RC4_KEY *key,size_t len,const unsigned char *inp,unsigned char *out);
154 &function_begin("RC4");
155 &mov ($dat,&wparam(0)); # load key schedule pointer
156 &mov ($ty, &wparam(1)); # load len
157 &mov ($inp,&wparam(2)); # load inp
158 &mov ($out,&wparam(3)); # load out
160 &xor ($xx,$xx); # avoid partial register stalls
163 &cmp ($ty,0); # safety net
164 &je (&label("abort"));
166 &mov (&LB($xx),&BP(0,$dat)); # load key->x
167 &mov (&LB($yy),&BP(4,$dat)); # load key->y
170 &lea ($tx,&DWP(0,$inp,$ty));
171 &sub ($out,$inp); # re-bias out
172 &mov (&wparam(1),$tx); # save input+len
176 # detect compressed key schedule...
177 &cmp (&DWP(256,$dat),-1);
178 &je (&label("RC4_CHAR"));
180 &mov ($tx,&DWP(0,$dat,$xx,4));
182 &and ($ty,-4); # how many 4-byte chunks?
183 &jz (&label("loop1"));
186 &mov (&wparam(3),$out); # $out as accumulator in these loops
187 &jz (&label("go4loop4"));
189 &picmeup($out,"OPENSSL_ia32cap_P");
190 &bt (&DWP(0,$out),26); # check SSE2 bit [could have been MMX]
191 &jnc (&label("go4loop4"));
193 &mov ($out,&wparam(3)) if (!$alt);
194 &movd ("mm7",&wparam(3)) if ($alt);
196 &lea ($ty,&DWP(-8,$inp,$ty));
197 &mov (&DWP(-4,$dat),$ty); # save input+(len/8)*8-8
200 &jmp(&label("loop_mmx_enter"));
202 &set_label("loop_mmx",16);
204 &set_label("loop_mmx_enter");
205 for ($i=1;$i<8;$i++) { &$RC4_loop_mmx($i); }
207 &xor ($yy,$yy); # this is second key to Core2
208 &mov (&LB($yy),&LB($ty)); # and Westmere performance...
209 &cmp ($inp,&DWP(-4,$dat));
210 &lea ($inp,&DWP(8,$inp));
211 &jb (&label("loop_mmx"));
218 &movq (&QWP(-8,$out,$inp),"mm1");
222 &movq (&QWP(-8,$out,$inp),"mm2");
226 &cmp ($inp,&wparam(1)); # compare to input+len
227 &je (&label("done"));
228 &jmp (&label("loop1"));
230 &set_label("go4loop4",16);
231 &lea ($ty,&DWP(-4,$inp,$ty));
232 &mov (&wparam(2),$ty); # save input+(len/4)*4-4
235 for ($i=0;$i<4;$i++) { RC4_loop($i); }
237 &xor ($out,&DWP(0,$inp));
238 &cmp ($inp,&wparam(2)); # compare to input+(len/4)*4-4
239 &mov (&DWP(0,$tx,$inp),$out);# $tx holds re-biased out here
240 &lea ($inp,&DWP(4,$inp));
241 &mov ($tx,&DWP(0,$dat,$xx,4));
242 &jb (&label("loop4"));
244 &cmp ($inp,&wparam(1)); # compare to input+len
245 &je (&label("done"));
246 &mov ($out,&wparam(3)); # restore $out
248 &set_label("loop1",16);
249 &add (&LB($yy),&LB($tx));
250 &mov ($ty,&DWP(0,$dat,$yy,4));
251 &mov (&DWP(0,$dat,$yy,4),$tx);
252 &mov (&DWP(0,$dat,$xx,4),$ty);
256 &mov ($ty,&DWP(0,$dat,$ty,4));
257 &xor (&LB($ty),&BP(0,$inp));
258 &lea ($inp,&DWP(1,$inp));
259 &mov ($tx,&DWP(0,$dat,$xx,4));
260 &cmp ($inp,&wparam(1)); # compare to input+len
261 &mov (&BP(-1,$out,$inp),&LB($ty));
262 &jb (&label("loop1"));
264 &jmp (&label("done"));
266 # this is essentially Intel P4 specific codepath...
267 &set_label("RC4_CHAR",16);
268 &movz ($tx,&BP(0,$dat,$xx));
269 # strangely enough unrolled loop performs over 20% slower...
270 &set_label("cloop1");
271 &add (&LB($yy),&LB($tx));
272 &movz ($ty,&BP(0,$dat,$yy));
273 &mov (&BP(0,$dat,$yy),&LB($tx));
274 &mov (&BP(0,$dat,$xx),&LB($ty));
275 &add (&LB($ty),&LB($tx));
276 &movz ($ty,&BP(0,$dat,$ty));
278 &xor (&LB($ty),&BP(0,$inp));
279 &lea ($inp,&DWP(1,$inp));
280 &movz ($tx,&BP(0,$dat,$xx));
281 &cmp ($inp,&wparam(1));
282 &mov (&BP(-1,$out,$inp),&LB($ty));
283 &jb (&label("cloop1"));
287 &mov (&DWP(-4,$dat),$yy); # save key->y
288 &mov (&BP(-8,$dat),&LB($xx)); # save key->x
290 &function_end("RC4");
292 ########################################################################
300 # void RC4_set_key(RC4_KEY *key,int len,const unsigned char *data);
301 &function_begin("RC4_set_key");
302 &mov ($out,&wparam(0)); # load key
303 &mov ($idi,&wparam(1)); # load len
304 &mov ($inp,&wparam(2)); # load data
305 &picmeup($idx,"OPENSSL_ia32cap_P");
307 &lea ($out,&DWP(2*4,$out)); # &key->data
308 &lea ($inp,&DWP(0,$inp,$idi)); # $inp to point at the end
311 &mov (&DWP(-4,$out),$idi); # borrow key->y
313 &bt (&DWP(0,$idx),20); # check for bit#20
314 &jc (&label("c1stloop"));
316 &set_label("w1stloop",16);
317 &mov (&DWP(0,$out,"eax",4),"eax"); # key->data[i]=i;
318 &add (&LB("eax"),1); # i++;
319 &jnc (&label("w1stloop"));
324 &set_label("w2ndloop",16);
325 &mov ("eax",&DWP(0,$out,$ido,4));
326 &add (&LB($idx),&BP(0,$inp,$idi));
327 &add (&LB($idx),&LB("eax"));
329 &mov ("ebx",&DWP(0,$out,$idx,4));
330 &jnz (&label("wnowrap"));
331 &mov ($idi,&DWP(-4,$out));
332 &set_label("wnowrap");
333 &mov (&DWP(0,$out,$idx,4),"eax");
334 &mov (&DWP(0,$out,$ido,4),"ebx");
336 &jnc (&label("w2ndloop"));
337 &jmp (&label("exit"));
339 # Unlike all other x86 [and x86_64] implementations, Intel P4 core
340 # [including EM64T] was found to perform poorly with above "32-bit" key
341 # schedule, a.k.a. RC4_INT. Performance improvement for IA-32 hand-coded
342 # assembler turned out to be 3.5x if re-coded for compressed 8-bit one,
343 # a.k.a. RC4_CHAR! It's however inappropriate to just switch to 8-bit
344 # schedule for x86[_64], because non-P4 implementations suffer from
345 # significant performance losses then, e.g. PIII exhibits >2x
346 # deterioration, and so does Opteron. In order to assure optimal
347 # all-round performance, we detect P4 at run-time and set up compressed
348 # key schedule, which is recognized by RC4 procedure.
350 &set_label("c1stloop",16);
351 &mov (&BP(0,$out,"eax"),&LB("eax")); # key->data[i]=i;
352 &add (&LB("eax"),1); # i++;
353 &jnc (&label("c1stloop"));
359 &set_label("c2ndloop",16);
360 &mov (&LB("eax"),&BP(0,$out,$ido));
361 &add (&LB($idx),&BP(0,$inp,$idi));
362 &add (&LB($idx),&LB("eax"));
364 &mov (&LB("ebx"),&BP(0,$out,$idx));
365 &jnz (&label("cnowrap"));
366 &mov ($idi,&DWP(-4,$out));
367 &set_label("cnowrap");
368 &mov (&BP(0,$out,$idx),&LB("eax"));
369 &mov (&BP(0,$out,$ido),&LB("ebx"));
371 &jnc (&label("c2ndloop"));
373 &mov (&DWP(256,$out),-1); # mark schedule as compressed
377 &mov (&DWP(-8,$out),"eax"); # key->x=0;
378 &mov (&DWP(-4,$out),"eax"); # key->y=0;
379 &function_end("RC4_set_key");
381 # const char *RC4_options(void);
382 &function_begin_B("RC4_options");
383 &call (&label("pic_point"));
384 &set_label("pic_point");
386 &lea ("eax",&DWP(&label("opts")."-".&label("pic_point"),"eax"));
387 &picmeup("edx","OPENSSL_ia32cap_P");
388 &mov ("edx",&DWP(0,"edx"));
390 &jc (&label("1xchar"));
392 &jnc (&label("ret"));
395 &set_label("1xchar");
399 &set_label("opts",64);
400 &asciz ("rc4(4x,int)");
401 &asciz ("rc4(1x,char)");
402 &asciz ("rc4(8x,mmx)");
403 &asciz ("RC4 for x86, CRYPTOGAMS by <appro\@openssl.org>");
405 &function_end_B("RC4_options");