9 $under=($::netware)?'':'_';
16 { if ($opcode =~ m/^j/o && $#_==0) # optimize jumps
17 { $_[0] = "NEAR $_[0]"; }
18 elsif ($opcode eq "lea" && $#_==1)# wipe storage qualifier from lea
19 { $_[1] =~ s/^[^\[]*\[/\[/o; }
25 # opcodes not covered by ::generic above, mostly inconsistent namings...
27 sub ::movz { &::movzx(@_); }
28 sub ::pushf { &::pushfd; }
29 sub ::popf { &::popfd; }
31 sub ::call { &::emit("call",(&islabel($_[0]) or "$under$_[0]")); }
32 sub ::call_ptr { &::emit("call",@_); }
33 sub ::jmp_ptr { &::emit("jmp",@_); }
35 # chosen SSE instructions
37 { my($p1,$p2,$optimize)=@_;
39 if ($optimize && $p1=~/^mm[0-7]$/ && $p2=~/^mm[0-7]$/)
40 # movq between mmx registers can sink Intel CPUs
41 { &::pshufw($p1,$p2,0xe4); }
43 { &::emit("movq",@_); }
45 sub ::pshufw { &::emit("pshufw",@_); }
48 { my($size,$addr,$reg1,$reg2,$idx)=@_;
53 $ret .= " PTR" if ($::mwerks);
59 # prepend global references with optional underscore
60 $addr =~ s/^([^\+\-0-9][^\+\-]*)/islabel($1) or "$under$1"/ige;
61 # put address arithmetic expression in parenthesis
62 $addr="($addr)" if ($addr =~ /^.+[\-\+].+$/);
64 if (($addr ne "") && ($addr ne 0))
65 { if ($addr !~ /^-/) { $ret .= "$addr+"; }
72 $ret .= "+$reg1" if ($reg1 ne "");
78 $ret =~ s/\+\]/]/; # in case $addr was the only argument
82 sub ::BP { &get_mem("BYTE",@_); }
83 sub ::DWP { &get_mem("DWORD",@_); }
84 sub ::QWP { &get_mem("QWORD",@_); }
85 sub ::BC { (($::mwerks)?"":"BYTE ")."@_"; }
86 sub ::DWC { (($::mwerks)?"":"DWORD ")."@_"; }
89 { if ($::mwerks) { push(@out,".section\t.text\n"); }
93 section code use32 class=code align=64
95 section .text code align=64
102 sub ::function_begin_B
103 { my $func=$under.shift;
114 foreach $i (%label) { undef $label{$i} if ($label{$i} =~ /^$prfx/); }
119 { # try to detect if SSE2 or MMX extensions were used on Win32...
120 if ($::win32 && grep {/\s+[x]*mm[0-7]/i} @out)
121 { # One can argue that it's wasteful to craft every
122 # SSE/MMX module with this snippet... Well, it's 72
123 # bytes long and for the moment we have two modules.
124 # Let's argue when we have 7 modules or so...
126 # $1<<10 sets a reserved bit to signal that variable
127 # was initialized already...
130 ${lprfx}OPENSSL_ia32cap_init:
131 lea edx,[${under}OPENSSL_ia32cap_P]
133 jne NEAR ${lprfx}nocpuid
134 mov DWORD [edx],1<<10
145 jnc NEAR ${lprfx}nocpuid
158 segment .CRT\$XCU rdata align=4
159 dd ${lprfx}OPENSSL_ia32cap_init
161 common ${under}OPENSSL_ia32cap_P 4
167 sub ::comment { foreach (@_) { push(@out,"\t; $_\n"); } }
169 sub islabel # see is argument is known label
171 foreach $i (%label) { return $label{$i} if ($label{$i} eq $_[0]); }
178 { push(@out,".") if ($::mwerks);
179 push(@out, "extern\t${under}$_\n");
184 { $label{$_[0]}="${under}${_[0]}" if (!defined($label{$_[0]}));
185 push(@out,"global\t$label{$_[0]}\n");
189 { if (!defined($label{$_[0]}))
190 { $label{$_[0]}="${lprfx}${label}${_[0]}"; $label++; }
195 { my $label=&::label($_[0]);
196 &::align($_[1]) if ($_[1]>1);
197 push(@out,"$label{$_[0]}:\n");
201 { push(@out,(($::mwerks)?".byte\t":"db\t").join(',',@_)."\n"); }
204 { push(@out,(($::mwerks)?".long\t":"dd\t").join(',',@_)."\n"); }
207 { push(@out,".") if ($::mwerks); push(@out,"align\t$_[0]\n"); }
211 &::lea($dst,&::DWP($sym));
215 { my($f)=$under.shift;
218 segment .CRT\$XCU rdata align=4