5fcd0b9d032ba04189eefef8b81b6acfb63f61fa
[openssl.git] / crypto / modes / asm / ghashv8-armx.pl
1 #! /usr/bin/env perl
2 # Copyright 2014-2016 The OpenSSL Project Authors. All Rights Reserved.
3 #
4 # Licensed under the OpenSSL license (the "License").  You may not use
5 # this file except in compliance with the License.  You can obtain a copy
6 # in the file LICENSE in the source distribution or at
7 # https://www.openssl.org/source/license.html
8
9 #
10 # ====================================================================
11 # Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
12 # project. The module is, however, dual licensed under OpenSSL and
13 # CRYPTOGAMS licenses depending on where you obtain it. For further
14 # details see http://www.openssl.org/~appro/cryptogams/.
15 # ====================================================================
16 #
17 # GHASH for ARMv8 Crypto Extension, 64-bit polynomial multiplication.
18 #
19 # June 2014
20 #
21 # Initial version was developed in tight cooperation with Ard
22 # Biesheuvel <ard.biesheuvel@linaro.org> from bits-n-pieces from
23 # other assembly modules. Just like aesv8-armx.pl this module
24 # supports both AArch32 and AArch64 execution modes.
25 #
26 # July 2014
27 #
28 # Implement 2x aggregated reduction [see ghash-x86.pl for background
29 # information].
30 #
31 # Current performance in cycles per processed byte:
32 #
33 #               PMULL[2]        32-bit NEON(*)
34 # Apple A7      0.92            5.62
35 # Cortex-A53    1.01            8.39
36 # Cortex-A57    1.17            7.61
37 # Denver        0.71            6.02
38 #
39 # (*)   presented for reference/comparison purposes;
40
41 $flavour = shift;
42 $output  = shift;
43
44 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
45 ( $xlate="${dir}arm-xlate.pl" and -f $xlate ) or
46 ( $xlate="${dir}../../perlasm/arm-xlate.pl" and -f $xlate) or
47 die "can't locate arm-xlate.pl";
48
49 open OUT,"| \"$^X\" $xlate $flavour $output";
50 *STDOUT=*OUT;
51
52 $Xi="x0";       # argument block
53 $Htbl="x1";
54 $inp="x2";
55 $len="x3";
56
57 $inc="x12";
58
59 {
60 my ($Xl,$Xm,$Xh,$IN)=map("q$_",(0..3));
61 my ($t0,$t1,$t2,$xC2,$H,$Hhl,$H2)=map("q$_",(8..14));
62
63 $code=<<___;
64 #include "arm_arch.h"
65
66 .text
67 ___
68 $code.=".arch   armv8-a+crypto\n"       if ($flavour =~ /64/);
69 $code.=".fpu    neon\n.code     32\n"   if ($flavour !~ /64/);
70
71 ################################################################################
72 # void gcm_init_v8(u128 Htable[16],const u64 H[2]);
73 #
74 # input:        128-bit H - secret parameter E(K,0^128)
75 # output:       precomputed table filled with degrees of twisted H;
76 #               H is twisted to handle reverse bitness of GHASH;
77 #               only few of 16 slots of Htable[16] are used;
78 #               data is opaque to outside world (which allows to
79 #               optimize the code independently);
80 #
81 $code.=<<___;
82 .global gcm_init_v8
83 .type   gcm_init_v8,%function
84 .align  4
85 gcm_init_v8:
86         vld1.64         {$t1},[x1]              @ load input H
87         vmov.i8         $xC2,#0xe1
88         vshl.i64        $xC2,$xC2,#57           @ 0xc2.0
89         vext.8          $IN,$t1,$t1,#8
90         vshr.u64        $t2,$xC2,#63
91         vdup.32         $t1,${t1}[1]
92         vext.8          $t0,$t2,$xC2,#8         @ t0=0xc2....01
93         vshr.u64        $t2,$IN,#63
94         vshr.s32        $t1,$t1,#31             @ broadcast carry bit
95         vand            $t2,$t2,$t0
96         vshl.i64        $IN,$IN,#1
97         vext.8          $t2,$t2,$t2,#8
98         vand            $t0,$t0,$t1
99         vorr            $IN,$IN,$t2             @ H<<<=1
100         veor            $H,$IN,$t0              @ twisted H
101         vst1.64         {$H},[x0],#16           @ store Htable[0]
102
103         @ calculate H^2
104         vext.8          $t0,$H,$H,#8            @ Karatsuba pre-processing
105         vpmull.p64      $Xl,$H,$H
106         veor            $t0,$t0,$H
107         vpmull2.p64     $Xh,$H,$H
108         vpmull.p64      $Xm,$t0,$t0
109
110         vext.8          $t1,$Xl,$Xh,#8          @ Karatsuba post-processing
111         veor            $t2,$Xl,$Xh
112         veor            $Xm,$Xm,$t1
113         veor            $Xm,$Xm,$t2
114         vpmull.p64      $t2,$Xl,$xC2            @ 1st phase
115
116         vmov            $Xh#lo,$Xm#hi           @ Xh|Xm - 256-bit result
117         vmov            $Xm#hi,$Xl#lo           @ Xm is rotated Xl
118         veor            $Xl,$Xm,$t2
119
120         vext.8          $t2,$Xl,$Xl,#8          @ 2nd phase
121         vpmull.p64      $Xl,$Xl,$xC2
122         veor            $t2,$t2,$Xh
123         veor            $H2,$Xl,$t2
124
125         vext.8          $t1,$H2,$H2,#8          @ Karatsuba pre-processing
126         veor            $t1,$t1,$H2
127         vext.8          $Hhl,$t0,$t1,#8         @ pack Karatsuba pre-processed
128         vst1.64         {$Hhl-$H2},[x0]         @ store Htable[1..2]
129
130         ret
131 .size   gcm_init_v8,.-gcm_init_v8
132 ___
133 ################################################################################
134 # void gcm_gmult_v8(u64 Xi[2],const u128 Htable[16]);
135 #
136 # input:        Xi - current hash value;
137 #               Htable - table precomputed in gcm_init_v8;
138 # output:       Xi - next hash value Xi;
139 #
140 $code.=<<___;
141 .global gcm_gmult_v8
142 .type   gcm_gmult_v8,%function
143 .align  4
144 gcm_gmult_v8:
145         vld1.64         {$t1},[$Xi]             @ load Xi
146         vmov.i8         $xC2,#0xe1
147         vld1.64         {$H-$Hhl},[$Htbl]       @ load twisted H, ...
148         vshl.u64        $xC2,$xC2,#57
149 #ifndef __ARMEB__
150         vrev64.8        $t1,$t1
151 #endif
152         vext.8          $IN,$t1,$t1,#8
153
154         vpmull.p64      $Xl,$H,$IN              @ H.lo·Xi.lo
155         veor            $t1,$t1,$IN             @ Karatsuba pre-processing
156         vpmull2.p64     $Xh,$H,$IN              @ H.hi·Xi.hi
157         vpmull.p64      $Xm,$Hhl,$t1            @ (H.lo+H.hi)·(Xi.lo+Xi.hi)
158
159         vext.8          $t1,$Xl,$Xh,#8          @ Karatsuba post-processing
160         veor            $t2,$Xl,$Xh
161         veor            $Xm,$Xm,$t1
162         veor            $Xm,$Xm,$t2
163         vpmull.p64      $t2,$Xl,$xC2            @ 1st phase of reduction
164
165         vmov            $Xh#lo,$Xm#hi           @ Xh|Xm - 256-bit result
166         vmov            $Xm#hi,$Xl#lo           @ Xm is rotated Xl
167         veor            $Xl,$Xm,$t2
168
169         vext.8          $t2,$Xl,$Xl,#8          @ 2nd phase of reduction
170         vpmull.p64      $Xl,$Xl,$xC2
171         veor            $t2,$t2,$Xh
172         veor            $Xl,$Xl,$t2
173
174 #ifndef __ARMEB__
175         vrev64.8        $Xl,$Xl
176 #endif
177         vext.8          $Xl,$Xl,$Xl,#8
178         vst1.64         {$Xl},[$Xi]             @ write out Xi
179
180         ret
181 .size   gcm_gmult_v8,.-gcm_gmult_v8
182 ___
183 ################################################################################
184 # void gcm_ghash_v8(u64 Xi[2],const u128 Htable[16],const u8 *inp,size_t len);
185 #
186 # input:        table precomputed in gcm_init_v8;
187 #               current hash value Xi;
188 #               pointer to input data;
189 #               length of input data in bytes, but divisible by block size;
190 # output:       next hash value Xi;
191 #
192 $code.=<<___;
193 .global gcm_ghash_v8
194 .type   gcm_ghash_v8,%function
195 .align  4
196 gcm_ghash_v8:
197 ___
198 $code.=<<___            if ($flavour !~ /64/);
199         vstmdb          sp!,{d8-d15}            @ 32-bit ABI says so
200 ___
201 $code.=<<___;
202         vld1.64         {$Xl},[$Xi]             @ load [rotated] Xi
203                                                 @ "[rotated]" means that
204                                                 @ loaded value would have
205                                                 @ to be rotated in order to
206                                                 @ make it appear as in
207                                                 @ alorithm specification
208         subs            $len,$len,#32           @ see if $len is 32 or larger
209         mov             $inc,#16                @ $inc is used as post-
210                                                 @ increment for input pointer;
211                                                 @ as loop is modulo-scheduled
212                                                 @ $inc is zeroed just in time
213                                                 @ to preclude oversteping
214                                                 @ inp[len], which means that
215                                                 @ last block[s] are actually
216                                                 @ loaded twice, but last
217                                                 @ copy is not processed
218         vld1.64         {$H-$Hhl},[$Htbl],#32   @ load twisted H, ..., H^2
219         vmov.i8         $xC2,#0xe1
220         vld1.64         {$H2},[$Htbl]
221         cclr            $inc,eq                 @ is it time to zero $inc?
222         vext.8          $Xl,$Xl,$Xl,#8          @ rotate Xi
223         vld1.64         {$t0},[$inp],#16        @ load [rotated] I[0]
224         vshl.u64        $xC2,$xC2,#57           @ compose 0xc2.0 constant
225 #ifndef __ARMEB__
226         vrev64.8        $t0,$t0
227         vrev64.8        $Xl,$Xl
228 #endif
229         vext.8          $IN,$t0,$t0,#8          @ rotate I[0]
230         b.lo            .Lodd_tail_v8           @ $len was less than 32
231 ___
232 { my ($Xln,$Xmn,$Xhn,$In) = map("q$_",(4..7));
233         #######
234         # Xi+2 =[H*(Ii+1 + Xi+1)] mod P =
235         #       [(H*Ii+1) + (H*Xi+1)] mod P =
236         #       [(H*Ii+1) + H^2*(Ii+Xi)] mod P
237         #
238 $code.=<<___;
239         vld1.64         {$t1},[$inp],$inc       @ load [rotated] I[1]
240 #ifndef __ARMEB__
241         vrev64.8        $t1,$t1
242 #endif
243         vext.8          $In,$t1,$t1,#8
244         veor            $IN,$IN,$Xl             @ I[i]^=Xi
245         vpmull.p64      $Xln,$H,$In             @ H·Ii+1
246         veor            $t1,$t1,$In             @ Karatsuba pre-processing
247         vpmull2.p64     $Xhn,$H,$In
248         b               .Loop_mod2x_v8
249
250 .align  4
251 .Loop_mod2x_v8:
252         vext.8          $t2,$IN,$IN,#8
253         subs            $len,$len,#32           @ is there more data?
254         vpmull.p64      $Xl,$H2,$IN             @ H^2.lo·Xi.lo
255         cclr            $inc,lo                 @ is it time to zero $inc?
256
257          vpmull.p64     $Xmn,$Hhl,$t1
258         veor            $t2,$t2,$IN             @ Karatsuba pre-processing
259         vpmull2.p64     $Xh,$H2,$IN             @ H^2.hi·Xi.hi
260         veor            $Xl,$Xl,$Xln            @ accumulate
261         vpmull2.p64     $Xm,$Hhl,$t2            @ (H^2.lo+H^2.hi)·(Xi.lo+Xi.hi)
262          vld1.64        {$t0},[$inp],$inc       @ load [rotated] I[i+2]
263
264         veor            $Xh,$Xh,$Xhn
265          cclr           $inc,eq                 @ is it time to zero $inc?
266         veor            $Xm,$Xm,$Xmn
267
268         vext.8          $t1,$Xl,$Xh,#8          @ Karatsuba post-processing
269         veor            $t2,$Xl,$Xh
270         veor            $Xm,$Xm,$t1
271          vld1.64        {$t1},[$inp],$inc       @ load [rotated] I[i+3]
272 #ifndef __ARMEB__
273          vrev64.8       $t0,$t0
274 #endif
275         veor            $Xm,$Xm,$t2
276         vpmull.p64      $t2,$Xl,$xC2            @ 1st phase of reduction
277
278 #ifndef __ARMEB__
279          vrev64.8       $t1,$t1
280 #endif
281         vmov            $Xh#lo,$Xm#hi           @ Xh|Xm - 256-bit result
282         vmov            $Xm#hi,$Xl#lo           @ Xm is rotated Xl
283          vext.8         $In,$t1,$t1,#8
284          vext.8         $IN,$t0,$t0,#8
285         veor            $Xl,$Xm,$t2
286          vpmull.p64     $Xln,$H,$In             @ H·Ii+1
287         veor            $IN,$IN,$Xh             @ accumulate $IN early
288
289         vext.8          $t2,$Xl,$Xl,#8          @ 2nd phase of reduction
290         vpmull.p64      $Xl,$Xl,$xC2
291         veor            $IN,$IN,$t2
292          veor           $t1,$t1,$In             @ Karatsuba pre-processing
293         veor            $IN,$IN,$Xl
294          vpmull2.p64    $Xhn,$H,$In
295         b.hs            .Loop_mod2x_v8          @ there was at least 32 more bytes
296
297         veor            $Xh,$Xh,$t2
298         vext.8          $IN,$t0,$t0,#8          @ re-construct $IN
299         adds            $len,$len,#32           @ re-construct $len
300         veor            $Xl,$Xl,$Xh             @ re-construct $Xl
301         b.eq            .Ldone_v8               @ is $len zero?
302 ___
303 }
304 $code.=<<___;
305 .Lodd_tail_v8:
306         vext.8          $t2,$Xl,$Xl,#8
307         veor            $IN,$IN,$Xl             @ inp^=Xi
308         veor            $t1,$t0,$t2             @ $t1 is rotated inp^Xi
309
310         vpmull.p64      $Xl,$H,$IN              @ H.lo·Xi.lo
311         veor            $t1,$t1,$IN             @ Karatsuba pre-processing
312         vpmull2.p64     $Xh,$H,$IN              @ H.hi·Xi.hi
313         vpmull.p64      $Xm,$Hhl,$t1            @ (H.lo+H.hi)·(Xi.lo+Xi.hi)
314
315         vext.8          $t1,$Xl,$Xh,#8          @ Karatsuba post-processing
316         veor            $t2,$Xl,$Xh
317         veor            $Xm,$Xm,$t1
318         veor            $Xm,$Xm,$t2
319         vpmull.p64      $t2,$Xl,$xC2            @ 1st phase of reduction
320
321         vmov            $Xh#lo,$Xm#hi           @ Xh|Xm - 256-bit result
322         vmov            $Xm#hi,$Xl#lo           @ Xm is rotated Xl
323         veor            $Xl,$Xm,$t2
324
325         vext.8          $t2,$Xl,$Xl,#8          @ 2nd phase of reduction
326         vpmull.p64      $Xl,$Xl,$xC2
327         veor            $t2,$t2,$Xh
328         veor            $Xl,$Xl,$t2
329
330 .Ldone_v8:
331 #ifndef __ARMEB__
332         vrev64.8        $Xl,$Xl
333 #endif
334         vext.8          $Xl,$Xl,$Xl,#8
335         vst1.64         {$Xl},[$Xi]             @ write out Xi
336
337 ___
338 $code.=<<___            if ($flavour !~ /64/);
339         vldmia          sp!,{d8-d15}            @ 32-bit ABI says so
340 ___
341 $code.=<<___;
342         ret
343 .size   gcm_ghash_v8,.-gcm_ghash_v8
344 ___
345 }
346 $code.=<<___;
347 .asciz  "GHASH for ARMv8, CRYPTOGAMS by <appro\@openssl.org>"
348 .align  2
349 ___
350
351 if ($flavour =~ /64/) {                 ######## 64-bit code
352     sub unvmov {
353         my $arg=shift;
354
355         $arg =~ m/q([0-9]+)#(lo|hi),\s*q([0-9]+)#(lo|hi)/o &&
356         sprintf "ins    v%d.d[%d],v%d.d[%d]",$1,($2 eq "lo")?0:1,$3,($4 eq "lo")?0:1;
357     }
358     foreach(split("\n",$code)) {
359         s/cclr\s+([wx])([^,]+),\s*([a-z]+)/csel $1$2,$1zr,$1$2,$3/o     or
360         s/vmov\.i8/movi/o               or      # fix up legacy mnemonics
361         s/vmov\s+(.*)/unvmov($1)/geo    or
362         s/vext\.8/ext/o                 or
363         s/vshr\.s/sshr\.s/o             or
364         s/vshr/ushr/o                   or
365         s/^(\s+)v/$1/o                  or      # strip off v prefix
366         s/\bbx\s+lr\b/ret/o;
367
368         s/\bq([0-9]+)\b/"v".($1<8?$1:$1+8).".16b"/geo;  # old->new registers
369         s/@\s/\/\//o;                           # old->new style commentary
370
371         # fix up remainig legacy suffixes
372         s/\.[ui]?8(\s)/$1/o;
373         s/\.[uis]?32//o and s/\.16b/\.4s/go;
374         m/\.p64/o and s/\.16b/\.1q/o;           # 1st pmull argument
375         m/l\.p64/o and s/\.16b/\.1d/go;         # 2nd and 3rd pmull arguments
376         s/\.[uisp]?64//o and s/\.16b/\.2d/go;
377         s/\.[42]([sd])\[([0-3])\]/\.$1\[$2\]/o;
378
379         print $_,"\n";
380     }
381 } else {                                ######## 32-bit code
382     sub unvdup32 {
383         my $arg=shift;
384
385         $arg =~ m/q([0-9]+),\s*q([0-9]+)\[([0-3])\]/o &&
386         sprintf "vdup.32        q%d,d%d[%d]",$1,2*$2+($3>>1),$3&1;
387     }
388     sub unvpmullp64 {
389         my ($mnemonic,$arg)=@_;
390
391         if ($arg =~ m/q([0-9]+),\s*q([0-9]+),\s*q([0-9]+)/o) {
392             my $word = 0xf2a00e00|(($1&7)<<13)|(($1&8)<<19)
393                                  |(($2&7)<<17)|(($2&8)<<4)
394                                  |(($3&7)<<1) |(($3&8)<<2);
395             $word |= 0x00010001  if ($mnemonic =~ "2");
396             # since ARMv7 instructions are always encoded little-endian.
397             # correct solution is to use .inst directive, but older
398             # assemblers don't implement it:-(
399             sprintf ".byte\t0x%02x,0x%02x,0x%02x,0x%02x\t@ %s %s",
400                         $word&0xff,($word>>8)&0xff,
401                         ($word>>16)&0xff,($word>>24)&0xff,
402                         $mnemonic,$arg;
403         }
404     }
405
406     foreach(split("\n",$code)) {
407         s/\b[wx]([0-9]+)\b/r$1/go;              # new->old registers
408         s/\bv([0-9])\.[12468]+[bsd]\b/q$1/go;   # new->old registers
409         s/\/\/\s?/@ /o;                         # new->old style commentary
410
411         # fix up remainig new-style suffixes
412         s/\],#[0-9]+/]!/o;
413
414         s/cclr\s+([^,]+),\s*([a-z]+)/mov$2      $1,#0/o                 or
415         s/vdup\.32\s+(.*)/unvdup32($1)/geo                              or
416         s/v?(pmull2?)\.p64\s+(.*)/unvpmullp64($1,$2)/geo                or
417         s/\bq([0-9]+)#(lo|hi)/sprintf "d%d",2*$1+($2 eq "hi")/geo       or
418         s/^(\s+)b\./$1b/o                                               or
419         s/^(\s+)ret/$1bx\tlr/o;
420
421         print $_,"\n";
422     }
423 }
424
425 close STDOUT; # enforce flush