crypto/modes/asm/ghashv8-armx.pl

   1 #!/usr/bin/env perl
   2 #
   3 # ====================================================================
   4 # Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
   5 # project. The module is, however, dual licensed under OpenSSL and
   6 # CRYPTOGAMS licenses depending on where you obtain it. For further
   7 # details see http://www.openssl.org/~appro/cryptogams/.
   8 # ====================================================================
   9 #
  10 # GHASH for ARMv8 Crypto Extension, 64-bit polynomial multiplication.
  11 #
  12 # June 2014
  13 #
  14 # Initial version was developed in tight cooperation with Ard
  15 # Biesheuvel <ard.biesheuvel@linaro.org> from bits-n-pieces from
  16 # other assembly modules. Just like aesv8-armx.pl this module
  17 # supports both AArch32 and AArch64 execution modes.
  18 #
  19 # July 2014
  20 #
  21 # Implement 2x aggregated reduction [see ghash-x86.pl for background
  22 # information].
  23 #
  24 # Current performance in cycles per processed byte:
  25 #
  26 #               PMULL[2]        32-bit NEON(*)
  27 # Apple A7      0.92            5.62
  28 # Cortex-A53    1.01            8.39
  29 # Cortex-A57    1.17            7.61
  30 # Denver        0.71            6.02
  31 #
  32 # (*)   presented for reference/comparison purposes;
  33
  34 $flavour = shift;
  35 $output  = shift;
  36
  37 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
  38 ( $xlate="${dir}arm-xlate.pl" and -f $xlate ) or
  39 ( $xlate="${dir}../../perlasm/arm-xlate.pl" and -f $xlate) or
  40 die "can't locate arm-xlate.pl";
  41
  42 open OUT,"| \"$^X\" $xlate $flavour $output";
  43 *STDOUT=*OUT;
  44
  45 $Xi="x0";       # argument block
  46 $Htbl="x1";
  47 $inp="x2";
  48 $len="x3";
  49
  50 $inc="x12";
  51
  52 {
  53 my ($Xl,$Xm,$Xh,$IN)=map("q$_",(0..3));
  54 my ($t0,$t1,$t2,$xC2,$H,$Hhl,$H2)=map("q$_",(8..14));
  55
  56 $code=<<___;
  57 #include "arm_arch.h"
  58
  59 .text
  60 ___
  61 $code.=".arch   armv8-a+crypto\n"       if ($flavour =~ /64/);
  62 $code.=".fpu    neon\n.code     32\n"   if ($flavour !~ /64/);
  63
  64 ################################################################################
  65 # void gcm_init_v8(u128 Htable[16],const u64 H[2]);
  66 #
  67 # input:        128-bit H - secret parameter E(K,0^128)
  68 # output:       precomputed table filled with degrees of twisted H;
  69 #               H is twisted to handle reverse bitness of GHASH;
  70 #               only few of 16 slots of Htable[16] are used;
  71 #               data is opaque to outside world (which allows to
  72 #               optimize the code independently);
  73 #
  74 $code.=<<___;
  75 .global gcm_init_v8
  76 .type   gcm_init_v8,%function
  77 .align  4
  78 gcm_init_v8:
  79         vld1.64         {$t1},[x1]              @ load input H
  80         vmov.i8         $xC2,#0xe1
  81         vshl.i64        $xC2,$xC2,#57           @ 0xc2.0
  82         vext.8          $IN,$t1,$t1,#8
  83         vshr.u64        $t2,$xC2,#63
  84         vdup.32         $t1,${t1}[1]
  85         vext.8          $t0,$t2,$xC2,#8         @ t0=0xc2....01
  86         vshr.u64        $t2,$IN,#63
  87         vshr.s32        $t1,$t1,#31             @ broadcast carry bit
  88         vand            $t2,$t2,$t0
  89         vshl.i64        $IN,$IN,#1
  90         vext.8          $t2,$t2,$t2,#8
  91         vand            $t0,$t0,$t1
  92         vorr            $IN,$IN,$t2             @ H<<<=1
  93         veor            $H,$IN,$t0              @ twisted H
  94         vst1.64         {$H},[x0],#16           @ store Htable[0]
  95
  96         @ calculate H^2
  97         vext.8          $t0,$H,$H,#8            @ Karatsuba pre-processing
  98         vpmull.p64      $Xl,$H,$H
  99         veor            $t0,$t0,$H
 100         vpmull2.p64     $Xh,$H,$H
 101         vpmull.p64      $Xm,$t0,$t0
 102
 103         vext.8          $t1,$Xl,$Xh,#8          @ Karatsuba post-processing
 104         veor            $t2,$Xl,$Xh
 105         veor            $Xm,$Xm,$t1
 106         veor            $Xm,$Xm,$t2
 107         vpmull.p64      $t2,$Xl,$xC2            @ 1st phase
 108
 109         vmov            $Xh#lo,$Xm#hi           @ Xh|Xm - 256-bit result
 110         vmov            $Xm#hi,$Xl#lo           @ Xm is rotated Xl
 111         veor            $Xl,$Xm,$t2
 112
 113         vext.8          $t2,$Xl,$Xl,#8          @ 2nd phase
 114         vpmull.p64      $Xl,$Xl,$xC2
 115         veor            $t2,$t2,$Xh
 116         veor            $H2,$Xl,$t2
 117
 118         vext.8          $t1,$H2,$H2,#8          @ Karatsuba pre-processing
 119         veor            $t1,$t1,$H2
 120         vext.8          $Hhl,$t0,$t1,#8         @ pack Karatsuba pre-processed
 121         vst1.64         {$Hhl-$H2},[x0]         @ store Htable[1..2]
 122
 123         ret
 124 .size   gcm_init_v8,.-gcm_init_v8
 125 ___
 126 ################################################################################
 127 # void gcm_gmult_v8(u64 Xi[2],const u128 Htable[16]);
 128 #
 129 # input:        Xi - current hash value;
 130 #               Htable - table precomputed in gcm_init_v8;
 131 # output:       Xi - next hash value Xi;
 132 #
 133 $code.=<<___;
 134 .global gcm_gmult_v8
 135 .type   gcm_gmult_v8,%function
 136 .align  4
 137 gcm_gmult_v8:
 138         vld1.64         {$t1},[$Xi]             @ load Xi
 139         vmov.i8         $xC2,#0xe1
 140         vld1.64         {$H-$Hhl},[$Htbl]       @ load twisted H, ...
 141         vshl.u64        $xC2,$xC2,#57
 142 #ifndef __ARMEB__
 143         vrev64.8        $t1,$t1
 144 #endif
 145         vext.8          $IN,$t1,$t1,#8
 146
 147         vpmull.p64      $Xl,$H,$IN              @ H.lo·Xi.lo
 148         veor            $t1,$t1,$IN             @ Karatsuba pre-processing
 149         vpmull2.p64     $Xh,$H,$IN              @ H.hi·Xi.hi
 150         vpmull.p64      $Xm,$Hhl,$t1            @ (H.lo+H.hi)·(Xi.lo+Xi.hi)
 151
 152         vext.8          $t1,$Xl,$Xh,#8          @ Karatsuba post-processing
 153         veor            $t2,$Xl,$Xh
 154         veor            $Xm,$Xm,$t1
 155         veor            $Xm,$Xm,$t2
 156         vpmull.p64      $t2,$Xl,$xC2            @ 1st phase of reduction
 157
 158         vmov            $Xh#lo,$Xm#hi           @ Xh|Xm - 256-bit result
 159         vmov            $Xm#hi,$Xl#lo           @ Xm is rotated Xl
 160         veor            $Xl,$Xm,$t2
 161
 162         vext.8          $t2,$Xl,$Xl,#8          @ 2nd phase of reduction
 163         vpmull.p64      $Xl,$Xl,$xC2
 164         veor            $t2,$t2,$Xh
 165         veor            $Xl,$Xl,$t2
 166
 167 #ifndef __ARMEB__
 168         vrev64.8        $Xl,$Xl
 169 #endif
 170         vext.8          $Xl,$Xl,$Xl,#8
 171         vst1.64         {$Xl},[$Xi]             @ write out Xi
 172
 173         ret
 174 .size   gcm_gmult_v8,.-gcm_gmult_v8
 175 ___
 176 ################################################################################
 177 # void gcm_ghash_v8(u64 Xi[2],const u128 Htable[16],const u8 *inp,size_t len);
 178 #
 179 # input:        table precomputed in gcm_init_v8;
 180 #               current hash value Xi;
 181 #               pointer to input data;
 182 #               length of input data in bytes, but divisible by block size;
 183 # output:       next hash value Xi;
 184 #
 185 $code.=<<___;
 186 .global gcm_ghash_v8
 187 .type   gcm_ghash_v8,%function
 188 .align  4
 189 gcm_ghash_v8:
 190 ___
 191 $code.=<<___            if ($flavour !~ /64/);
 192         vstmdb          sp!,{d8-d15}            @ 32-bit ABI says so
 193 ___
 194 $code.=<<___;
 195         vld1.64         {$Xl},[$Xi]             @ load [rotated] Xi
 196                                                 @ "[rotated]" means that
 197                                                 @ loaded value would have
 198                                                 @ to be rotated in order to
 199                                                 @ make it appear as in
 200                                                 @ alorithm specification
 201         subs            $len,$len,#32           @ see if $len is 32 or larger
 202         mov             $inc,#16                @ $inc is used as post-
 203                                                 @ increment for input pointer;
 204                                                 @ as loop is modulo-scheduled
 205                                                 @ $inc is zeroed just in time
 206                                                 @ to preclude oversteping
 207                                                 @ inp[len], which means that
 208                                                 @ last block[s] are actually
 209                                                 @ loaded twice, but last
 210                                                 @ copy is not processed
 211         vld1.64         {$H-$Hhl},[$Htbl],#32   @ load twisted H, ..., H^2
 212         vmov.i8         $xC2,#0xe1
 213         vld1.64         {$H2},[$Htbl]
 214         cclr            $inc,eq                 @ is it time to zero $inc?
 215         vext.8          $Xl,$Xl,$Xl,#8          @ rotate Xi
 216         vld1.64         {$t0},[$inp],#16        @ load [rotated] I[0]
 217         vshl.u64        $xC2,$xC2,#57           @ compose 0xc2.0 constant
 218 #ifndef __ARMEB__
 219         vrev64.8        $t0,$t0
 220         vrev64.8        $Xl,$Xl
 221 #endif
 222         vext.8          $IN,$t0,$t0,#8          @ rotate I[0]
 223         b.lo            .Lodd_tail_v8           @ $len was less than 32
 224 ___
 225 { my ($Xln,$Xmn,$Xhn,$In) = map("q$_",(4..7));
 226         #######
 227         # Xi+2 =[H*(Ii+1 + Xi+1)] mod P =
 228         #       [(H*Ii+1) + (H*Xi+1)] mod P =
 229         #       [(H*Ii+1) + H^2*(Ii+Xi)] mod P
 230         #
 231 $code.=<<___;
 232         vld1.64         {$t1},[$inp],$inc       @ load [rotated] I[1]
 233 #ifndef __ARMEB__
 234         vrev64.8        $t1,$t1
 235 #endif
 236         vext.8          $In,$t1,$t1,#8
 237         veor            $IN,$IN,$Xl             @ I[i]^=Xi
 238         vpmull.p64      $Xln,$H,$In             @ H·Ii+1
 239         veor            $t1,$t1,$In             @ Karatsuba pre-processing
 240         vpmull2.p64     $Xhn,$H,$In
 241         b               .Loop_mod2x_v8
 242
 243 .align  4
 244 .Loop_mod2x_v8:
 245         vext.8          $t2,$IN,$IN,#8
 246         subs            $len,$len,#32           @ is there more data?
 247         vpmull.p64      $Xl,$H2,$IN             @ H^2.lo·Xi.lo
 248         cclr            $inc,lo                 @ is it time to zero $inc?
 249
 250          vpmull.p64     $Xmn,$Hhl,$t1
 251         veor            $t2,$t2,$IN             @ Karatsuba pre-processing
 252         vpmull2.p64     $Xh,$H2,$IN             @ H^2.hi·Xi.hi
 253         veor            $Xl,$Xl,$Xln            @ accumulate
 254         vpmull2.p64     $Xm,$Hhl,$t2            @ (H^2.lo+H^2.hi)·(Xi.lo+Xi.hi)
 255          vld1.64        {$t0},[$inp],$inc       @ load [rotated] I[i+2]
 256
 257         veor            $Xh,$Xh,$Xhn
 258          cclr           $inc,eq                 @ is it time to zero $inc?
 259         veor            $Xm,$Xm,$Xmn
 260
 261         vext.8          $t1,$Xl,$Xh,#8          @ Karatsuba post-processing
 262         veor            $t2,$Xl,$Xh
 263         veor            $Xm,$Xm,$t1
 264          vld1.64        {$t1},[$inp],$inc       @ load [rotated] I[i+3]
 265 #ifndef __ARMEB__
 266          vrev64.8       $t0,$t0
 267 #endif
 268         veor            $Xm,$Xm,$t2
 269         vpmull.p64      $t2,$Xl,$xC2            @ 1st phase of reduction
 270
 271 #ifndef __ARMEB__
 272          vrev64.8       $t1,$t1
 273 #endif
 274         vmov            $Xh#lo,$Xm#hi           @ Xh|Xm - 256-bit result
 275         vmov            $Xm#hi,$Xl#lo           @ Xm is rotated Xl
 276          vext.8         $In,$t1,$t1,#8
 277          vext.8         $IN,$t0,$t0,#8
 278         veor            $Xl,$Xm,$t2
 279          vpmull.p64     $Xln,$H,$In             @ H·Ii+1
 280         veor            $IN,$IN,$Xh             @ accumulate $IN early
 281
 282         vext.8          $t2,$Xl,$Xl,#8          @ 2nd phase of reduction
 283         vpmull.p64      $Xl,$Xl,$xC2
 284         veor            $IN,$IN,$t2
 285          veor           $t1,$t1,$In             @ Karatsuba pre-processing
 286         veor            $IN,$IN,$Xl
 287          vpmull2.p64    $Xhn,$H,$In
 288         b.hs            .Loop_mod2x_v8          @ there was at least 32 more bytes
 289
 290         veor            $Xh,$Xh,$t2
 291         vext.8          $IN,$t0,$t0,#8          @ re-construct $IN
 292         adds            $len,$len,#32           @ re-construct $len
 293         veor            $Xl,$Xl,$Xh             @ re-construct $Xl
 294         b.eq            .Ldone_v8               @ is $len zero?
 295 ___
 296 }
 297 $code.=<<___;
 298 .Lodd_tail_v8:
 299         vext.8          $t2,$Xl,$Xl,#8
 300         veor            $IN,$IN,$Xl             @ inp^=Xi
 301         veor            $t1,$t0,$t2             @ $t1 is rotated inp^Xi
 302
 303         vpmull.p64      $Xl,$H,$IN              @ H.lo·Xi.lo
 304         veor            $t1,$t1,$IN             @ Karatsuba pre-processing
 305         vpmull2.p64     $Xh,$H,$IN              @ H.hi·Xi.hi
 306         vpmull.p64      $Xm,$Hhl,$t1            @ (H.lo+H.hi)·(Xi.lo+Xi.hi)
 307
 308         vext.8          $t1,$Xl,$Xh,#8          @ Karatsuba post-processing
 309         veor            $t2,$Xl,$Xh
 310         veor            $Xm,$Xm,$t1
 311         veor            $Xm,$Xm,$t2
 312         vpmull.p64      $t2,$Xl,$xC2            @ 1st phase of reduction
 313
 314         vmov            $Xh#lo,$Xm#hi           @ Xh|Xm - 256-bit result
 315         vmov            $Xm#hi,$Xl#lo           @ Xm is rotated Xl
 316         veor            $Xl,$Xm,$t2
 317
 318         vext.8          $t2,$Xl,$Xl,#8          @ 2nd phase of reduction
 319         vpmull.p64      $Xl,$Xl,$xC2
 320         veor            $t2,$t2,$Xh
 321         veor            $Xl,$Xl,$t2
 322
 323 .Ldone_v8:
 324 #ifndef __ARMEB__
 325         vrev64.8        $Xl,$Xl
 326 #endif
 327         vext.8          $Xl,$Xl,$Xl,#8
 328         vst1.64         {$Xl},[$Xi]             @ write out Xi
 329
 330 ___
 331 $code.=<<___            if ($flavour !~ /64/);
 332         vldmia          sp!,{d8-d15}            @ 32-bit ABI says so
 333 ___
 334 $code.=<<___;
 335         ret
 336 .size   gcm_ghash_v8,.-gcm_ghash_v8
 337 ___
 338 }
 339 $code.=<<___;
 340 .asciz  "GHASH for ARMv8, CRYPTOGAMS by <appro\@openssl.org>"
 341 .align  2
 342 ___
 343
 344 if ($flavour =~ /64/) {                 ######## 64-bit code
 345     sub unvmov {
 346         my $arg=shift;
 347
 348         $arg =~ m/q([0-9]+)#(lo|hi),\s*q([0-9]+)#(lo|hi)/o &&
 349         sprintf "ins    v%d.d[%d],v%d.d[%d]",$1,($2 eq "lo")?0:1,$3,($4 eq "lo")?0:1;
 350     }
 351     foreach(split("\n",$code)) {
 352         s/cclr\s+([wx])([^,]+),\s*([a-z]+)/csel $1$2,$1zr,$1$2,$3/o     or
 353         s/vmov\.i8/movi/o               or      # fix up legacy mnemonics
 354         s/vmov\s+(.*)/unvmov($1)/geo    or
 355         s/vext\.8/ext/o                 or
 356         s/vshr\.s/sshr\.s/o             or
 357         s/vshr/ushr/o                   or
 358         s/^(\s+)v/$1/o                  or      # strip off v prefix
 359         s/\bbx\s+lr\b/ret/o;
 360
 361         s/\bq([0-9]+)\b/"v".($1<8?$1:$1+8).".16b"/geo;  # old->new registers
 362         s/@\s/\/\//o;                           # old->new style commentary
 363
 364         # fix up remainig legacy suffixes
 365         s/\.[ui]?8(\s)/$1/o;
 366         s/\.[uis]?32//o and s/\.16b/\.4s/go;
 367         m/\.p64/o and s/\.16b/\.1q/o;           # 1st pmull argument
 368         m/l\.p64/o and s/\.16b/\.1d/go;         # 2nd and 3rd pmull arguments
 369         s/\.[uisp]?64//o and s/\.16b/\.2d/go;
 370         s/\.[42]([sd])\[([0-3])\]/\.$1\[$2\]/o;
 371
 372         print $_,"\n";
 373     }
 374 } else {                                ######## 32-bit code
 375     sub unvdup32 {
 376         my $arg=shift;
 377
 378         $arg =~ m/q([0-9]+),\s*q([0-9]+)\[([0-3])\]/o &&
 379         sprintf "vdup.32        q%d,d%d[%d]",$1,2*$2+($3>>1),$3&1;
 380     }
 381     sub unvpmullp64 {
 382         my ($mnemonic,$arg)=@_;
 383
 384         if ($arg =~ m/q([0-9]+),\s*q([0-9]+),\s*q([0-9]+)/o) {
 385             my $word = 0xf2a00e00|(($1&7)<<13)|(($1&8)<<19)
 386                                  |(($2&7)<<17)|(($2&8)<<4)
 387                                  |(($3&7)<<1) |(($3&8)<<2);
 388             $word |= 0x00010001  if ($mnemonic =~ "2");
 389             # since ARMv7 instructions are always encoded little-endian.
 390             # correct solution is to use .inst directive, but older
 391             # assemblers don't implement it:-(
 392             sprintf ".byte\t0x%02x,0x%02x,0x%02x,0x%02x\t@ %s %s",
 393                         $word&0xff,($word>>8)&0xff,
 394                         ($word>>16)&0xff,($word>>24)&0xff,
 395                         $mnemonic,$arg;
 396         }
 397     }
 398
 399     foreach(split("\n",$code)) {
 400         s/\b[wx]([0-9]+)\b/r$1/go;              # new->old registers
 401         s/\bv([0-9])\.[12468]+[bsd]\b/q$1/go;   # new->old registers
 402         s/\/\/\s?/@ /o;                         # new->old style commentary
 403
 404         # fix up remainig new-style suffixes
 405         s/\],#[0-9]+/]!/o;
 406
 407         s/cclr\s+([^,]+),\s*([a-z]+)/mov$2      $1,#0/o                 or
 408         s/vdup\.32\s+(.*)/unvdup32($1)/geo                              or
 409         s/v?(pmull2?)\.p64\s+(.*)/unvpmullp64($1,$2)/geo                or
 410         s/\bq([0-9]+)#(lo|hi)/sprintf "d%d",2*$1+($2 eq "hi")/geo       or
 411         s/^(\s+)b\./$1b/o                                               or
 412         s/^(\s+)ret/$1bx\tlr/o;
 413
 414         print $_,"\n";
 415     }
 416 }
 417
 418 close STDOUT; # enforce flush