2 # Copyright 2010-2018 The OpenSSL Project Authors. All Rights Reserved.
4 # Licensed under the Apache License 2.0 (the "License"). You may not use
5 # this file except in compliance with the License. You can obtain a copy
6 # in the file LICENSE in the source distribution or at
7 # https://www.openssl.org/source/license.html
10 # ====================================================================
11 # Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
12 # project. The module is, however, dual licensed under OpenSSL and
13 # CRYPTOGAMS licenses depending on where you obtain it. For further
14 # details see http://www.openssl.org/~appro/cryptogams/.
15 # ====================================================================
19 # The module implements "4-bit" GCM GHASH function and underlying
20 # single multiplication operation in GF(2^128). "4-bit" means that it
21 # uses 256 bytes per-key table [+32 bytes shared table]. There is no
22 # experimental performance data available yet. The only approximation
23 # that can be made at this point is based on code size. Inner loop is
24 # 32 instructions long and on single-issue core should execute in <40
25 # cycles. Having verified that gcc 3.4 didn't unroll corresponding
26 # loop, this assembler loop body was found to be ~3x smaller than
27 # compiler-generated one...
31 # Rescheduling for dual-issue pipeline resulted in 8.5% improvement on
32 # Cortex A8 core and ~25 cycles per processed byte (which was observed
33 # to be ~3 times faster than gcc-generated code:-)
37 # Profiler-assisted and platform-specific optimization resulted in 7%
38 # improvement on Cortex A8 core and ~23.5 cycles per byte.
42 # Add NEON implementation featuring polynomial multiplication, i.e. no
43 # lookup tables involved. On Cortex A8 it was measured to process one
44 # byte in 15 cycles or 55% faster than integer-only code.
48 # Switch to multiplication algorithm suggested in paper referred
49 # below and combine it with reduction algorithm from x86 module.
50 # Performance improvement over previous version varies from 65% on
51 # Snapdragon S4 to 110% on Cortex A9. In absolute terms Cortex A8
52 # processes one byte in 8.45 cycles, A9 - in 10.2, A15 - in 7.63,
53 # Snapdragon S4 - in 9.33.
55 # Câmara, D.; Gouvêa, C. P. L.; López, J. & Dahab, R.: Fast Software
56 # Polynomial Multiplication on ARM Processors using the NEON Engine.
58 # http://conradoplg.cryptoland.net/files/2010/12/mocrysen13.pdf
60 # ====================================================================
61 # Note about "528B" variant. In ARM case it makes lesser sense to
62 # implement it for following reasons:
64 # - performance improvement won't be anywhere near 50%, because 128-
65 # bit shift operation is neatly fused with 128-bit xor here, and
66 # "538B" variant would eliminate only 4-5 instructions out of 32
67 # in the inner loop (meaning that estimated improvement is ~15%);
68 # - ARM-based systems are often embedded ones and extra memory
69 # consumption might be unappreciated (for so little improvement);
71 # Byte order [in]dependence. =========================================
73 # Caller is expected to maintain specific *dword* order in Htable,
74 # namely with *least* significant dword of 128-bit value at *lower*
75 # address. This differs completely from C code and has everything to
76 # do with ldm instruction and order in which dwords are "consumed" by
77 # algorithm. *Byte* order within these dwords in turn is whatever
78 # *native* byte order on current platform. See gcm128.c for working
82 if ($flavour=~/\w[\w\-]*\.\w+$/) { $output=$flavour; undef $flavour; }
83 else { while (($output=shift) && ($output!~/\w[\w\-]*\.\w+$/)) {} }
85 if ($flavour && $flavour ne "void") {
86 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
87 ( $xlate="${dir}arm-xlate.pl" and -f $xlate ) or
88 ( $xlate="${dir}../../perlasm/arm-xlate.pl" and -f $xlate) or
89 die "can't locate arm-xlate.pl";
91 open STDOUT,"| \"$^X\" $xlate $flavour $output";
93 open STDOUT,">$output";
96 $Xi="r0"; # argument block
101 $Zll="r4"; # variables
110 ################# r13 is stack pointer
112 ################# r15 is program counter
114 $rem_4bit=$inp; # used in gcm_gmult_4bit
120 for ($Zll,$Zlh,$Zhl,$Zhh) {
122 #if __ARM_ARCH__>=7 && defined(__ARMEL__)
125 #elif defined(__ARMEB__)
131 strb $Tlh,[$Xi,#$i+2]
133 strb $Thl,[$Xi,#$i+1]
137 $code.="\t".shift(@args)."\n";
143 #include "arm_arch.h"
145 #if defined(__thumb2__) || defined(__clang__)
147 #define ldrplb ldrbpl
148 #define ldrneb ldrbne
150 #if defined(__thumb2__)
158 .type rem_4bit,%object
161 .short 0x0000,0x1C20,0x3840,0x2460
162 .short 0x7080,0x6CA0,0x48C0,0x54E0
163 .short 0xE100,0xFD20,0xD940,0xC560
164 .short 0x9180,0x8DA0,0xA9C0,0xB5E0
165 .size rem_4bit,.-rem_4bit
167 .type rem_4bit_get,%function
169 #if defined(__thumb2__)
170 adr $rem_4bit,rem_4bit
172 sub $rem_4bit,pc,#8+32 @ &rem_4bit
177 .size rem_4bit_get,.-rem_4bit_get
179 .global gcm_ghash_4bit
180 .type gcm_ghash_4bit,%function
183 #if defined(__thumb2__)
186 sub r12,pc,#8+48 @ &rem_4bit
188 add $len,$inp,$len @ $len to point at the end
189 stmdb sp!,{r3-r11,lr} @ save $len/end too
191 ldmia r12,{r4-r11} @ copy rem_4bit ...
192 stmdb sp!,{r4-r11} @ ... to stack
202 add $Zhh,$Htbl,$nlo,lsl#4
203 ldmia $Zhh,{$Zll-$Zhh} @ load Htbl[nlo]
207 and $nhi,$Zll,#0xf @ rem
208 ldmia $Thh,{$Tll-$Thh} @ load Htbl[nhi]
210 eor $Zll,$Tll,$Zll,lsr#4
211 ldrh $Tll,[sp,$nhi] @ rem_4bit[rem]
212 eor $Zll,$Zll,$Zlh,lsl#28
214 eor $Zlh,$Tlh,$Zlh,lsr#4
215 eor $Zlh,$Zlh,$Zhl,lsl#28
216 eor $Zhl,$Thl,$Zhl,lsr#4
217 eor $Zhl,$Zhl,$Zhh,lsl#28
218 eor $Zhh,$Thh,$Zhh,lsr#4
222 eor $Zhh,$Zhh,$Tll,lsl#16
225 add $Thh,$Htbl,$nlo,lsl#4
226 and $nlo,$Zll,#0xf @ rem
229 ldmia $Thh,{$Tll-$Thh} @ load Htbl[nlo]
230 eor $Zll,$Tll,$Zll,lsr#4
231 eor $Zll,$Zll,$Zlh,lsl#28
232 eor $Zlh,$Tlh,$Zlh,lsr#4
233 eor $Zlh,$Zlh,$Zhl,lsl#28
234 ldrh $Tll,[sp,$nlo] @ rem_4bit[rem]
235 eor $Zhl,$Thl,$Zhl,lsr#4
239 ldrplb $nlo,[$inp,$cnt]
240 eor $Zhl,$Zhl,$Zhh,lsl#28
241 eor $Zhh,$Thh,$Zhh,lsr#4
244 and $nhi,$Zll,#0xf @ rem
245 eor $Zhh,$Zhh,$Tll,lsl#16 @ ^= rem_4bit[rem]
247 ldmia $Thh,{$Tll-$Thh} @ load Htbl[nhi]
248 eor $Zll,$Tll,$Zll,lsr#4
252 ldrplb $Tll,[$Xi,$cnt]
253 eor $Zll,$Zll,$Zlh,lsl#28
254 eor $Zlh,$Tlh,$Zlh,lsr#4
256 eor $Zlh,$Zlh,$Zhl,lsl#28
257 eor $Zhl,$Thl,$Zhl,lsr#4
258 eor $Zhl,$Zhl,$Zhh,lsl#28
263 eor $Zhh,$Thh,$Zhh,lsr#4
267 andpl $nhi,$nlo,#0xf0
268 andpl $nlo,$nlo,#0x0f
269 eor $Zhh,$Zhh,$Tlh,lsl#16 @ ^= rem_4bit[rem]
272 ldr $len,[sp,#32] @ re-load $len/end
276 &Zsmash("cmp\t$inp,$len","\n".
277 "#ifdef __thumb2__\n".
280 " ldrneb $nlo,[$inp,#15]");
286 ldmia sp!,{r4-r11,pc}
288 ldmia sp!,{r4-r11,lr}
290 moveq pc,lr @ be binary compatible with V4, yet
291 bx lr @ interoperable with Thumb ISA:-)
293 .size gcm_ghash_4bit,.-gcm_ghash_4bit
295 .global gcm_gmult_4bit
296 .type gcm_gmult_4bit,%function
298 stmdb sp!,{r4-r11,lr}
306 add $Zhh,$Htbl,$nlo,lsl#4
307 ldmia $Zhh,{$Zll-$Zhh} @ load Htbl[nlo]
311 and $nhi,$Zll,#0xf @ rem
312 ldmia $Thh,{$Tll-$Thh} @ load Htbl[nhi]
314 eor $Zll,$Tll,$Zll,lsr#4
315 ldrh $Tll,[$rem_4bit,$nhi] @ rem_4bit[rem]
316 eor $Zll,$Zll,$Zlh,lsl#28
317 eor $Zlh,$Tlh,$Zlh,lsr#4
318 eor $Zlh,$Zlh,$Zhl,lsl#28
319 eor $Zhl,$Thl,$Zhl,lsr#4
320 eor $Zhl,$Zhl,$Zhh,lsl#28
321 eor $Zhh,$Thh,$Zhh,lsr#4
323 eor $Zhh,$Zhh,$Tll,lsl#16
327 add $Thh,$Htbl,$nlo,lsl#4
328 and $nlo,$Zll,#0xf @ rem
331 ldmia $Thh,{$Tll-$Thh} @ load Htbl[nlo]
332 eor $Zll,$Tll,$Zll,lsr#4
333 eor $Zll,$Zll,$Zlh,lsl#28
334 eor $Zlh,$Tlh,$Zlh,lsr#4
335 eor $Zlh,$Zlh,$Zhl,lsl#28
336 ldrh $Tll,[$rem_4bit,$nlo] @ rem_4bit[rem]
337 eor $Zhl,$Thl,$Zhl,lsr#4
341 ldrplb $nlo,[$Xi,$cnt]
342 eor $Zhl,$Zhl,$Zhh,lsl#28
343 eor $Zhh,$Thh,$Zhh,lsr#4
346 and $nhi,$Zll,#0xf @ rem
347 eor $Zhh,$Zhh,$Tll,lsl#16 @ ^= rem_4bit[rem]
349 ldmia $Thh,{$Tll-$Thh} @ load Htbl[nhi]
350 eor $Zll,$Tll,$Zll,lsr#4
351 eor $Zll,$Zll,$Zlh,lsl#28
352 eor $Zlh,$Tlh,$Zlh,lsr#4
353 ldrh $Tll,[$rem_4bit,$nhi] @ rem_4bit[rem]
354 eor $Zlh,$Zlh,$Zhl,lsl#28
355 eor $Zhl,$Thl,$Zhl,lsr#4
356 eor $Zhl,$Zhl,$Zhh,lsl#28
357 eor $Zhh,$Thh,$Zhh,lsr#4
361 andpl $nhi,$nlo,#0xf0
362 andpl $nlo,$nlo,#0x0f
363 eor $Zhh,$Zhh,$Tll,lsl#16 @ ^= rem_4bit[rem]
369 ldmia sp!,{r4-r11,pc}
371 ldmia sp!,{r4-r11,lr}
373 moveq pc,lr @ be binary compatible with V4, yet
374 bx lr @ interoperable with Thumb ISA:-)
376 .size gcm_gmult_4bit,.-gcm_gmult_4bit
379 my ($Xl,$Xm,$Xh,$IN)=map("q$_",(0..3));
380 my ($t0,$t1,$t2,$t3)=map("q$_",(8..12));
381 my ($Hlo,$Hhi,$Hhl,$k48,$k32,$k16)=map("d$_",(26..31));
386 vext.8 $t0#lo, $a, $a, #1 @ A1
387 vmull.p8 $t0, $t0#lo, $b @ F = A1*B
388 vext.8 $r#lo, $b, $b, #1 @ B1
389 vmull.p8 $r, $a, $r#lo @ E = A*B1
390 vext.8 $t1#lo, $a, $a, #2 @ A2
391 vmull.p8 $t1, $t1#lo, $b @ H = A2*B
392 vext.8 $t3#lo, $b, $b, #2 @ B2
393 vmull.p8 $t3, $a, $t3#lo @ G = A*B2
394 vext.8 $t2#lo, $a, $a, #3 @ A3
395 veor $t0, $t0, $r @ L = E + F
396 vmull.p8 $t2, $t2#lo, $b @ J = A3*B
397 vext.8 $r#lo, $b, $b, #3 @ B3
398 veor $t1, $t1, $t3 @ M = G + H
399 vmull.p8 $r, $a, $r#lo @ I = A*B3
400 veor $t0#lo, $t0#lo, $t0#hi @ t0 = (L) (P0 + P1) << 8
401 vand $t0#hi, $t0#hi, $k48
402 vext.8 $t3#lo, $b, $b, #4 @ B4
403 veor $t1#lo, $t1#lo, $t1#hi @ t1 = (M) (P2 + P3) << 16
404 vand $t1#hi, $t1#hi, $k32
405 vmull.p8 $t3, $a, $t3#lo @ K = A*B4
406 veor $t2, $t2, $r @ N = I + J
407 veor $t0#lo, $t0#lo, $t0#hi
408 veor $t1#lo, $t1#lo, $t1#hi
409 veor $t2#lo, $t2#lo, $t2#hi @ t2 = (N) (P4 + P5) << 24
410 vand $t2#hi, $t2#hi, $k16
411 vext.8 $t0, $t0, $t0, #15
412 veor $t3#lo, $t3#lo, $t3#hi @ t3 = (K) (P6 + P7) << 32
414 vext.8 $t1, $t1, $t1, #14
415 veor $t2#lo, $t2#lo, $t2#hi
416 vmull.p8 $r, $a, $b @ D = A*B
417 vext.8 $t3, $t3, $t3, #12
418 vext.8 $t2, $t2, $t2, #13
427 #if __ARM_MAX_ARCH__>=7
431 .global gcm_init_neon
432 .type gcm_init_neon,%function
435 vld1.64 $IN#hi,[r1]! @ load H
439 vshr.u64 $t0#lo,#63 @ t0=0xc2....01
441 vshr.u64 $Hlo,$IN#lo,#63
442 vshr.s8 $t1,#7 @ broadcast carry bit
445 vorr $IN#hi,$Hlo @ H<<<=1
446 veor $IN,$IN,$t0 @ twisted H
450 .size gcm_init_neon,.-gcm_init_neon
452 .global gcm_gmult_neon
453 .type gcm_gmult_neon,%function
456 vld1.64 $IN#hi,[$Xi]! @ load Xi
457 vld1.64 $IN#lo,[$Xi]!
458 vmov.i64 $k48,#0x0000ffffffffffff
459 vldmia $Htbl,{$Hlo-$Hhi} @ load twisted H
460 vmov.i64 $k32,#0x00000000ffffffff
464 vmov.i64 $k16,#0x000000000000ffff
465 veor $Hhl,$Hlo,$Hhi @ Karatsuba pre-processing
468 .size gcm_gmult_neon,.-gcm_gmult_neon
470 .global gcm_ghash_neon
471 .type gcm_ghash_neon,%function
474 vld1.64 $Xl#hi,[$Xi]! @ load Xi
475 vld1.64 $Xl#lo,[$Xi]!
476 vmov.i64 $k48,#0x0000ffffffffffff
477 vldmia $Htbl,{$Hlo-$Hhi} @ load twisted H
478 vmov.i64 $k32,#0x00000000ffffffff
482 vmov.i64 $k16,#0x000000000000ffff
483 veor $Hhl,$Hlo,$Hhi @ Karatsuba pre-processing
486 vld1.64 $IN#hi,[$inp]! @ load inp
487 vld1.64 $IN#lo,[$inp]!
491 veor $IN,$Xl @ inp^=Xi
494 &clmul64x64 ($Xl,$Hlo,"$IN#lo"); # H.lo·Xi.lo
496 veor $IN#lo,$IN#lo,$IN#hi @ Karatsuba pre-processing
498 &clmul64x64 ($Xm,$Hhl,"$IN#lo"); # (H.lo+H.hi)·(Xi.lo+Xi.hi)
499 &clmul64x64 ($Xh,$Hhi,"$IN#hi"); # H.hi·Xi.hi
501 veor $Xm,$Xm,$Xl @ Karatsuba post-processing
503 veor $Xl#hi,$Xl#hi,$Xm#lo
504 veor $Xh#lo,$Xh#lo,$Xm#hi @ Xh|Xl - 256-bit result
506 @ equivalent of reduction_avx from ghash-x86_64.pl
507 vshl.i64 $t1,$Xl,#57 @ 1st phase
512 veor $Xl#hi,$Xl#hi,$t2#lo @
513 veor $Xh#lo,$Xh#lo,$t2#hi
515 vshr.u64 $t2,$Xl,#1 @ 2nd phase
519 vshr.u64 $Xl,$Xl,#1 @
530 vst1.64 $Xl#hi,[$Xi]! @ write out Xi
534 .size gcm_ghash_neon,.-gcm_ghash_neon
539 .asciz "GHASH for ARMv4/NEON, CRYPTOGAMS by <appro\@openssl.org>"
543 foreach (split("\n",$code)) {
544 s/\`([^\`]*)\`/eval $1/geo;
546 s/\bq([0-9]+)#(lo|hi)/sprintf "d%d",2*$1+($2 eq "hi")/geo or
547 s/\bret\b/bx lr/go or
548 s/\bbx\s+lr\b/.word\t0xe12fff1e/go; # make it possible to compile with -march=armv4
552 close STDOUT; # enforce flush