crypto/bn/asm/ia64.S

   1 .text
   2 .asciz  "ia64.S, Version 1.0"
   3 .asciz  "IA-64 ISA artwork by Andy Polyakov <appro@fy.chalmers.se>"
   4
   5 //
   6 // ====================================================================
   7 // Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
   8 // project.
   9 //
  10 // Rights for redistribution and usage in source and binary forms are
  11 // granted according to the OpenSSL license. Warranty of any kind is
  12 // disclaimed.
  13 // ====================================================================
  14 //
  15
  16 // Q.   How much faster does it get?
  17 // A.   Here is the output from 'openssl speed rsa dsa' for vanilla
  18 //      0.9.6a compiled with gcc version 2.96 20000731 (Red Hat
  19 //      Linux 7.1 2.96-81):
  20 //
  21 //                        sign    verify    sign/s verify/s
  22 //      rsa  512 bits   0.0036s   0.0003s    275.3   2999.2
  23 //      rsa 1024 bits   0.0203s   0.0011s     49.3    894.1
  24 //      rsa 2048 bits   0.1331s   0.0040s      7.5    250.9
  25 //      rsa 4096 bits   0.9270s   0.0147s      1.1     68.1
  26 //                        sign    verify    sign/s verify/s
  27 //      dsa  512 bits   0.0035s   0.0043s    288.3    234.8
  28 //      dsa 1024 bits   0.0111s   0.0135s     90.0     74.2
  29 //
  30 //      And here is similar output but for this assembler
  31 //      implementation:-)
  32 //
  33 //                        sign    verify    sign/s verify/s
  34 //      rsa  512 bits   0.0021s   0.0001s    549.4   9638.5
  35 //      rsa 1024 bits   0.0055s   0.0002s    183.8   4481.1
  36 //      rsa 2048 bits   0.0244s   0.0006s     41.4   1726.3
  37 //      rsa 4096 bits   0.1295s   0.0018s      7.7    561.5
  38 //                        sign    verify    sign/s verify/s
  39 //      dsa  512 bits   0.0012s   0.0013s    891.9    756.6
  40 //      dsa 1024 bits   0.0023s   0.0028s    440.4    376.2
  41 //
  42 //      Yes, you may argue that it's not fair comparison as it's
  43 //      possible to craft the C implementation with BN_UMULT_HIGH
  44 //      inline assembler macro. But of course! Here is the output
  45 //      with the macro:
  46 //
  47 //                        sign    verify    sign/s verify/s
  48 //      rsa  512 bits   0.0020s   0.0002s    495.0   6561.0
  49 //      rsa 1024 bits   0.0086s   0.0004s    116.2   2235.7
  50 //      rsa 2048 bits   0.0519s   0.0015s     19.3    667.3
  51 //      rsa 4096 bits   0.3464s   0.0053s      2.9    187.7
  52 //                        sign    verify    sign/s verify/s
  53 //      dsa  512 bits   0.0016s   0.0020s    613.1    510.5
  54 //      dsa 1024 bits   0.0045s   0.0054s    221.0    183.9
  55 //
  56 //      My code is still way faster, huh:-) And I believe that even
  57 //      higher performance can be achieved. Note that as keys get
  58 //      longer, performance gain is larger. Why? According to the
  59 //      profiler there is another player in the field, namely
  60 //      BN_from_montgomery consuming larger and larger portion of CPU
  61 //      time as keysize decreases. I therefore consider putting effort
  62 //      to assembler implementation of the following routine:
  63 //
  64 //      void bn_mul_add_mont (BN_ULONG *rp,BN_ULONG *np,int nl,BN_ULONG n0)
  65 //      {
  66 //      int      i,j;
  67 //      BN_ULONG v;
  68 //
  69 //      for (i=0; i<nl; i++)
  70 //              {
  71 //              v=bn_mul_add_words(rp,np,nl,(rp[0]*n0)&BN_MASK2);
  72 //              nrp++;
  73 //              rp++;
  74 //              if (((nrp[-1]+=v)&BN_MASK2) < v)
  75 //                      for (j=0; ((++nrp[j])&BN_MASK2) == 0; j++) ;
  76 //              }
  77 //      }
  78 //
  79 //      It might as well be beneficial to implement even combaX
  80 //      variants, as it appears as it can literally unleash the
  81 //      performance (see comment section to bn_mul_comba8 below).
  82 //
  83 //      And finally for your reference the output for 0.9.6a compiled
  84 //      with SGIcc version 0.01.0-12 (keep in mind that for the moment
  85 //      of this writing it's not possible to convince SGIcc to use
  86 //      BN_UMULT_HIGH inline assembler macro, yet the code is fast,
  87 //      i.e. for a compiler generated one:-):
  88 //
  89 //                        sign    verify    sign/s verify/s
  90 //      rsa  512 bits   0.0022s   0.0002s    452.7   5894.3
  91 //      rsa 1024 bits   0.0097s   0.0005s    102.7   2002.9
  92 //      rsa 2048 bits   0.0578s   0.0017s     17.3    600.2
  93 //      rsa 4096 bits   0.3838s   0.0061s      2.6    164.5
  94 //                        sign    verify    sign/s verify/s
  95 //      dsa  512 bits   0.0018s   0.0022s    547.3    459.6
  96 //      dsa 1024 bits   0.0051s   0.0062s    196.6    161.3
  97 //
  98 //      Oh! Benchmarks were performed on 733MHz Lion-class Itanium
  99 //      system running Redhat Linux 7.1 (very special thanks to Ray
 100 //      McCaffity of Williams Communications for providing an account).
 101 //
 102 // Q.   What's the heck with 'rum 1<<5' at the end of every function?
 103 // A.   Well, by clearing the "upper FP registers written" bit of the
 104 //      User Mask I want to excuse the kernel from preserving upper
 105 //      (f32-f128) FP register bank over process context switch, thus
 106 //      minimizing bus bandwidth consumption during the switch (i.e.
 107 //      after PKI opration completes and the program is off doing
 108 //      something else like bulk symmetric encryption). Having said
 109 //      this, I also want to point out that it might be good idea
 110 //      to compile the whole toolkit (as well as majority of the
 111 //      programs for that matter) with -mfixed-range=f32-f127 command
 112 //      line option. No, it doesn't prevent the compiler from writing
 113 //      to upper bank, but at least discourages to do so. If you don't
 114 //      like the idea you have the option to compile the module with
 115 //      -Drum=nop.m in command line.
 116 //
 117
 118 #if 1
 119 //
 120 // bn_[add|sub]_words routines.
 121 //
 122 // Loops are spinning in 2*(n+5) ticks on Itanuim (provided that the
 123 // data reside in L1 cache, i.e. 2 ticks away). It's possible to
 124 // compress the epilogue and get down to 2*n+6, but at the cost of
 125 // scalability (the neat feature of this implementation is that it
 126 // shall automagically spin in n+5 on "wider" IA-64 implementations:-)
 127 // I consider that the epilogue is short enough as it is to trade tiny
 128 // performance loss on Itanium for scalability.
 129 //
 130 // BN_ULONG bn_add_words(BN_ULONG *rp, BN_ULONG *ap, BN_ULONG *bp,int num)
 131 //
 132 .global bn_add_words#
 133 .proc   bn_add_words#
 134 .align  64
 135 .space  32      // makes the loop body aligned at 64-byte boundary
 136 bn_add_words:
 137         .prologue
 138         .fframe 0
 139         .save   ar.pfs,r2
 140 { .mii  alloc           r2=ar.pfs,4,12,0,16
 141         cmp4.le         p6,p0=r35,r0    };;
 142 { .mfb  mov             r8=r0                   // return value
 143 (p6)    br.ret.spnt.many        b0      };;
 144
 145         .save   ar.lc,r3
 146 { .mib  sub             r10=r35,r0,1
 147         mov             r3=ar.lc
 148         brp.loop.imp    .L_bn_add_words_ctop,.L_bn_add_words_cend-16
 149                                         }
 150         .body
 151 { .mib  mov             r14=r32                 // rp
 152         mov             r9=pr           };;
 153 { .mii  mov             r15=r33                 // ap
 154         mov             ar.lc=r10
 155         mov             ar.ec=6         }
 156 { .mib  mov             r16=r34                 // bp
 157         mov             pr.rot=1<<16    }
 158
 159 .L_bn_add_words_ctop:   ;;
 160 { .mii  (p16)   ld8             r32=[r16],8       // b=*(bp++)
 161         (p18)   add             r39=r37,r34
 162         (p19)   cmp.ltu.unc     p56,p0=r40,r38  }
 163 { .mfb  (p0)    nop.m           0x0
 164         (p0)    nop.f           0x0
 165         (p0)    nop.b           0x0             }
 166 { .mii  (p16)   ld8             r35=[r15],8       // a=*(ap++)
 167         (p58)   cmp.eq.or       p57,p0=-1,r41     // (p20)
 168         (p58)   add             r41=1,r41       } // (p20)
 169 { .mfb  (p21)   st8             [r14]=r42,8       // *(rp++)=r
 170         (p0)    nop.f           0x0
 171         br.ctop.sptk    .L_bn_add_words_ctop    };;
 172 .L_bn_add_words_cend:
 173
 174 { .mii
 175 (p59)   add             r8=1,r8         // return value
 176         mov             pr=r9,-1
 177         mov             ar.lc=r3        }
 178 { .mbb  nop.b           0x0
 179         br.ret.sptk.many        b0      };;
 180 .endp   bn_add_words#
 181
 182 //
 183 // BN_ULONG bn_sub_words(BN_ULONG *rp, BN_ULONG *ap, BN_ULONG *bp,int num)
 184 //
 185 .global bn_sub_words#
 186 .proc   bn_sub_words#
 187 .align  64
 188 .space  32      // makes the loop body aligned at 64-byte boundary
 189 bn_sub_words:
 190         .prologue
 191         .fframe 0
 192         .save   ar.pfs,r2
 193 { .mii  alloc           r2=ar.pfs,4,12,0,16
 194         cmp4.le         p6,p0=r35,r0    };;
 195 { .mfb  mov             r8=r0                   // return value
 196 (p6)    br.ret.spnt.many        b0      };;
 197
 198         .save   ar.lc,r3
 199 { .mib  sub             r10=r35,r0,1
 200         mov             r3=ar.lc
 201         brp.loop.imp    .L_bn_sub_words_ctop,.L_bn_sub_words_cend-16
 202                                         }
 203         .body
 204 { .mib  mov             r14=r32                 // rp
 205         mov             r9=pr           };;
 206 { .mii  mov             r15=r33                 // ap
 207         mov             ar.lc=r10
 208         mov             ar.ec=6         }
 209 { .mib  mov             r16=r34                 // bp
 210         mov             pr.rot=1<<16    }
 211
 212 .L_bn_sub_words_ctop:   ;;
 213 { .mii  (p16)   ld8             r32=[r16],8       // b=*(bp++)
 214         (p18)   sub             r39=r37,r34
 215         (p19)   cmp.gtu.unc     p56,p0=r40,r38  }
 216 { .mfb  (p0)    nop.m           0x0
 217         (p0)    nop.f           0x0
 218         (p0)    nop.b           0x0             }
 219 { .mii  (p16)   ld8             r35=[r15],8       // a=*(ap++)
 220         (p58)   cmp.eq.or       p57,p0=0,r41      // (p20)
 221         (p58)   add             r41=-1,r41      } // (p20)
 222 { .mbb  (p21)   st8             [r14]=r42,8       // *(rp++)=r
 223         (p0)    nop.b           0x0
 224         br.ctop.sptk    .L_bn_sub_words_ctop    };;
 225 .L_bn_sub_words_cend:
 226
 227 { .mii
 228 (p59)   add             r8=1,r8         // return value
 229         mov             pr=r9,-1
 230         mov             ar.lc=r3        }
 231 { .mbb  nop.b           0x0
 232         br.ret.sptk.many        b0      };;
 233 .endp   bn_sub_words#
 234 #endif
 235
 236 #if 0
 237 #define XMA_TEMPTATION
 238 #endif
 239
 240 #if 1
 241 //
 242 // BN_ULONG bn_mul_words(BN_ULONG *rp, BN_ULONG *ap, int num, BN_ULONG w)
 243 //
 244 .global bn_mul_words#
 245 .proc   bn_mul_words#
 246 .align  64
 247 .space  32      // makes the loop body aligned at 64-byte boundary
 248 bn_mul_words:
 249         .prologue
 250         .fframe 0
 251         .save   ar.pfs,r2
 252 #ifdef XMA_TEMPTATION
 253 { .mfi  alloc           r2=ar.pfs,4,0,0,0       };;
 254 #else
 255 { .mfi  alloc           r2=ar.pfs,4,4,0,8       };;
 256 #endif
 257 { .mib  mov             r8=r0                   // return value
 258         cmp4.le         p6,p0=r34,r0
 259 (p6)    br.ret.spnt.many        b0              };;
 260
 261         .save   ar.lc,r3
 262 { .mii  sub     r10=r34,r0,1
 263         mov     r3=ar.lc
 264         mov     r9=pr                   };;
 265
 266         .body
 267 { .mib  setf.sig        f8=r35  // w
 268         mov             pr.rot=0x400001<<16
 269                         // ------^----- serves as (p48) at first (p26)
 270         brp.loop.imp    .L_bn_mul_words_ctop,.L_bn_mul_words_cend-16
 271                                         }
 272
 273 #ifndef XMA_TEMPTATION
 274
 275 { .mii  mov             r14=r32 // rp
 276         mov             r15=r33 // ap
 277         mov             ar.lc=r10       }
 278 { .mii  mov             r39=0   // serves as r33 at first (p26)
 279         mov             ar.ec=12        }
 280
 281 // This loop spins in 2*(n+11) ticks. It's scheduled for data in L2
 282 // cache (i.e. 9 ticks away) as floating point load/store instructions
 283 // bypass L1 cache and L2 latency is actually best-case scenario for
 284 // ldf8. The loop is not scalable and shall run in 2*(n+11) even on
 285 // "wider" IA-64 implementations. It's a trade-off here. n+22 loop
 286 // would give us ~5% in *overall* performance improvement on "wider"
 287 // IA-64, but would hurt Itanium for about same because of longer
 288 // epilogue. As it's a matter of few percents in either case I've
 289 // chosen to trade the scalability for development time (you can see
 290 // this very instruction sequence in bn_mul_add_words loop which in
 291 // turn is scalable).
 292 .L_bn_mul_words_ctop:   ;;
 293 { .mfi  (p25)   getf.sig        r36=f49                 // low
 294         (p21)   xmpy.lu         f45=f37,f8
 295         (p27)   cmp.ltu         p52,p48=r39,r38 }
 296 { .mfi  (p16)   ldf8            f32=[r15],8
 297         (p21)   xmpy.hu         f38=f37,f8
 298         (p0)    nop.i           0x0             };;
 299 { .mii  (p26)   getf.sig        r32=f43                 // high
 300         (p48)   add             r38=r37,r33             // (p26)
 301         (p52)   add             r38=r37,r33,1   }       // (p26)
 302 { .mfb  (p27)   st8             [r14]=r39,8
 303         (p0)    nop.f           0x0
 304         br.ctop.sptk    .L_bn_mul_words_ctop    };;
 305 .L_bn_mul_words_cend:
 306
 307 { .mii  nop.m           0x0
 308 (p49)   add             r8=r34,r0
 309 (p53)   add             r8=r34,r0,1     }
 310 { .mfb  nop.m   0x0
 311         nop.f   0x0
 312         nop.b   0x0                     }
 313
 314 #else   // XMA_TEMPTATION
 315
 316         setf.sig        f37=r0  // serves as carry at (p18) tick
 317         mov             ar.lc=r10
 318         mov             ar.ec=5
 319
 320 // Most of you examining this code very likely wonder why in the name
 321 // of Intel the following loop is commented out? Indeed, it looks so
 322 // neat that you find it hard to believe that it's something wrong
 323 // with it, right? The catch is that every iteration depends on the
 324 // result from previous one and the latter isn't available instantly.
 325 // The loop therefore spins at the latency of xma minus 1, or in other
 326 // words at 6*(n+4) ticks:-( Compare to the "production" loop above
 327 // that runs in 2*(n+11) where the low latency problem is worked around
 328 // by moving the dependency to one-tick latent interger ALU. Note that
 329 // "distance" between ldf8 and xma is not latency of ldf8, but the
 330 // *difference* between xma and ldf8 latencies.
 331 .L_bn_mul_words_ctop:   ;;
 332 { .mfi  (p16)   ldf8            f32=[r33],8
 333         (p18)   xma.hu          f38=f34,f8,f39  }
 334 { .mfb  (p20)   stf8            [r32]=f37,8
 335         (p18)   xma.lu          f35=f34,f8,f39
 336         br.ctop.sptk    .L_bn_mul_words_ctop    };;
 337 .L_bn_mul_words_cend:
 338
 339         getf.sig        r8=f41          // the return value
 340
 341 #endif  // XMA_TEMPTATION
 342
 343 { .mii  nop.m           0x0
 344         mov             pr=r9,-1
 345         mov             ar.lc=r3        }
 346 { .mfb  rum             1<<5            // clear um.mfh
 347         nop.f           0x0
 348         br.ret.sptk.many        b0      };;
 349 .endp   bn_mul_words#
 350 #endif
 351
 352 #if 1
 353 //
 354 // BN_ULONG bn_mul_add_words(BN_ULONG *rp, BN_ULONG *ap, int num, BN_ULONG w)
 355 //
 356 .global bn_mul_add_words#
 357 .proc   bn_mul_add_words#
 358 .align  64
 359 //.space        0       // makes the loop split at 64-byte boundary
 360 bn_mul_add_words:
 361         .prologue
 362         .fframe 0
 363         .save   ar.pfs,r2
 364 { .mii  alloc           r2=ar.pfs,4,12,0,16
 365         cmp4.le         p6,p0=r34,r0    };;
 366 { .mfb  mov             r8=r0                   // return value
 367 (p6)    br.ret.spnt.many        b0      };;
 368
 369         .save   ar.lc,r3
 370 { .mii  sub     r10=r34,r0,1
 371         mov     r3=ar.lc
 372         mov     r9=pr                   };;
 373
 374         .body
 375 { .mib  setf.sig        f8=r35  // w
 376         mov             pr.rot=0x400001<<16
 377                         // ------^----- serves as (p48) at first (p26)
 378         brp.loop.imp    .L_bn_mul_add_words_ctop,.L_bn_mul_add_words_cend-16
 379                                         }
 380 { .mii  mov             r14=r32 // rp
 381         mov             r15=r33 // ap
 382         mov             ar.lc=r10       }
 383 { .mii  mov             r39=0   // serves as r33 at first (p26)
 384         mov             r18=r32 // rp copy
 385         mov             ar.ec=14        }
 386
 387 // This loop spins in 3*(n+13) ticks on Itanium and should spin in
 388 // 2*(n+13) on "wider" IA-64 implementations (to be verified with new
 389 // µ-architecture manuals as they become available). As usual it's
 390 // possible to compress the epilogue, down to 10 in this case, at the
 391 // cost of scalability. Compressed (and therefore non-scalable) loop
 392 // running at 3*(n+10) would buy you ~10% on Itanium but take ~35%
 393 // from "wider" IA-64 so let it be scalable! Special attention was
 394 // paid for having the loop body split at 64-byte boundary. ld8 is
 395 // scheduled for L1 cache as the data is more than likely there.
 396 // Indeed, bn_mul_words has put it there a moment ago:-)
 397 .L_bn_mul_add_words_ctop:       ;;
 398 { .mfi  (p25)   getf.sig        r36=f49                 // low
 399         (p21)   xmpy.lu         f45=f37,f8
 400         (p27)   cmp.ltu         p52,p48=r39,r38 }
 401 { .mfi  (p16)   ldf8            f32=[r15],8
 402         (p21)   xmpy.hu         f38=f37,f8
 403         (p27)   add             r43=r43,r39     };;
 404 { .mii  (p26)   getf.sig        r32=f43                 // high
 405         (p48)   add             r38=r37,r33             // (p26)
 406         (p52)   add             r38=r37,r33,1   }       // (p26)
 407 { .mfb  (p27)   cmp.ltu.unc     p56,p0=r43,r39
 408         (p0)    nop.f           0x0
 409         (p0)    nop.b           0x0             }
 410 { .mii  (p26)   ld8             r42=[r18],8
 411         (p58)   cmp.eq.or       p57,p0=-1,r44
 412         (p58)   add             r44=1,r44       }
 413 { .mfb  (p29)   st8             [r14]=r45,8
 414         (p0)    nop.f           0x0
 415         br.ctop.sptk    .L_bn_mul_add_words_ctop};;
 416 .L_bn_mul_add_words_cend:
 417
 418 { .mii  nop.m           0x0
 419 (p51)   add             r8=r36,r0
 420 (p55)   add             r8=r36,r0,1     }
 421 { .mfb  nop.m   0x0
 422         nop.f   0x0
 423         nop.b   0x0                     };;
 424 { .mii
 425 (p59)   add             r8=1,r8
 426         mov             pr=r9,-1
 427         mov             ar.lc=r3        }
 428 { .mfb  rum             1<<5            // clear um.mfh
 429         nop.f           0x0
 430         br.ret.sptk.many        b0      };;
 431 .endp   bn_mul_add_words#
 432 #endif
 433
 434 #if 1
 435 //
 436 // void bn_sqr_words(BN_ULONG *rp, BN_ULONG *ap, int num)
 437 //
 438 .global bn_sqr_words#
 439 .proc   bn_sqr_words#
 440 .align  64
 441 .space  32      // makes the loop body aligned at 64-byte boundary
 442 bn_sqr_words:
 443         .prologue
 444         .fframe 0
 445         .save   ar.pfs,r2
 446 { .mii  alloc           r2=ar.pfs,3,0,0,0
 447         sxt4            r34=r34         };;
 448 { .mii  cmp.le          p6,p0=r34,r0
 449         mov             r8=r0           }       // return value
 450 { .mfb  nop.f           0x0
 451 (p6)    br.ret.spnt.many        b0      };;
 452
 453         .save   ar.lc,r3
 454 { .mii  sub     r10=r34,r0,1
 455         mov     r3=ar.lc
 456         mov     r9=pr                   };;
 457
 458         .body
 459 { .mib
 460         mov             pr.rot=1<<16
 461         brp.loop.imp    .L_bn_sqr_words_ctop,.L_bn_sqr_words_cend-16
 462                                         }
 463 { .mii  add             r34=8,r32
 464         mov             ar.lc=r10
 465         mov             ar.ec=18        }
 466
 467 // 2*(n+17) on Itanium, (n+17) on "wider" IA-64 implementations. It's
 468 // possible to compress the epilogue (I'm getting tired to write this
 469 // comment over and over) and get down to 2*n+16 at the cost of
 470 // scalability. The decision will very likely be reconsidered after the
 471 // benchmark program is profiled. I.e. if perfomance gain on Itanium
 472 // will appear larger than loss on "wider" IA-64, then the loop should
 473 // be explicitely split and the epilogue compressed.
 474 .L_bn_sqr_words_ctop:   ;;
 475 { .mfi  (p16)   ldf8            f32=[r33],8
 476         (p25)   xmpy.lu         f42=f41,f41
 477         (p0)    nop.i           0x0             }
 478 { .mib  (p33)   stf8            [r32]=f50,16
 479         (p0)    nop.i           0x0
 480         (p0)    nop.b           0x0             }
 481 { .mfi  (p0)    nop.m           0x0
 482         (p25)   xmpy.hu         f52=f41,f41
 483         (p0)    nop.i           0x0             }
 484 { .mib  (p33)   stf8            [r34]=f60,16
 485         (p0)    nop.i           0x0
 486         br.ctop.sptk    .L_bn_sqr_words_ctop    };;
 487 .L_bn_sqr_words_cend:
 488
 489 { .mii  nop.m           0x0
 490         mov             pr=r9,-1
 491         mov             ar.lc=r3        }
 492 { .mfb  rum             1<<5            // clear um.mfh
 493         nop.f           0x0
 494         br.ret.sptk.many        b0      };;
 495 .endp   bn_sqr_words#
 496 #endif
 497
 498 #if 1
 499 // Apparently we win nothing by implementing special bn_mul_comba8.
 500 // Yes, it is possible to reduce the number of multiplications by
 501 // almost factor of two, but then the amount of additions would
 502 // increase by factor of two (as we would have to perform those
 503 // otherwise performed by xma ourselves). Normally we would trade
 504 // anyway as multiplications are way more expensive, but not this
 505 // time... Multiplication kernel is fully pipelined and as we drain
 506 // one 128-bit multiplication result per clock cycle multiplications
 507 // are effectively as inexpensive as additions. Special implementation
 508 // might become of interest for "wider" IA-64 implementation as you'll
 509 // be able to get through the multiplication phase faster (there won't
 510 // be any stall issues as discussed in the commentary section below and
 511 // you therefore will be able to employ all 4 FP units)... But these
 512 // Itanium days it's simply too hard to justify the effort so I just
 513 // drop down to bn_mul_comba8 code:-)
 514 //
 515 // void bn_sqr_comba8(BN_ULONG *r, BN_ULONG *a)
 516 //
 517 .global bn_sqr_comba8#
 518 .proc   bn_sqr_comba8#
 519 .align  64
 520 bn_sqr_comba8:
 521         .prologue
 522         .fframe 0
 523         .save   ar.pfs,r2
 524 { .mii  alloc   r2=ar.pfs,2,1,0,0
 525         mov     r34=r33
 526         add     r14=8,r33               };;
 527         .body
 528 { .mii  add     r17=8,r34
 529         add     r15=16,r33
 530         add     r18=16,r34              }
 531 { .mfb  add     r16=24,r33
 532         br      .L_cheat_entry_point8   };;
 533 #endif
 534
 535 #if 1
 536 // I've estimated this routine to run in ~120 ticks, but in reality
 537 // (i.e. according to ar.itc) it takes ~160 ticks. Are those extra
 538 // cycles consumed for instructions fetch? Or did I misinterpret some
 539 // clause in Itanium µ-architecture manual? Comments are welcomed and
 540 // highly appreciated.
 541 //
 542 // However! It should be noted that even 160 ticks is darn good result
 543 // as it's over 10 (yes, ten, spelled as t-e-n) times faster than the
 544 // C version (compiled with gcc with inline assembler). I really
 545 // kicked compiler's butt here, didn't I? Yeah! This brings us to the
 546 // following statement. It's damn shame that this routine isn't called
 547 // very often nowadays! According to the profiler most CPU time is
 548 // consumed by bn_mul_add_words called from BN_from_montgomery. In
 549 // order to estimate what we're missing, I've compared the performance
 550 // of this routine against "traditional" implementation, i.e. against
 551 // following routine:
 552 //
 553 // void bn_mul_comba8(BN_ULONG *r, BN_ULONG *a, BN_ULONG *b)
 554 // {    r[ 8]=bn_mul_words(    &(r[0]),a,8,b[0]);
 555 //      r[ 9]=bn_mul_add_words(&(r[1]),a,8,b[1]);
 556 //      r[10]=bn_mul_add_words(&(r[2]),a,8,b[2]);
 557 //      r[11]=bn_mul_add_words(&(r[3]),a,8,b[3]);
 558 //      r[12]=bn_mul_add_words(&(r[4]),a,8,b[4]);
 559 //      r[13]=bn_mul_add_words(&(r[5]),a,8,b[5]);
 560 //      r[14]=bn_mul_add_words(&(r[6]),a,8,b[6]);
 561 //      r[15]=bn_mul_add_words(&(r[7]),a,8,b[7]);
 562 // }
 563 //
 564 // The one below is over 8 times faster than the one above:-( Even
 565 // more reasons to "combafy" bn_mul_add_mont...
 566 //
 567 // And yes, this routine really made me wish there were an optimizing
 568 // assembler! It also feels like it deserves a dedication.
 569 //
 570 //      To my wife for being there and to my kids...
 571 //
 572 // void bn_mul_comba8(BN_ULONG *r, BN_ULONG *a, BN_ULONG *b)
 573 //
 574 #define carry1  r14
 575 #define carry2  r15
 576 #define carry3  r34
 577 .global bn_mul_comba8#
 578 .proc   bn_mul_comba8#
 579 .align  64
 580 bn_mul_comba8:
 581         .prologue
 582         .fframe 0
 583         .save   ar.pfs,r2
 584 { .mii  alloc   r2=ar.pfs,3,0,0,0
 585         add     r14=8,r33
 586         add     r17=8,r34               }
 587         .body
 588 { .mii  add     r15=16,r33
 589         add     r18=16,r34
 590         add     r16=24,r33              };;
 591 .L_cheat_entry_point8:
 592 { .mmi  add     r19=24,r34
 593
 594         ldf8    f32=[r33],32            }
 595
 596 { .mmi  ldf8    f120=[r34],32
 597         ldf8    f121=[r17],32           };;
 598 { .mmi  ldf8    f122=[r18],32
 599         ldf8    f123=[r19],32           }
 600 { .mmi  ldf8    f124=[r34]
 601         ldf8    f125=[r17]              }
 602 { .mmi  ldf8    f126=[r18]
 603         ldf8    f127=[r19]              }
 604
 605 { .mmi  ldf8    f33=[r14],32
 606         ldf8    f34=[r15],32            }
 607 { .mmi  ldf8    f35=[r16],32
 608         ldf8    f36=[r33]               }
 609 { .mmi  ldf8    f37=[r14]
 610         ldf8    f38=[r15]               }
 611 { .mfi  ldf8    f39=[r16]
 612 // -------\ Entering multiplier's heaven /-------
 613 // ------------\                    /------------
 614 // -----------------\          /-----------------
 615 // ----------------------\/----------------------
 616                 xma.hu  f41=f32,f120,f0         }
 617 { .mfi          xma.lu  f40=f32,f120,f0         };; // (*)
 618 { .mfi          xma.hu  f51=f32,f121,f0         }
 619 { .mfi          xma.lu  f50=f32,f121,f0         };;
 620 { .mfi          xma.hu  f61=f32,f122,f0         }
 621 { .mfi          xma.lu  f60=f32,f122,f0         };;
 622 { .mfi          xma.hu  f71=f32,f123,f0         }
 623 { .mfi          xma.lu  f70=f32,f123,f0         };;
 624 { .mfi          xma.hu  f81=f32,f124,f0         }
 625 { .mfi          xma.lu  f80=f32,f124,f0         };;
 626 { .mfi          xma.hu  f91=f32,f125,f0         }
 627 { .mfi          xma.lu  f90=f32,f125,f0         };;
 628 { .mfi          xma.hu  f101=f32,f126,f0        }
 629 { .mfi          xma.lu  f100=f32,f126,f0        };;
 630 { .mfi          xma.hu  f111=f32,f127,f0        }
 631 { .mfi          xma.lu  f110=f32,f127,f0        };;;;
 632 // (*)  You can argue that splitting at every second bundle would
 633 //      prevent "wider" IA-64 implementations from achieving the peak
 634 //      performance. Well, not really... The catch is that if you
 635 //      intend to keep 4 FP units busy by splitting at every fourth
 636 //      bundle and thus perform these 16 multiplications in 4 ticks,
 637 //      the first bundle *below* would stall because the result from
 638 //      the first xma bundle *above* won't be available for another 3
 639 //      ticks (if not more, being an optimist, I assume that "wider"
 640 //      implementation will have same latency:-). This stall will hold
 641 //      you back and the performance would be as if every second bundle
 642 //      were split *anyway*...
 643 { .mfi  getf.sig        r16=f40
 644                 xma.hu  f42=f33,f120,f41
 645         add             r33=8,r32               }
 646 { .mfi          xma.lu  f41=f33,f120,f41        };;
 647 { .mfi  getf.sig        r24=f50
 648                 xma.hu  f52=f33,f121,f51        }
 649 { .mfi          xma.lu  f51=f33,f121,f51        };;
 650 { .mfi  st8             [r32]=r16,16
 651                 xma.hu  f62=f33,f122,f61        }
 652 { .mfi          xma.lu  f61=f33,f122,f61        };;
 653 { .mfi          xma.hu  f72=f33,f123,f71        }
 654 { .mfi          xma.lu  f71=f33,f123,f71        };;
 655 { .mfi          xma.hu  f82=f33,f124,f81        }
 656 { .mfi          xma.lu  f81=f33,f124,f81        };;
 657 { .mfi          xma.hu  f92=f33,f125,f91        }
 658 { .mfi          xma.lu  f91=f33,f125,f91        };;
 659 { .mfi          xma.hu  f102=f33,f126,f101      }
 660 { .mfi          xma.lu  f101=f33,f126,f101      };;
 661 { .mfi          xma.hu  f112=f33,f127,f111      }
 662 { .mfi          xma.lu  f111=f33,f127,f111      };;;;
 663 //-------------------------------------------------//
 664 { .mfi  getf.sig        r25=f41
 665                 xma.hu  f43=f34,f120,f42        }
 666 { .mfi          xma.lu  f42=f34,f120,f42        };;
 667 { .mfi  getf.sig        r16=f60
 668                 xma.hu  f53=f34,f121,f52        }
 669 { .mfi          xma.lu  f52=f34,f121,f52        };;
 670 { .mfi  getf.sig        r17=f51
 671                 xma.hu  f63=f34,f122,f62
 672         add             r25=r25,r24             }
 673 { .mfi          xma.lu  f62=f34,f122,f62
 674         mov             carry1=0                };;
 675 { .mfi  cmp.ltu         p6,p0=r25,r24
 676                 xma.hu  f73=f34,f123,f72        }
 677 { .mfi          xma.lu  f72=f34,f123,f72        };;
 678 { .mfi  st8             [r33]=r25,16
 679                 xma.hu  f83=f34,f124,f82
 680 (p6)    add             carry1=1,carry1         }
 681 { .mfi          xma.lu  f82=f34,f124,f82        };;
 682 { .mfi          xma.hu  f93=f34,f125,f92        }
 683 { .mfi          xma.lu  f92=f34,f125,f92        };;
 684 { .mfi          xma.hu  f103=f34,f126,f102      }
 685 { .mfi          xma.lu  f102=f34,f126,f102      };;
 686 { .mfi          xma.hu  f113=f34,f127,f112      }
 687 { .mfi          xma.lu  f112=f34,f127,f112      };;;;
 688 //-------------------------------------------------//
 689 { .mfi  getf.sig        r18=f42
 690                 xma.hu  f44=f35,f120,f43
 691         add             r17=r17,r16             }
 692 { .mfi          xma.lu  f43=f35,f120,f43        };;
 693 { .mfi  getf.sig        r24=f70
 694                 xma.hu  f54=f35,f121,f53        }
 695 { .mfi  mov             carry2=0
 696                 xma.lu  f53=f35,f121,f53        };;
 697 { .mfi  getf.sig        r25=f61
 698                 xma.hu  f64=f35,f122,f63
 699         cmp.ltu         p7,p0=r17,r16           }
 700 { .mfi  add             r18=r18,r17
 701                 xma.lu  f63=f35,f122,f63        };;
 702 { .mfi  getf.sig        r26=f52
 703                 xma.hu  f74=f35,f123,f73
 704 (p7)    add             carry2=1,carry2         }
 705 { .mfi  cmp.ltu         p7,p0=r18,r17
 706                 xma.lu  f73=f35,f123,f73
 707         add             r18=r18,carry1          };;
 708 { .mfi
 709                 xma.hu  f84=f35,f124,f83
 710 (p7)    add             carry2=1,carry2         }
 711 { .mfi  cmp.ltu         p7,p0=r18,carry1
 712                 xma.lu  f83=f35,f124,f83        };;
 713 { .mfi  st8             [r32]=r18,16
 714                 xma.hu  f94=f35,f125,f93
 715 (p7)    add             carry2=1,carry2         }
 716 { .mfi          xma.lu  f93=f35,f125,f93        };;
 717 { .mfi          xma.hu  f104=f35,f126,f103      }
 718 { .mfi          xma.lu  f103=f35,f126,f103      };;
 719 { .mfi          xma.hu  f114=f35,f127,f113      }
 720 { .mfi  mov             carry1=0
 721                 xma.lu  f113=f35,f127,f113
 722         add             r25=r25,r24             };;;;
 723 //-------------------------------------------------//
 724 { .mfi  getf.sig        r27=f43
 725                 xma.hu  f45=f36,f120,f44
 726         cmp.ltu         p6,p0=r25,r24           }
 727 { .mfi          xma.lu  f44=f36,f120,f44
 728         add             r26=r26,r25             };;
 729 { .mfi  getf.sig        r16=f80
 730                 xma.hu  f55=f36,f121,f54
 731 (p6)    add             carry1=1,carry1         }
 732 { .mfi          xma.lu  f54=f36,f121,f54        };;
 733 { .mfi  getf.sig        r17=f71
 734                 xma.hu  f65=f36,f122,f64
 735         cmp.ltu         p6,p0=r26,r25           }
 736 { .mfi          xma.lu  f64=f36,f122,f64
 737         add             r27=r27,r26             };;
 738 { .mfi  getf.sig        r18=f62
 739                 xma.hu  f75=f36,f123,f74
 740 (p6)    add             carry1=1,carry1         }
 741 { .mfi  cmp.ltu         p6,p0=r27,r26
 742                 xma.lu  f74=f36,f123,f74
 743         add             r27=r27,carry2          };;
 744 { .mfi  getf.sig        r19=f53
 745                 xma.hu  f85=f36,f124,f84
 746 (p6)    add             carry1=1,carry1         }
 747 { .mfi          xma.lu  f84=f36,f124,f84
 748         cmp.ltu         p6,p0=r27,carry2        };;
 749 { .mfi  st8             [r33]=r27,16
 750                 xma.hu  f95=f36,f125,f94
 751 (p6)    add             carry1=1,carry1         }
 752 { .mfi          xma.lu  f94=f36,f125,f94        };;
 753 { .mfi          xma.hu  f105=f36,f126,f104      }
 754 { .mfi  mov             carry2=0
 755                 xma.lu  f104=f36,f126,f104
 756         add             r17=r17,r16             };;
 757 { .mfi          xma.hu  f115=f36,f127,f114
 758         cmp.ltu         p7,p0=r17,r16           }
 759 { .mfi          xma.lu  f114=f36,f127,f114
 760         add             r18=r18,r17             };;;;
 761 //-------------------------------------------------//
 762 { .mfi  getf.sig        r20=f44
 763                 xma.hu  f46=f37,f120,f45
 764 (p7)    add             carry2=1,carry2         }
 765 { .mfi  cmp.ltu         p7,p0=r18,r17
 766                 xma.lu  f45=f37,f120,f45
 767         add             r19=r19,r18             };;
 768 { .mfi  getf.sig        r24=f90
 769                 xma.hu  f56=f37,f121,f55        }
 770 { .mfi          xma.lu  f55=f37,f121,f55        };;
 771 { .mfi  getf.sig        r25=f81
 772                 xma.hu  f66=f37,f122,f65
 773 (p7)    add             carry2=1,carry2         }
 774 { .mfi  cmp.ltu         p7,p0=r19,r18
 775                 xma.lu  f65=f37,f122,f65
 776         add             r20=r20,r19             };;
 777 { .mfi  getf.sig        r26=f72
 778                 xma.hu  f76=f37,f123,f75
 779 (p7)    add             carry2=1,carry2         }
 780 { .mfi  cmp.ltu         p7,p0=r20,r19
 781                 xma.lu  f75=f37,f123,f75
 782         add             r20=r20,carry1          };;
 783 { .mfi  getf.sig        r27=f63
 784                 xma.hu  f86=f37,f124,f85
 785 (p7)    add             carry2=1,carry2         }
 786 { .mfi          xma.lu  f85=f37,f124,f85
 787         cmp.ltu         p7,p0=r20,carry1        };;
 788 { .mfi  getf.sig        r28=f54
 789                 xma.hu  f96=f37,f125,f95
 790 (p7)    add             carry2=1,carry2         }
 791 { .mfi  st8             [r32]=r20,16
 792                 xma.lu  f95=f37,f125,f95        };;
 793 { .mfi          xma.hu  f106=f37,f126,f105      }
 794 { .mfi  mov             carry1=0
 795                 xma.lu  f105=f37,f126,f105
 796         add             r25=r25,r24             };;
 797 { .mfi          xma.hu  f116=f37,f127,f115
 798         cmp.ltu         p6,p0=r25,r24           }
 799 { .mfi          xma.lu  f115=f37,f127,f115
 800         add             r26=r26,r25             };;;;
 801 //-------------------------------------------------//
 802 { .mfi  getf.sig        r29=f45
 803                 xma.hu  f47=f38,f120,f46
 804 (p6)    add             carry1=1,carry1         }
 805 { .mfi  cmp.ltu         p6,p0=r26,r25
 806                 xma.lu  f46=f38,f120,f46
 807         add             r27=r27,r26             };;
 808 { .mfi  getf.sig        r16=f100
 809                 xma.hu  f57=f38,f121,f56
 810 (p6)    add             carry1=1,carry1         }
 811 { .mfi  cmp.ltu         p6,p0=r27,r26
 812                 xma.lu  f56=f38,f121,f56
 813         add             r28=r28,r27             };;
 814 { .mfi  getf.sig        r17=f91
 815                 xma.hu  f67=f38,f122,f66
 816 (p6)    add             carry1=1,carry1         }
 817 { .mfi  cmp.ltu         p6,p0=r28,r27
 818                 xma.lu  f66=f38,f122,f66
 819         add             r29=r29,r28             };;
 820 { .mfi  getf.sig        r18=f82
 821                 xma.hu  f77=f38,f123,f76
 822 (p6)    add             carry1=1,carry1         }
 823 { .mfi  cmp.ltu         p6,p0=r29,r28
 824                 xma.lu  f76=f38,f123,f76
 825         add             r29=r29,carry2          };;
 826 { .mfi  getf.sig        r19=f73
 827                 xma.hu  f87=f38,f124,f86
 828 (p6)    add             carry1=1,carry1         }
 829 { .mfi          xma.lu  f86=f38,f124,f86
 830         cmp.ltu         p6,p0=r29,carry2        };;
 831 { .mfi  getf.sig        r20=f64
 832                 xma.hu  f97=f38,f125,f96
 833 (p6)    add             carry1=1,carry1         }
 834 { .mfi  st8             [r33]=r29,16
 835                 xma.lu  f96=f38,f125,f96        };;
 836 { .mfi  getf.sig        r21=f55
 837                 xma.hu  f107=f38,f126,f106      }
 838 { .mfi  mov             carry2=0
 839                 xma.lu  f106=f38,f126,f106
 840         add             r17=r17,r16             };;
 841 { .mfi          xma.hu  f117=f38,f127,f116
 842         cmp.ltu         p7,p0=r17,r16           }
 843 { .mfi          xma.lu  f116=f38,f127,f116
 844         add             r18=r18,r17             };;;;
 845 //-------------------------------------------------//
 846 { .mfi  getf.sig        r22=f46
 847                 xma.hu  f48=f39,f120,f47
 848 (p7)    add             carry2=1,carry2         }
 849 { .mfi  cmp.ltu         p7,p0=r18,r17
 850                 xma.lu  f47=f39,f120,f47
 851         add             r19=r19,r18             };;
 852 { .mfi  getf.sig        r24=f110
 853                 xma.hu  f58=f39,f121,f57
 854 (p7)    add             carry2=1,carry2         }
 855 { .mfi  cmp.ltu         p7,p0=r19,r18
 856                 xma.lu  f57=f39,f121,f57
 857         add             r20=r20,r19             };;
 858 { .mfi  getf.sig        r25=f101
 859                 xma.hu  f68=f39,f122,f67
 860 (p7)    add             carry2=1,carry2         }
 861 { .mfi  cmp.ltu         p7,p0=r20,r19
 862                 xma.lu  f67=f39,f122,f67
 863         add             r21=r21,r20             };;
 864 { .mfi  getf.sig        r26=f92
 865                 xma.hu  f78=f39,f123,f77
 866 (p7)    add             carry2=1,carry2         }
 867 { .mfi  cmp.ltu         p7,p0=r21,r20
 868                 xma.lu  f77=f39,f123,f77
 869         add             r22=r22,r21             };;
 870 { .mfi  getf.sig        r27=f83
 871                 xma.hu  f88=f39,f124,f87
 872 (p7)    add             carry2=1,carry2         }
 873 { .mfi  cmp.ltu         p7,p0=r22,r21
 874                 xma.lu  f87=f39,f124,f87
 875         add             r22=r22,carry1          };;
 876 { .mfi  getf.sig        r28=f74
 877                 xma.hu  f98=f39,f125,f97
 878 (p7)    add             carry2=1,carry2         }
 879 { .mfi          xma.lu  f97=f39,f125,f97
 880         cmp.ltu         p7,p0=r22,carry1        };;
 881 { .mfi  getf.sig        r29=f65
 882                 xma.hu  f108=f39,f126,f107
 883 (p7)    add             carry2=1,carry2         }
 884 { .mfi  st8             [r32]=r22,16
 885                 xma.lu  f107=f39,f126,f107      };;
 886 { .mfi  getf.sig        r30=f56
 887                 xma.hu  f118=f39,f127,f117      }
 888 { .mfi          xma.lu  f117=f39,f127,f117      };;;;
 889 //-------------------------------------------------//
 890 // Leaving muliplier's heaven... Quite a ride, huh?
 891
 892 { .mii  getf.sig        r31=f47
 893         add             r25=r25,r24
 894         mov             carry1=0                };;
 895 { .mii          getf.sig        r16=f111
 896         cmp.ltu         p6,p0=r25,r24
 897         add             r26=r26,r25             };;
 898 { .mfb          getf.sig        r17=f102        }
 899 { .mii
 900 (p6)    add             carry1=1,carry1
 901         cmp.ltu         p6,p0=r26,r25
 902         add             r27=r27,r26             };;
 903 { .mfb  nop.m   0x0                             }
 904 { .mii
 905 (p6)    add             carry1=1,carry1
 906         cmp.ltu         p6,p0=r27,r26
 907         add             r28=r28,r27             };;
 908 { .mii          getf.sig        r18=f93
 909                 add             r17=r17,r16
 910                 mov             carry3=0        }
 911 { .mii
 912 (p6)    add             carry1=1,carry1
 913         cmp.ltu         p6,p0=r28,r27
 914         add             r29=r29,r28             };;
 915 { .mii          getf.sig        r19=f84
 916                 cmp.ltu         p7,p0=r17,r16   }
 917 { .mii
 918 (p6)    add             carry1=1,carry1
 919         cmp.ltu         p6,p0=r29,r28
 920         add             r30=r30,r29             };;
 921 { .mii          getf.sig        r20=f75
 922                 add             r18=r18,r17     }
 923 { .mii
 924 (p6)    add             carry1=1,carry1
 925         cmp.ltu         p6,p0=r30,r29
 926         add             r31=r31,r30             };;
 927 { .mfb          getf.sig        r21=f66         }
 928 { .mii  (p7)    add             carry3=1,carry3
 929                 cmp.ltu         p7,p0=r18,r17
 930                 add             r19=r19,r18     }
 931 { .mfb  nop.m   0x0                             }
 932 { .mii
 933 (p6)    add             carry1=1,carry1
 934         cmp.ltu         p6,p0=r31,r30
 935         add             r31=r31,carry2          };;
 936 { .mfb          getf.sig        r22=f57         }
 937 { .mii  (p7)    add             carry3=1,carry3
 938                 cmp.ltu         p7,p0=r19,r18
 939                 add             r20=r20,r19     }
 940 { .mfb  nop.m   0x0                             }
 941 { .mii
 942 (p6)    add             carry1=1,carry1
 943         cmp.ltu         p6,p0=r31,carry2        };;
 944 { .mfb          getf.sig        r23=f48         }
 945 { .mii  (p7)    add             carry3=1,carry3
 946                 cmp.ltu         p7,p0=r20,r19
 947                 add             r21=r21,r20     }
 948 { .mii
 949 (p6)    add             carry1=1,carry1         }
 950 { .mfb  st8             [r33]=r31,16            };;
 951
 952 { .mfb  getf.sig        r24=f112                }
 953 { .mii  (p7)    add             carry3=1,carry3
 954                 cmp.ltu         p7,p0=r21,r20
 955                 add             r22=r22,r21     };;
 956 { .mfb  getf.sig        r25=f103                }
 957 { .mii  (p7)    add             carry3=1,carry3
 958                 cmp.ltu         p7,p0=r22,r21
 959                 add             r23=r23,r22     };;
 960 { .mfb  getf.sig        r26=f94                 }
 961 { .mii  (p7)    add             carry3=1,carry3
 962                 cmp.ltu         p7,p0=r23,r22
 963                 add             r23=r23,carry1  };;
 964 { .mfb  getf.sig        r27=f85                 }
 965 { .mii  (p7)    add             carry3=1,carry3
 966                 cmp.ltu         p7,p8=r23,carry1};;
 967 { .mii  getf.sig        r28=f76
 968         add             r25=r25,r24
 969         mov             carry1=0                }
 970 { .mii          st8             [r32]=r23,16
 971         (p7)    add             carry2=1,carry3
 972         (p8)    add             carry2=0,carry3 };;
 973
 974 { .mfb  nop.m   0x0                             }
 975 { .mii  getf.sig        r29=f67
 976         cmp.ltu         p6,p0=r25,r24
 977         add             r26=r26,r25             };;
 978 { .mfb  getf.sig        r30=f58                 }
 979 { .mii
 980 (p6)    add             carry1=1,carry1
 981         cmp.ltu         p6,p0=r26,r25
 982         add             r27=r27,r26             };;
 983 { .mfb          getf.sig        r16=f113        }
 984 { .mii
 985 (p6)    add             carry1=1,carry1
 986         cmp.ltu         p6,p0=r27,r26
 987         add             r28=r28,r27             };;
 988 { .mfb          getf.sig        r17=f104        }
 989 { .mii
 990 (p6)    add             carry1=1,carry1
 991         cmp.ltu         p6,p0=r28,r27
 992         add             r29=r29,r28             };;
 993 { .mfb          getf.sig        r18=f95         }
 994 { .mii
 995 (p6)    add             carry1=1,carry1
 996         cmp.ltu         p6,p0=r29,r28
 997         add             r30=r30,r29             };;
 998 { .mii          getf.sig        r19=f86
 999                 add             r17=r17,r16
1000                 mov             carry3=0        }
1001 { .mii
1002 (p6)    add             carry1=1,carry1
1003         cmp.ltu         p6,p0=r30,r29
1004         add             r30=r30,carry2          };;
1005 { .mii          getf.sig        r20=f77
1006                 cmp.ltu         p7,p0=r17,r16
1007                 add             r18=r18,r17     }
1008 { .mii
1009 (p6)    add             carry1=1,carry1
1010         cmp.ltu         p6,p0=r30,carry2        };;
1011 { .mfb          getf.sig        r21=f68         }
1012 { .mii  st8             [r33]=r30,16
1013 (p6)    add             carry1=1,carry1         };;
1014
1015 { .mfb  getf.sig        r24=f114                }
1016 { .mii  (p7)    add             carry3=1,carry3
1017                 cmp.ltu         p7,p0=r18,r17
1018                 add             r19=r19,r18     };;
1019 { .mfb  getf.sig        r25=f105                }
1020 { .mii  (p7)    add             carry3=1,carry3
1021                 cmp.ltu         p7,p0=r19,r18
1022                 add             r20=r20,r19     };;
1023 { .mfb  getf.sig        r26=f96                 }
1024 { .mii  (p7)    add             carry3=1,carry3
1025                 cmp.ltu         p7,p0=r20,r19
1026                 add             r21=r21,r20     };;
1027 { .mfb  getf.sig        r27=f87                 }
1028 { .mii  (p7)    add             carry3=1,carry3
1029                 cmp.ltu         p7,p0=r21,r20
1030                 add             r21=r21,carry1  };;
1031 { .mib  getf.sig        r28=f78
1032         add             r25=r25,r24             }
1033 { .mib  (p7)    add             carry3=1,carry3
1034                 cmp.ltu         p7,p8=r21,carry1};;
1035 { .mii          st8             [r32]=r21,16
1036         (p7)    add             carry2=1,carry3
1037         (p8)    add             carry2=0,carry3 }
1038
1039 { .mii  mov             carry1=0
1040         cmp.ltu         p6,p0=r25,r24
1041         add             r26=r26,r25             };;
1042 { .mfb          getf.sig        r16=f115        }
1043 { .mii
1044 (p6)    add             carry1=1,carry1
1045         cmp.ltu         p6,p0=r26,r25
1046         add             r27=r27,r26             };;
1047 { .mfb          getf.sig        r17=f106        }
1048 { .mii
1049 (p6)    add             carry1=1,carry1
1050         cmp.ltu         p6,p0=r27,r26
1051         add             r28=r28,r27             };;
1052 { .mfb          getf.sig        r18=f97         }
1053 { .mii
1054 (p6)    add             carry1=1,carry1
1055         cmp.ltu         p6,p0=r28,r27
1056         add             r28=r28,carry2          };;
1057 { .mib          getf.sig        r19=f88
1058                 add             r17=r17,r16     }
1059 { .mib
1060 (p6)    add             carry1=1,carry1
1061         cmp.ltu         p6,p0=r28,carry2        };;
1062 { .mii  st8             [r33]=r28,16
1063 (p6)    add             carry1=1,carry1         }
1064
1065 { .mii          mov             carry2=0
1066                 cmp.ltu         p7,p0=r17,r16
1067                 add             r18=r18,r17     };;
1068 { .mfb  getf.sig        r24=f116                }
1069 { .mii  (p7)    add             carry2=1,carry2
1070                 cmp.ltu         p7,p0=r18,r17
1071                 add             r19=r19,r18     };;
1072 { .mfb  getf.sig        r25=f107                }
1073 { .mii  (p7)    add             carry2=1,carry2
1074                 cmp.ltu         p7,p0=r19,r18
1075                 add             r19=r19,carry1  };;
1076 { .mfb  getf.sig        r26=f98                 }
1077 { .mii  (p7)    add             carry2=1,carry2
1078                 cmp.ltu         p7,p0=r19,carry1};;
1079 { .mii          st8             [r32]=r19,16
1080         (p7)    add             carry2=1,carry2 }
1081
1082 { .mfb  add             r25=r25,r24             };;
1083
1084 { .mfb          getf.sig        r16=f117        }
1085 { .mii  mov             carry1=0
1086         cmp.ltu         p6,p0=r25,r24
1087         add             r26=r26,r25             };;
1088 { .mfb          getf.sig        r17=f108        }
1089 { .mii
1090 (p6)    add             carry1=1,carry1
1091         cmp.ltu         p6,p0=r26,r25
1092         add             r26=r26,carry2          };;
1093 { .mfb  nop.m   0x0                             }
1094 { .mii
1095 (p6)    add             carry1=1,carry1
1096         cmp.ltu         p6,p0=r26,carry2        };;
1097 { .mii  st8             [r33]=r26,16
1098 (p6)    add             carry1=1,carry1         }
1099
1100 { .mfb          add             r17=r17,r16     };;
1101 { .mfb  getf.sig        r24=f118                }
1102 { .mii          mov             carry2=0
1103                 cmp.ltu         p7,p0=r17,r16
1104                 add             r17=r17,carry1  };;
1105 { .mii  (p7)    add             carry2=1,carry2
1106                 cmp.ltu         p7,p0=r17,carry1};;
1107 { .mii          st8             [r32]=r17
1108         (p7)    add             carry2=1,carry2 };;
1109 { .mfb  add             r24=r24,carry2          };;
1110 { .mib  st8             [r33]=r24               }
1111
1112 { .mib  rum             1<<5            // clear um.mfh
1113         br.ret.sptk.many        b0      };;
1114 .endp   bn_mul_comba8#
1115 .endp   bn_sqr_comba8#
1116 #undef  carry3
1117 #undef  carry2
1118 #undef  carry1
1119 #endif
1120
1121 #if 1
1122 // It's possible to make it faster (see comment to bn_sqr_comba8), but
1123 // I reckon it doesn't worth the effort. Basically because the routine
1124 // (actually both of them) practically never called... So I just play
1125 // same trick as with bn_sqr_comba8.
1126 //
1127 // void bn_sqr_comba4(BN_ULONG *r, BN_ULONG *a)
1128 //
1129 .global bn_sqr_comba4#
1130 .proc   bn_sqr_comba4#
1131 .align  64
1132 bn_sqr_comba4:
1133         .prologue
1134         .fframe 0
1135         .save   ar.pfs,r2
1136 { .mii  alloc   r2=ar.pfs,2,1,0,0
1137         mov     r34=r33
1138         add     r14=8,r33               };;
1139         .body
1140 { .mii  add     r17=8,r34
1141         add     r15=16,r33
1142         add     r18=16,r34              }
1143 { .mfb  add     r16=24,r33
1144         br      .L_cheat_entry_point4   };;
1145 #endif
1146
1147 #if 1
1148 // Runs in ~115 cycles and ~4.5 times faster than C. Well, whatever...
1149 //
1150 // void bn_mul_comba4(BN_ULONG *r, BN_ULONG *a, BN_ULONG *b)
1151 //
1152 #define carry1  r14
1153 #define carry2  r15
1154 .global bn_mul_comba4#
1155 .proc   bn_mul_comba4#
1156 .align  64
1157 bn_mul_comba4:
1158         .prologue
1159         .fframe 0
1160         .save   ar.pfs,r2
1161 { .mii  alloc   r2=ar.pfs,3,0,0,0
1162         add     r14=8,r33
1163         add     r17=8,r34               }
1164         .body
1165 { .mii  add     r15=16,r33
1166         add     r18=16,r34
1167         add     r16=24,r33              };;
1168 .L_cheat_entry_point4:
1169 { .mmi  add     r19=24,r34
1170
1171         ldf8    f32=[r33]               }
1172
1173 { .mmi  ldf8    f120=[r34]
1174         ldf8    f121=[r17]              };;
1175 { .mmi  ldf8    f122=[r18]
1176         ldf8    f123=[r19]              }
1177
1178 { .mmi  ldf8    f33=[r14]
1179         ldf8    f34=[r15]               }
1180 { .mfi  ldf8    f35=[r16]
1181
1182                 xma.hu  f41=f32,f120,f0         }
1183 { .mfi          xma.lu  f40=f32,f120,f0         };;
1184 { .mfi          xma.hu  f51=f32,f121,f0         }
1185 { .mfi          xma.lu  f50=f32,f121,f0         };;
1186 { .mfi          xma.hu  f61=f32,f122,f0         }
1187 { .mfi          xma.lu  f60=f32,f122,f0         };;
1188 { .mfi          xma.hu  f71=f32,f123,f0         }
1189 { .mfi          xma.lu  f70=f32,f123,f0         };;;;
1190 // Major stall takes place here, and 3 more places below. Result from
1191 // first xma is not available for another 3 ticks.
1192 { .mfi  getf.sig        r16=f40
1193                 xma.hu  f42=f33,f120,f41
1194         add             r33=8,r32               }
1195 { .mfi          xma.lu  f41=f33,f120,f41        };;
1196 { .mfi  getf.sig        r24=f50
1197                 xma.hu  f52=f33,f121,f51        }
1198 { .mfi          xma.lu  f51=f33,f121,f51        };;
1199 { .mfi  st8             [r32]=r16,16
1200                 xma.hu  f62=f33,f122,f61        }
1201 { .mfi          xma.lu  f61=f33,f122,f61        };;
1202 { .mfi          xma.hu  f72=f33,f123,f71        }
1203 { .mfi          xma.lu  f71=f33,f123,f71        };;;;
1204 //-------------------------------------------------//
1205 { .mfi  getf.sig        r25=f41
1206                 xma.hu  f43=f34,f120,f42        }
1207 { .mfi          xma.lu  f42=f34,f120,f42        };;
1208 { .mfi  getf.sig        r16=f60
1209                 xma.hu  f53=f34,f121,f52        }
1210 { .mfi          xma.lu  f52=f34,f121,f52        };;
1211 { .mfi  getf.sig        r17=f51
1212                 xma.hu  f63=f34,f122,f62
1213         add             r25=r25,r24             }
1214 { .mfi  mov             carry1=0
1215                 xma.lu  f62=f34,f122,f62        };;
1216 { .mfi  st8             [r33]=r25,16
1217                 xma.hu  f73=f34,f123,f72
1218         cmp.ltu         p6,p0=r25,r24           }
1219 { .mfi          xma.lu  f72=f34,f123,f72        };;;;
1220 //-------------------------------------------------//
1221 { .mfi  getf.sig        r18=f42
1222                 xma.hu  f44=f35,f120,f43
1223 (p6)    add             carry1=1,carry1         }
1224 { .mfi  add             r17=r17,r16
1225                 xma.lu  f43=f35,f120,f43
1226         mov             carry2=0                };;
1227 { .mfi  getf.sig        r24=f70
1228                 xma.hu  f54=f35,f121,f53
1229         cmp.ltu         p7,p0=r17,r16           }
1230 { .mfi          xma.lu  f53=f35,f121,f53        };;
1231 { .mfi  getf.sig        r25=f61
1232                 xma.hu  f64=f35,f122,f63
1233         add             r18=r18,r17             }
1234 { .mfi          xma.lu  f63=f35,f122,f63
1235 (p7)    add             carry2=1,carry2         };;
1236 { .mfi  getf.sig        r26=f52
1237                 xma.hu  f74=f35,f123,f73
1238         cmp.ltu         p7,p0=r18,r17           }
1239 { .mfi          xma.lu  f73=f35,f123,f73
1240         add             r18=r18,carry1          };;
1241 //-------------------------------------------------//
1242 { .mii  st8             [r32]=r18,16
1243 (p7)    add             carry2=1,carry2
1244         cmp.ltu         p7,p0=r18,carry1        };;
1245
1246 { .mfi  getf.sig        r27=f43 // last major stall
1247 (p7)    add             carry2=1,carry2         };;
1248 { .mii          getf.sig        r16=f71
1249         add             r25=r25,r24
1250         mov             carry1=0                };;
1251 { .mii          getf.sig        r17=f62
1252         cmp.ltu         p6,p0=r25,r24
1253         add             r26=r26,r25             };;
1254 { .mii
1255 (p6)    add             carry1=1,carry1
1256         cmp.ltu         p6,p0=r26,r25
1257         add             r27=r27,r26             };;
1258 { .mii
1259 (p6)    add             carry1=1,carry1
1260         cmp.ltu         p6,p0=r27,r26
1261         add             r27=r27,carry2          };;
1262 { .mii          getf.sig        r18=f53
1263 (p6)    add             carry1=1,carry1
1264         cmp.ltu         p6,p0=r27,carry2        };;
1265 { .mfi  st8             [r33]=r27,16
1266 (p6)    add             carry1=1,carry1         }
1267
1268 { .mii          getf.sig        r19=f44
1269                 add             r17=r17,r16
1270                 mov             carry2=0        };;
1271 { .mii  getf.sig        r24=f72
1272                 cmp.ltu         p7,p0=r17,r16
1273                 add             r18=r18,r17     };;
1274 { .mii  (p7)    add             carry2=1,carry2
1275                 cmp.ltu         p7,p0=r18,r17
1276                 add             r19=r19,r18     };;
1277 { .mii  (p7)    add             carry2=1,carry2
1278                 cmp.ltu         p7,p0=r19,r18
1279                 add             r19=r19,carry1  };;
1280 { .mii  getf.sig        r25=f63
1281         (p7)    add             carry2=1,carry2
1282                 cmp.ltu         p7,p0=r19,carry1};;
1283 { .mii          st8             [r32]=r19,16
1284         (p7)    add             carry2=1,carry2 }
1285
1286 { .mii  getf.sig        r26=f54
1287         add             r25=r25,r24
1288         mov             carry1=0                };;
1289 { .mii          getf.sig        r16=f73
1290         cmp.ltu         p6,p0=r25,r24
1291         add             r26=r26,r25             };;
1292 { .mii
1293 (p6)    add             carry1=1,carry1
1294         cmp.ltu         p6,p0=r26,r25
1295         add             r26=r26,carry2          };;
1296 { .mii          getf.sig        r17=f64
1297 (p6)    add             carry1=1,carry1
1298         cmp.ltu         p6,p0=r26,carry2        };;
1299 { .mii  st8             [r33]=r26,16
1300 (p6)    add             carry1=1,carry1         }
1301
1302 { .mii  getf.sig        r24=f74
1303                 add             r17=r17,r16
1304                 mov             carry2=0        };;
1305 { .mii          cmp.ltu         p7,p0=r17,r16
1306                 add             r17=r17,carry1  };;
1307
1308 { .mii  (p7)    add             carry2=1,carry2
1309                 cmp.ltu         p7,p0=r17,carry1};;
1310 { .mii          st8             [r32]=r17,16
1311         (p7)    add             carry2=1,carry2 };;
1312
1313 { .mii  add             r24=r24,carry2          };;
1314 { .mii  st8             [r33]=r24               }
1315
1316 { .mib  rum             1<<5            // clear um.mfh
1317         br.ret.sptk.many        b0      };;
1318 .endp   bn_mul_comba4#
1319 .endp   bn_sqr_comba4#
1320 #undef  carry2
1321 #undef  carry1
1322 #endif
1323
1324 #if 1
1325 //
1326 // BN_ULONG bn_div_words(BN_ULONG h, BN_ULONG l, BN_ULONG d)
1327 //
1328 // In the nutshell it's a port of my MIPS III/IV implementation.
1329 //
1330 #define AT      r14
1331 #define H       r16
1332 #define HH      r20
1333 #define L       r17
1334 #define D       r18
1335 #define DH      r22
1336 #define I       r21
1337
1338 #define cont    p16
1339 #define break   p0      // p20
1340 #define equ     p24
1341 .global abort#
1342 .global bn_div_words#
1343 .proc   bn_div_words#
1344 .align  64
1345 bn_div_words:
1346         .prologue
1347         .fframe 0
1348         .save   ar.pfs,r2
1349         .save   b0,r3
1350 { .mii  alloc           r2=ar.pfs,3,5,0,8
1351         mov             r3=b0
1352         mov             r10=pr          };;
1353 { .mmb  cmp.eq          p6,p0=r34,r0
1354         mov             r8=-1
1355 (p6)    br.ret.spnt.many        b0      };;
1356
1357         .body
1358 { .mii  mov             H=r32           // save h
1359         mov             ar.ec=0         // don't rotate at exit
1360         mov             pr.rot=0        }
1361 { .mii  mov             L=r33           // save l
1362         mov             r36=r0          }
1363
1364 1:      ;;      // -vv- note signed comparison
1365 { .mfi  (p0)    cmp.lt          p16,p0=r0,r34   // d
1366         (p0)    shladd          r33=r34,1,r0    }
1367 { .mfb  (p0)    add             r35=1,r36
1368         (p0)    nop.f           0x0
1369 (p16)   br.wtop.dpnt            1b              };;
1370
1371 { .mii  mov             D=r34
1372         shr.u           DH=r34,32
1373         sub             r35=64,r36              };;
1374 { .mii  setf.sig        f7=DH
1375         shr.u           AT=H,r35
1376         mov             I=r36                   };;
1377 { .mib  cmp.ne          p6,p0=r0,AT
1378         shl             H=H,r36
1379 (p6)    br.call.spnt.clr        b0=abort        };;     // overflow, die...
1380
1381 { .mfi  fcvt.xuf.s1     f7=f7
1382         shr.u           AT=L,r35                };;
1383 { .mii  shl             L=L,r36
1384         or              H=H,AT                  };;
1385
1386 { .mii  nop.m           0x0
1387         cmp.leu         p6,p0=D,H;;
1388 (p6)    sub             H=H,D                   }
1389
1390 { .mlx  setf.sig        f14=D
1391         movl            AT=0xffffffff           }
1392 ///////////////////////////////////////////////////////////
1393 { .mii  setf.sig        f6=H
1394         shr.u           HH=H,32;;
1395         cmp.eq          p6,p7=HH,DH             };;
1396 { .mfb
1397 (p6)    setf.sig        f8=AT
1398 (p7)    fcvt.xuf.s1     f6=f6
1399 (p7)    br.call.sptk    b6=.L_udiv64_32_b6      };;
1400
1401 { .mfi  getf.sig        r33=f8                          // q
1402         xmpy.lu         f9=f8,f14               }
1403 { .mfi  xmpy.hu         f10=f8,f14
1404         shrp            H=H,L,32                };;
1405
1406 { .mmi  getf.sig        r35=f9                          // tl
1407         getf.sig        r31=f10                 };;     // th
1408
1409 2:      ;;
1410 { .mii  (p0)    add             r32=-1,r33
1411         (p0)    cmp.eq          equ,cont=HH,r31         };;
1412 { .mii  (p0)    cmp.ltu         p8,p0=r35,D
1413         (p0)    sub             r34=r35,D
1414         (equ)   cmp.leu         break,cont=r35,H        };;
1415 { .mib  (cont)  cmp.leu         cont,break=HH,r31
1416         (p8)    add             r31=-1,r31
1417 (cont)  br.wtop.spnt            2b                      };;
1418 ///////////////////////////////////////////////////////////
1419         shl             r8=r33,32
1420         sub             H=H,r35
1421         shl             L=L,32
1422 ///////////////////////////////////////////////////////////
1423 { .mii  setf.sig        f6=H
1424         shr.u           HH=H,32;;
1425         cmp.eq          p6,p7=HH,DH             };;
1426 { .mfb
1427 (p6)    setf.sig        f8=AT
1428 (p7)    fcvt.xuf.s1     f6=f6
1429 (p7)    br.call.sptk    b6=.L_udiv64_32_b6      };;
1430
1431 { .mfi  getf.sig        r33=f8                          // q
1432         xmpy.lu         f9=f8,f14               }
1433 { .mfi  xmpy.hu         f10=f8,f14
1434         shrp            H=H,L,32                };;
1435
1436 { .mmi  getf.sig        r35=f9                          // tl
1437         getf.sig        r31=f10                 };;     // th
1438
1439 2:      ;;
1440 { .mii  (p0)    add             r32=-1,r33
1441         (p0)    cmp.eq          equ,cont=HH,r31         };;
1442 { .mii  (p0)    cmp.ltu         p8,p0=r35,D
1443         (p0)    sub             r34=r35,D
1444         (equ)   cmp.leu         break,cont=r35,H        };;
1445 { .mib  (cont)  cmp.leu         cont,break=HH,r31
1446         (p8)    add             r31=-1,r31
1447 (cont)  br.wtop.spnt            2b                      };;
1448 ///////////////////////////////////////////////////////////
1449 { .mii  sub     H=H,r35
1450         or      r8=r8,r33
1451         mov     ar.pfs=r2               };;
1452 { .mii  shr.u   r9=H,I                  // remainder if anybody wants it
1453         mov     pr=r10,-1               }
1454 { .mfb  br.ret.sptk.many        b0      };;
1455
1456 // Unsigned 64 by 32 (well, by 64 for the moment) bit integer division
1457 // procedure.
1458 //
1459 // inputs:      f6 = double(a), f7 = double(b)
1460 // outputs:     f8 = a/b
1461 // clobbered:   f8,f9,f10,f11,PR
1462 #define PR      p15
1463 // In the nutshell this procedure is Intel code and therefore is
1464 // copyrighted to Intel Corporation (I suppose...). It's sligtly
1465 // modified for specific needs.
1466 .align  32
1467 .space  16
1468 .L_udiv64_32_b6:
1469         frcpa.s1        f8,PR=f6,f7;;           // [0]  y0 = 1 / b
1470
1471 (PR)    fnma.s1         f9=f7,f8,f1             // [5]  e0 = 1 - b * y0
1472 (PR)    fmpy.s1         f10=f6,f8;;             // [5]  q0 = a * y0
1473 (PR)    fmpy.s1         f11=f9,f9               // [10] e1 = e0 * e0
1474 (PR)    fma.s1          f10=f9,f10,f10;;        // [10] q1 = q0 + e0 * q0
1475 (PR)    fma.s1          f8=f9,f8,f8     //;;    // [15] y1 = y0 + e0 * y0
1476 (PR)    fma.s1          f9=f11,f10,f10;;        // [15] q2 = q1 + e1 * q1
1477 (PR)    fma.s1          f8=f11,f8,f8    //;;    // [20] y2 = y1 + e1 * y1
1478 (PR)    fnma.s1         f10=f7,f9,f6;;          // [20] r2 = a - b * q2
1479 (PR)    fma.s1          f8=f10,f8,f9;;          // [25] q3 = q2 + r2 * y2
1480
1481         fcvt.fxu.trunc.s1       f8=f8           // [30] q = trunc(q3)
1482         br.ret.sptk.many        b6;;
1483 .endp   bn_div_words#
1484 #endif