Support for ILP32 on HPUX-IA64.
[openssl.git] / crypto / bn / asm / ia64.S
1 .explicit
2 .text
3 .ident  "ia64.S, Version 1.2"
4 .ident  "IA-64 ISA artwork by Andy Polyakov <appro@fy.chalmers.se>"
5
6 //
7 // ====================================================================
8 // Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
9 // project.
10 //
11 // Rights for redistribution and usage in source and binary forms are
12 // granted according to the OpenSSL license. Warranty of any kind is
13 // disclaimed.
14 // ====================================================================
15 //
16
17 // Q.   How much faster does it get?
18 // A.   Here is the output from 'openssl speed rsa dsa' for vanilla
19 //      0.9.6a compiled with gcc version 2.96 20000731 (Red Hat
20 //      Linux 7.1 2.96-81):
21 //
22 //                        sign    verify    sign/s verify/s
23 //      rsa  512 bits   0.0036s   0.0003s    275.3   2999.2
24 //      rsa 1024 bits   0.0203s   0.0011s     49.3    894.1
25 //      rsa 2048 bits   0.1331s   0.0040s      7.5    250.9
26 //      rsa 4096 bits   0.9270s   0.0147s      1.1     68.1
27 //                        sign    verify    sign/s verify/s
28 //      dsa  512 bits   0.0035s   0.0043s    288.3    234.8
29 //      dsa 1024 bits   0.0111s   0.0135s     90.0     74.2
30 //
31 //      And here is similar output but for this assembler
32 //      implementation:-)
33 //
34 //                        sign    verify    sign/s verify/s
35 //      rsa  512 bits   0.0021s   0.0001s    549.4   9638.5
36 //      rsa 1024 bits   0.0055s   0.0002s    183.8   4481.1
37 //      rsa 2048 bits   0.0244s   0.0006s     41.4   1726.3
38 //      rsa 4096 bits   0.1295s   0.0018s      7.7    561.5
39 //                        sign    verify    sign/s verify/s
40 //      dsa  512 bits   0.0012s   0.0013s    891.9    756.6
41 //      dsa 1024 bits   0.0023s   0.0028s    440.4    376.2
42 //      
43 //      Yes, you may argue that it's not fair comparison as it's
44 //      possible to craft the C implementation with BN_UMULT_HIGH
45 //      inline assembler macro. But of course! Here is the output
46 //      with the macro:
47 //
48 //                        sign    verify    sign/s verify/s
49 //      rsa  512 bits   0.0020s   0.0002s    495.0   6561.0
50 //      rsa 1024 bits   0.0086s   0.0004s    116.2   2235.7
51 //      rsa 2048 bits   0.0519s   0.0015s     19.3    667.3
52 //      rsa 4096 bits   0.3464s   0.0053s      2.9    187.7
53 //                        sign    verify    sign/s verify/s
54 //      dsa  512 bits   0.0016s   0.0020s    613.1    510.5
55 //      dsa 1024 bits   0.0045s   0.0054s    221.0    183.9
56 //
57 //      My code is still way faster, huh:-) And I believe that even
58 //      higher performance can be achieved. Note that as keys get
59 //      longer, performance gain is larger. Why? According to the
60 //      profiler there is another player in the field, namely
61 //      BN_from_montgomery consuming larger and larger portion of CPU
62 //      time as keysize decreases. I therefore consider putting effort
63 //      to assembler implementation of the following routine:
64 //
65 //      void bn_mul_add_mont (BN_ULONG *rp,BN_ULONG *np,int nl,BN_ULONG n0)
66 //      {
67 //      int      i,j;
68 //      BN_ULONG v;
69 //
70 //      for (i=0; i<nl; i++)
71 //              {
72 //              v=bn_mul_add_words(rp,np,nl,(rp[0]*n0)&BN_MASK2);
73 //              nrp++;
74 //              rp++;
75 //              if (((nrp[-1]+=v)&BN_MASK2) < v)
76 //                      for (j=0; ((++nrp[j])&BN_MASK2) == 0; j++) ;
77 //              }
78 //      }
79 //
80 //      It might as well be beneficial to implement even combaX
81 //      variants, as it appears as it can literally unleash the
82 //      performance (see comment section to bn_mul_comba8 below).
83 //
84 //      And finally for your reference the output for 0.9.6a compiled
85 //      with SGIcc version 0.01.0-12 (keep in mind that for the moment
86 //      of this writing it's not possible to convince SGIcc to use
87 //      BN_UMULT_HIGH inline assembler macro, yet the code is fast,
88 //      i.e. for a compiler generated one:-):
89 //
90 //                        sign    verify    sign/s verify/s
91 //      rsa  512 bits   0.0022s   0.0002s    452.7   5894.3
92 //      rsa 1024 bits   0.0097s   0.0005s    102.7   2002.9
93 //      rsa 2048 bits   0.0578s   0.0017s     17.3    600.2
94 //      rsa 4096 bits   0.3838s   0.0061s      2.6    164.5
95 //                        sign    verify    sign/s verify/s
96 //      dsa  512 bits   0.0018s   0.0022s    547.3    459.6
97 //      dsa 1024 bits   0.0051s   0.0062s    196.6    161.3
98 //
99 //      Oh! Benchmarks were performed on 733MHz Lion-class Itanium
100 //      system running Redhat Linux 7.1 (very special thanks to Ray
101 //      McCaffity of Williams Communications for providing an account).
102 //
103 // Q.   What's the heck with 'rum 1<<5' at the end of every function?
104 // A.   Well, by clearing the "upper FP registers written" bit of the
105 //      User Mask I want to excuse the kernel from preserving upper
106 //      (f32-f128) FP register bank over process context switch, thus
107 //      minimizing bus bandwidth consumption during the switch (i.e.
108 //      after PKI opration completes and the program is off doing
109 //      something else like bulk symmetric encryption). Having said
110 //      this, I also want to point out that it might be good idea
111 //      to compile the whole toolkit (as well as majority of the
112 //      programs for that matter) with -mfixed-range=f32-f127 command
113 //      line option. No, it doesn't prevent the compiler from writing
114 //      to upper bank, but at least discourages to do so. If you don't
115 //      like the idea you have the option to compile the module with
116 //      -Drum=nop.m in command line.
117 //
118
119 #if 1
120 //
121 // bn_[add|sub]_words routines.
122 //
123 // Loops are spinning in 2*(n+5) ticks on Itanuim (provided that the
124 // data reside in L1 cache, i.e. 2 ticks away). It's possible to
125 // compress the epilogue and get down to 2*n+6, but at the cost of
126 // scalability (the neat feature of this implementation is that it
127 // shall automagically spin in n+5 on "wider" IA-64 implementations:-)
128 // I consider that the epilogue is short enough as it is to trade tiny
129 // performance loss on Itanium for scalability.
130 //
131 // BN_ULONG bn_add_words(BN_ULONG *rp, BN_ULONG *ap, BN_ULONG *bp,int num)
132 //
133 .global bn_add_words#
134 .proc   bn_add_words#
135 .align  64
136 .skip   32      // makes the loop body aligned at 64-byte boundary
137 bn_add_words:
138         .prologue
139         .fframe 0
140         .save   ar.pfs,r2
141 { .mii; alloc           r2=ar.pfs,4,12,0,16
142         cmp4.le         p6,p0=r35,r0    };;
143 { .mfb; mov             r8=r0                   // return value
144 (p6)    br.ret.spnt.many        b0      };;
145
146         .save   ar.lc,r3
147 { .mib; sub             r10=r35,r0,1
148         mov             r3=ar.lc
149         brp.loop.imp    .L_bn_add_words_ctop,.L_bn_add_words_cend-16
150                                         }
151         .body
152 { .mib;
153 #if defined(_HPUX_SOURCE) && defined(_ILP32)
154         addp4           r14=0,r32               // rp
155 #else
156         mov             r14=r32                 // rp
157 #endif
158         mov             r9=pr           };;
159 { .mii;
160 #if defined(_HPUX_SOURCE) && defined(_ILP32)
161         addp4           r15=0,r33               // ap
162 #else
163         mov             r15=r33                 // ap
164 #endif
165         mov             ar.lc=r10
166         mov             ar.ec=6         }
167 { .mib;
168 #if defined(_HPUX_SOURCE) && defined(_ILP32)
169         addp4           r16=0,r34               // bp
170 #else
171         mov             r16=r34                 // bp
172 #endif
173         mov             pr.rot=1<<16    };;
174
175 .L_bn_add_words_ctop:
176 { .mii; (p16)   ld8             r32=[r16],8       // b=*(bp++)
177         (p18)   add             r39=r37,r34
178         (p19)   cmp.ltu.unc     p56,p0=r40,r38  }
179 { .mfb; (p0)    nop.m           0x0
180         (p0)    nop.f           0x0
181         (p0)    nop.b           0x0             }
182 { .mii; (p16)   ld8             r35=[r15],8       // a=*(ap++)
183         (p58)   cmp.eq.or       p57,p0=-1,r41     // (p20)
184         (p58)   add             r41=1,r41       } // (p20)
185 { .mfb; (p21)   st8             [r14]=r42,8       // *(rp++)=r
186         (p0)    nop.f           0x0
187         br.ctop.sptk    .L_bn_add_words_ctop    };;
188 .L_bn_add_words_cend:
189
190 { .mii;
191 (p59)   add             r8=1,r8         // return value
192         mov             pr=r9,0x1ffff
193         mov             ar.lc=r3        }
194 { .mbb; nop.b           0x0
195         br.ret.sptk.many        b0      };;
196 .endp   bn_add_words#
197
198 //
199 // BN_ULONG bn_sub_words(BN_ULONG *rp, BN_ULONG *ap, BN_ULONG *bp,int num)
200 //
201 .global bn_sub_words#
202 .proc   bn_sub_words#
203 .align  64
204 .skip   32      // makes the loop body aligned at 64-byte boundary
205 bn_sub_words:
206         .prologue
207         .fframe 0
208         .save   ar.pfs,r2
209 { .mii; alloc           r2=ar.pfs,4,12,0,16
210         cmp4.le         p6,p0=r35,r0    };;
211 { .mfb; mov             r8=r0                   // return value
212 (p6)    br.ret.spnt.many        b0      };;
213
214         .save   ar.lc,r3
215 { .mib; sub             r10=r35,r0,1
216         mov             r3=ar.lc
217         brp.loop.imp    .L_bn_sub_words_ctop,.L_bn_sub_words_cend-16
218                                         }
219         .body
220 { .mib;
221 #if defined(_HPUX_SOURCE) && defined(_ILP32)
222         addp4           r14=0,r32               // rp
223 #else
224         mov             r14=r32                 // rp
225 #endif
226         mov             r9=pr           };;
227 { .mii;
228 #if defined(_HPUX_SOURCE) && defined(_ILP32)
229         addp4           r15=0,r33               // ap
230 #else
231         mov             r15=r33                 // ap
232 #endif
233         mov             ar.lc=r10
234         mov             ar.ec=6         }
235 { .mib;
236 #if defined(_HPUX_SOURCE) && defined(_ILP32)
237         addp4           r16=0,r34               // bp
238 #else
239         mov             r16=r34                 // bp
240 #endif
241         mov             pr.rot=1<<16    };;
242
243 .L_bn_sub_words_ctop:
244 { .mii; (p16)   ld8             r32=[r16],8       // b=*(bp++)
245         (p18)   sub             r39=r37,r34
246         (p19)   cmp.gtu.unc     p56,p0=r40,r38  }
247 { .mfb; (p0)    nop.m           0x0
248         (p0)    nop.f           0x0
249         (p0)    nop.b           0x0             }
250 { .mii; (p16)   ld8             r35=[r15],8       // a=*(ap++)
251         (p58)   cmp.eq.or       p57,p0=0,r41      // (p20)
252         (p58)   add             r41=-1,r41      } // (p20)
253 { .mbb; (p21)   st8             [r14]=r42,8       // *(rp++)=r
254         (p0)    nop.b           0x0
255         br.ctop.sptk    .L_bn_sub_words_ctop    };;
256 .L_bn_sub_words_cend:
257
258 { .mii;
259 (p59)   add             r8=1,r8         // return value
260         mov             pr=r9,0x1ffff
261         mov             ar.lc=r3        }
262 { .mbb; nop.b           0x0
263         br.ret.sptk.many        b0      };;
264 .endp   bn_sub_words#
265 #endif
266
267 #if 0
268 #define XMA_TEMPTATION
269 #endif
270
271 #if 1
272 //
273 // BN_ULONG bn_mul_words(BN_ULONG *rp, BN_ULONG *ap, int num, BN_ULONG w)
274 //
275 .global bn_mul_words#
276 .proc   bn_mul_words#
277 .align  64
278 .skip   32      // makes the loop body aligned at 64-byte boundary
279 bn_mul_words:
280         .prologue
281         .fframe 0
282         .save   ar.pfs,r2
283 #ifdef XMA_TEMPTATION
284 { .mfi; alloc           r2=ar.pfs,4,0,0,0       };;
285 #else
286 { .mfi; alloc           r2=ar.pfs,4,4,0,8       };;
287 #endif
288 { .mib; mov             r8=r0                   // return value
289         cmp4.le         p6,p0=r34,r0
290 (p6)    br.ret.spnt.many        b0              };;
291
292         .save   ar.lc,r3
293 { .mii; sub     r10=r34,r0,1
294         mov     r3=ar.lc
295         mov     r9=pr                   };;
296
297         .body
298 { .mib; setf.sig        f8=r35  // w
299         mov             pr.rot=0x400001<<16
300                         // ------^----- serves as (p48) at first (p26)
301         brp.loop.imp    .L_bn_mul_words_ctop,.L_bn_mul_words_cend-16
302                                         }
303
304 #ifndef XMA_TEMPTATION
305
306 { .mii;
307 #if defined(_HPUX_SOURCE) && defined(_ILP32)
308         addp4           r14=0,r32       // rp
309         addp4           r15=0,r33       // ap
310 #else
311         mov             r14=r32         // rp
312         mov             r15=r33         // ap
313 #endif
314         mov             ar.lc=r10       }
315 { .mii; mov             r39=0   // serves as r33 at first (p26)
316         mov             ar.ec=12        };;
317
318 // This loop spins in 2*(n+11) ticks. It's scheduled for data in L2
319 // cache (i.e. 9 ticks away) as floating point load/store instructions
320 // bypass L1 cache and L2 latency is actually best-case scenario for
321 // ldf8. The loop is not scalable and shall run in 2*(n+11) even on
322 // "wider" IA-64 implementations. It's a trade-off here. n+22 loop
323 // would give us ~5% in *overall* performance improvement on "wider"
324 // IA-64, but would hurt Itanium for about same because of longer
325 // epilogue. As it's a matter of few percents in either case I've
326 // chosen to trade the scalability for development time (you can see
327 // this very instruction sequence in bn_mul_add_words loop which in
328 // turn is scalable).
329 .L_bn_mul_words_ctop:
330 { .mfi; (p25)   getf.sig        r36=f49                 // low
331         (p21)   xmpy.lu         f45=f37,f8
332         (p27)   cmp.ltu         p52,p48=r39,r38 }
333 { .mfi; (p16)   ldf8            f32=[r15],8
334         (p21)   xmpy.hu         f38=f37,f8
335         (p0)    nop.i           0x0             };;
336 { .mii; (p26)   getf.sig        r32=f43                 // high
337         .pred.rel       "mutex",p48,p52
338         (p48)   add             r38=r37,r33             // (p26)
339         (p52)   add             r38=r37,r33,1   }       // (p26)
340 { .mfb; (p27)   st8             [r14]=r39,8
341         (p0)    nop.f           0x0
342         br.ctop.sptk    .L_bn_mul_words_ctop    };;
343 .L_bn_mul_words_cend:
344
345 { .mii; nop.m           0x0
346 .pred.rel       "mutex",p49,p53
347 (p49)   add             r8=r34,r0
348 (p53)   add             r8=r34,r0,1     }
349 { .mfb; nop.m   0x0
350         nop.f   0x0
351         nop.b   0x0                     }
352
353 #else   // XMA_TEMPTATION
354
355         setf.sig        f37=r0  // serves as carry at (p18) tick
356         mov             ar.lc=r10
357         mov             ar.ec=5;;
358
359 // Most of you examining this code very likely wonder why in the name
360 // of Intel the following loop is commented out? Indeed, it looks so
361 // neat that you find it hard to believe that it's something wrong
362 // with it, right? The catch is that every iteration depends on the
363 // result from previous one and the latter isn't available instantly.
364 // The loop therefore spins at the latency of xma minus 1, or in other
365 // words at 6*(n+4) ticks:-( Compare to the "production" loop above
366 // that runs in 2*(n+11) where the low latency problem is worked around
367 // by moving the dependency to one-tick latent interger ALU. Note that
368 // "distance" between ldf8 and xma is not latency of ldf8, but the
369 // *difference* between xma and ldf8 latencies.
370 .L_bn_mul_words_ctop:
371 { .mfi; (p16)   ldf8            f32=[r33],8
372         (p18)   xma.hu          f38=f34,f8,f39  }
373 { .mfb; (p20)   stf8            [r32]=f37,8
374         (p18)   xma.lu          f35=f34,f8,f39
375         br.ctop.sptk    .L_bn_mul_words_ctop    };;
376 .L_bn_mul_words_cend:
377
378         getf.sig        r8=f41          // the return value
379
380 #endif  // XMA_TEMPTATION
381
382 { .mii; nop.m           0x0
383         mov             pr=r9,0x1ffff
384         mov             ar.lc=r3        }
385 { .mfb; rum             1<<5            // clear um.mfh
386         nop.f           0x0
387         br.ret.sptk.many        b0      };;
388 .endp   bn_mul_words#
389 #endif
390
391 #if 1
392 //
393 // BN_ULONG bn_mul_add_words(BN_ULONG *rp, BN_ULONG *ap, int num, BN_ULONG w)
394 //
395 .global bn_mul_add_words#
396 .proc   bn_mul_add_words#
397 .align  64
398 //.skip 0       // makes the loop split at 64-byte boundary
399 bn_mul_add_words:
400         .prologue
401         .fframe 0
402         .save   ar.pfs,r2
403 { .mii; alloc           r2=ar.pfs,4,12,0,16
404         cmp4.le         p6,p0=r34,r0    };;
405 { .mfb; mov             r8=r0                   // return value
406 (p6)    br.ret.spnt.many        b0      };;
407
408         .save   ar.lc,r3
409 { .mii; sub     r10=r34,r0,1
410         mov     r3=ar.lc
411         mov     r9=pr                   };;
412
413         .body
414 { .mib; setf.sig        f8=r35  // w
415         mov             pr.rot=0x400001<<16
416                         // ------^----- serves as (p48) at first (p26)
417         brp.loop.imp    .L_bn_mul_add_words_ctop,.L_bn_mul_add_words_cend-16
418                                         }
419 { .mii;
420 #if defined(_HPUX_SOURCE) && defined(_ILP32)
421         addp4           r14=0,r32       // rp
422         addp4           r15=0,r33       // ap
423 #else
424         mov             r14=r32         // rp
425         mov             r15=r33         // ap
426 #endif
427         mov             ar.lc=r10       }
428 { .mii; mov             r39=0   // serves as r33 at first (p26)
429 #if defined(_HPUX_SOURCE) && defined(_ILP32)
430         addp4           r18=0,r32       // rp copy
431 #else
432         mov             r18=r32         // rp copy
433 #endif
434         mov             ar.ec=14        };;
435
436 // This loop spins in 3*(n+13) ticks on Itanium and should spin in
437 // 2*(n+13) on "wider" IA-64 implementations (to be verified with new
438 // µ-architecture manuals as they become available). As usual it's
439 // possible to compress the epilogue, down to 10 in this case, at the
440 // cost of scalability. Compressed (and therefore non-scalable) loop
441 // running at 3*(n+10) would buy you ~10% on Itanium but take ~35%
442 // from "wider" IA-64 so let it be scalable! Special attention was
443 // paid for having the loop body split at 64-byte boundary. ld8 is
444 // scheduled for L1 cache as the data is more than likely there.
445 // Indeed, bn_mul_words has put it there a moment ago:-)
446 .L_bn_mul_add_words_ctop:
447 { .mfi; (p25)   getf.sig        r36=f49                 // low
448         (p21)   xmpy.lu         f45=f37,f8
449         (p27)   cmp.ltu         p52,p48=r39,r38 }
450 { .mfi; (p16)   ldf8            f32=[r15],8
451         (p21)   xmpy.hu         f38=f37,f8
452         (p27)   add             r43=r43,r39     };;
453 { .mii; (p26)   getf.sig        r32=f43                 // high
454         .pred.rel       "mutex",p48,p52
455         (p48)   add             r38=r37,r33             // (p26)
456         (p52)   add             r38=r37,r33,1   }       // (p26)
457 { .mfb; (p27)   cmp.ltu.unc     p56,p0=r43,r39
458         (p0)    nop.f           0x0
459         (p0)    nop.b           0x0             }
460 { .mii; (p26)   ld8             r42=[r18],8
461         (p58)   cmp.eq.or       p57,p0=-1,r44
462         (p58)   add             r44=1,r44       }
463 { .mfb; (p29)   st8             [r14]=r45,8
464         (p0)    nop.f           0x0
465         br.ctop.sptk    .L_bn_mul_add_words_ctop};;
466 .L_bn_mul_add_words_cend:
467
468 { .mii; nop.m           0x0
469 .pred.rel       "mutex",p51,p55
470 (p51)   add             r8=r36,r0
471 (p55)   add             r8=r36,r0,1     }
472 { .mfb; nop.m   0x0
473         nop.f   0x0
474         nop.b   0x0                     };;
475 { .mii;
476 (p59)   add             r8=1,r8
477         mov             pr=r9,0x1ffff
478         mov             ar.lc=r3        }
479 { .mfb; rum             1<<5            // clear um.mfh
480         nop.f           0x0
481         br.ret.sptk.many        b0      };;
482 .endp   bn_mul_add_words#
483 #endif
484
485 #if 1
486 //
487 // void bn_sqr_words(BN_ULONG *rp, BN_ULONG *ap, int num)
488 //
489 .global bn_sqr_words#
490 .proc   bn_sqr_words#
491 .align  64
492 .skip   32      // makes the loop body aligned at 64-byte boundary 
493 bn_sqr_words:
494         .prologue
495         .fframe 0
496         .save   ar.pfs,r2
497 { .mii; alloc           r2=ar.pfs,3,0,0,0
498         sxt4            r34=r34         };;
499 { .mii; cmp.le          p6,p0=r34,r0
500         mov             r8=r0           }       // return value
501 { .mfb; nop.f           0x0
502 (p6)    br.ret.spnt.many        b0      };;
503
504         .save   ar.lc,r3
505 { .mii; sub     r10=r34,r0,1
506         mov     r3=ar.lc
507         mov     r9=pr                   };;
508
509         .body
510 #if defined(_HPUX_SOURCE) && defined(_ILP32)
511 { .mii; addp4           r32=0,r32
512         addp4           r33=0,r33       };;
513 #endif
514 { .mib;
515         mov             pr.rot=1<<16
516         brp.loop.imp    .L_bn_sqr_words_ctop,.L_bn_sqr_words_cend-16
517                                         }
518 { .mii; add             r34=8,r32
519         mov             ar.lc=r10
520         mov             ar.ec=18        };;
521
522 // 2*(n+17) on Itanium, (n+17) on "wider" IA-64 implementations. It's
523 // possible to compress the epilogue (I'm getting tired to write this
524 // comment over and over) and get down to 2*n+16 at the cost of
525 // scalability. The decision will very likely be reconsidered after the
526 // benchmark program is profiled. I.e. if perfomance gain on Itanium
527 // will appear larger than loss on "wider" IA-64, then the loop should
528 // be explicitely split and the epilogue compressed.
529 .L_bn_sqr_words_ctop:
530 { .mfi; (p16)   ldf8            f32=[r33],8
531         (p25)   xmpy.lu         f42=f41,f41
532         (p0)    nop.i           0x0             }
533 { .mib; (p33)   stf8            [r32]=f50,16
534         (p0)    nop.i           0x0
535         (p0)    nop.b           0x0             }
536 { .mfi; (p0)    nop.m           0x0
537         (p25)   xmpy.hu         f52=f41,f41
538         (p0)    nop.i           0x0             }
539 { .mib; (p33)   stf8            [r34]=f60,16
540         (p0)    nop.i           0x0
541         br.ctop.sptk    .L_bn_sqr_words_ctop    };;
542 .L_bn_sqr_words_cend:
543
544 { .mii; nop.m           0x0
545         mov             pr=r9,0x1ffff
546         mov             ar.lc=r3        }
547 { .mfb; rum             1<<5            // clear um.mfh
548         nop.f           0x0
549         br.ret.sptk.many        b0      };;
550 .endp   bn_sqr_words#
551 #endif
552
553 #if 1
554 // Apparently we win nothing by implementing special bn_sqr_comba8.
555 // Yes, it is possible to reduce the number of multiplications by
556 // almost factor of two, but then the amount of additions would
557 // increase by factor of two (as we would have to perform those
558 // otherwise performed by xma ourselves). Normally we would trade
559 // anyway as multiplications are way more expensive, but not this
560 // time... Multiplication kernel is fully pipelined and as we drain
561 // one 128-bit multiplication result per clock cycle multiplications
562 // are effectively as inexpensive as additions. Special implementation
563 // might become of interest for "wider" IA-64 implementation as you'll
564 // be able to get through the multiplication phase faster (there won't
565 // be any stall issues as discussed in the commentary section below and
566 // you therefore will be able to employ all 4 FP units)... But these
567 // Itanium days it's simply too hard to justify the effort so I just
568 // drop down to bn_mul_comba8 code:-)
569 //
570 // void bn_sqr_comba8(BN_ULONG *r, BN_ULONG *a)
571 //
572 .global bn_sqr_comba8#
573 .proc   bn_sqr_comba8#
574 .align  64
575 bn_sqr_comba8:
576         .prologue
577         .fframe 0
578         .save   ar.pfs,r2
579 #if defined(_HPUX_SOURCE) && defined(_ILP32)
580 { .mii; alloc   r2=ar.pfs,2,1,0,0
581         addp4   r33=0,r33
582         addp4   r32=0,r32               };;
583 { .mii;
584 #else
585 { .mii; alloc   r2=ar.pfs,2,1,0,0
586 #endif
587         mov     r34=r33
588         add     r14=8,r33               };;
589         .body
590 { .mii; add     r17=8,r34
591         add     r15=16,r33
592         add     r18=16,r34              }
593 { .mfb; add     r16=24,r33
594         br      .L_cheat_entry_point8   };;
595 .endp   bn_sqr_comba8#
596 #endif
597
598 #if 1
599 // I've estimated this routine to run in ~120 ticks, but in reality
600 // (i.e. according to ar.itc) it takes ~160 ticks. Are those extra
601 // cycles consumed for instructions fetch? Or did I misinterpret some
602 // clause in Itanium µ-architecture manual? Comments are welcomed and
603 // highly appreciated.
604 //
605 // However! It should be noted that even 160 ticks is darn good result
606 // as it's over 10 (yes, ten, spelled as t-e-n) times faster than the
607 // C version (compiled with gcc with inline assembler). I really
608 // kicked compiler's butt here, didn't I? Yeah! This brings us to the
609 // following statement. It's damn shame that this routine isn't called
610 // very often nowadays! According to the profiler most CPU time is
611 // consumed by bn_mul_add_words called from BN_from_montgomery. In
612 // order to estimate what we're missing, I've compared the performance
613 // of this routine against "traditional" implementation, i.e. against
614 // following routine:
615 //
616 // void bn_mul_comba8(BN_ULONG *r, BN_ULONG *a, BN_ULONG *b)
617 // {    r[ 8]=bn_mul_words(    &(r[0]),a,8,b[0]);
618 //      r[ 9]=bn_mul_add_words(&(r[1]),a,8,b[1]);
619 //      r[10]=bn_mul_add_words(&(r[2]),a,8,b[2]);
620 //      r[11]=bn_mul_add_words(&(r[3]),a,8,b[3]);
621 //      r[12]=bn_mul_add_words(&(r[4]),a,8,b[4]);
622 //      r[13]=bn_mul_add_words(&(r[5]),a,8,b[5]);
623 //      r[14]=bn_mul_add_words(&(r[6]),a,8,b[6]);
624 //      r[15]=bn_mul_add_words(&(r[7]),a,8,b[7]);
625 // }
626 //
627 // The one below is over 8 times faster than the one above:-( Even
628 // more reasons to "combafy" bn_mul_add_mont...
629 //
630 // And yes, this routine really made me wish there were an optimizing
631 // assembler! It also feels like it deserves a dedication.
632 //
633 //      To my wife for being there and to my kids...
634 //
635 // void bn_mul_comba8(BN_ULONG *r, BN_ULONG *a, BN_ULONG *b)
636 //
637 #define carry1  r14
638 #define carry2  r15
639 #define carry3  r34
640 .global bn_mul_comba8#
641 .proc   bn_mul_comba8#
642 .align  64
643 bn_mul_comba8:
644         .prologue
645         .fframe 0
646         .save   ar.pfs,r2
647 #if defined(_HPUX_SOURCE) && defined(_ILP32)
648 { .mii; alloc   r2=ar.pfs,3,0,0,0
649         addp4   r33=0,r33
650         addp4   r34=0,r34               };;
651 { .mii; addp4   r32=0,r32
652 #else
653 { .mii; alloc   r2=ar.pfs,3,0,0,0
654 #endif
655         add     r14=8,r33
656         add     r17=8,r34               }
657         .body
658 { .mii; add     r15=16,r33
659         add     r18=16,r34
660         add     r16=24,r33              }
661 .L_cheat_entry_point8:
662 { .mmi; add     r19=24,r34
663
664         ldf8    f32=[r33],32            };;
665
666 { .mmi; ldf8    f120=[r34],32
667         ldf8    f121=[r17],32           }
668 { .mmi; ldf8    f122=[r18],32
669         ldf8    f123=[r19],32           };;
670 { .mmi; ldf8    f124=[r34]
671         ldf8    f125=[r17]              }
672 { .mmi; ldf8    f126=[r18]
673         ldf8    f127=[r19]              }
674
675 { .mmi; ldf8    f33=[r14],32
676         ldf8    f34=[r15],32            }
677 { .mmi; ldf8    f35=[r16],32;;
678         ldf8    f36=[r33]               }
679 { .mmi; ldf8    f37=[r14]
680         ldf8    f38=[r15]               }
681 { .mfi; ldf8    f39=[r16]
682 // -------\ Entering multiplier's heaven /-------
683 // ------------\                    /------------
684 // -----------------\          /-----------------
685 // ----------------------\/----------------------
686                 xma.hu  f41=f32,f120,f0         }
687 { .mfi;         xma.lu  f40=f32,f120,f0         };; // (*)
688 { .mfi;         xma.hu  f51=f32,f121,f0         }
689 { .mfi;         xma.lu  f50=f32,f121,f0         };;
690 { .mfi;         xma.hu  f61=f32,f122,f0         }
691 { .mfi;         xma.lu  f60=f32,f122,f0         };;
692 { .mfi;         xma.hu  f71=f32,f123,f0         }
693 { .mfi;         xma.lu  f70=f32,f123,f0         };;
694 { .mfi;         xma.hu  f81=f32,f124,f0         }
695 { .mfi;         xma.lu  f80=f32,f124,f0         };;
696 { .mfi;         xma.hu  f91=f32,f125,f0         }
697 { .mfi;         xma.lu  f90=f32,f125,f0         };;
698 { .mfi;         xma.hu  f101=f32,f126,f0        }
699 { .mfi;         xma.lu  f100=f32,f126,f0        };;
700 { .mfi;         xma.hu  f111=f32,f127,f0        }
701 { .mfi;         xma.lu  f110=f32,f127,f0        };;//
702 // (*)  You can argue that splitting at every second bundle would
703 //      prevent "wider" IA-64 implementations from achieving the peak
704 //      performance. Well, not really... The catch is that if you
705 //      intend to keep 4 FP units busy by splitting at every fourth
706 //      bundle and thus perform these 16 multiplications in 4 ticks,
707 //      the first bundle *below* would stall because the result from
708 //      the first xma bundle *above* won't be available for another 3
709 //      ticks (if not more, being an optimist, I assume that "wider"
710 //      implementation will have same latency:-). This stall will hold
711 //      you back and the performance would be as if every second bundle
712 //      were split *anyway*...
713 { .mfi; getf.sig        r16=f40
714                 xma.hu  f42=f33,f120,f41
715         add             r33=8,r32               }
716 { .mfi;         xma.lu  f41=f33,f120,f41        };;
717 { .mfi; getf.sig        r24=f50
718                 xma.hu  f52=f33,f121,f51        }
719 { .mfi;         xma.lu  f51=f33,f121,f51        };;
720 { .mfi; st8             [r32]=r16,16
721                 xma.hu  f62=f33,f122,f61        }
722 { .mfi;         xma.lu  f61=f33,f122,f61        };;
723 { .mfi;         xma.hu  f72=f33,f123,f71        }
724 { .mfi;         xma.lu  f71=f33,f123,f71        };;
725 { .mfi;         xma.hu  f82=f33,f124,f81        }
726 { .mfi;         xma.lu  f81=f33,f124,f81        };;
727 { .mfi;         xma.hu  f92=f33,f125,f91        }
728 { .mfi;         xma.lu  f91=f33,f125,f91        };;
729 { .mfi;         xma.hu  f102=f33,f126,f101      }
730 { .mfi;         xma.lu  f101=f33,f126,f101      };;
731 { .mfi;         xma.hu  f112=f33,f127,f111      }
732 { .mfi;         xma.lu  f111=f33,f127,f111      };;//
733 //-------------------------------------------------//
734 { .mfi; getf.sig        r25=f41
735                 xma.hu  f43=f34,f120,f42        }
736 { .mfi;         xma.lu  f42=f34,f120,f42        };;
737 { .mfi; getf.sig        r16=f60
738                 xma.hu  f53=f34,f121,f52        }
739 { .mfi;         xma.lu  f52=f34,f121,f52        };;
740 { .mfi; getf.sig        r17=f51
741                 xma.hu  f63=f34,f122,f62
742         add             r25=r25,r24             }
743 { .mfi;         xma.lu  f62=f34,f122,f62
744         mov             carry1=0                };;
745 { .mfi; cmp.ltu         p6,p0=r25,r24
746                 xma.hu  f73=f34,f123,f72        }
747 { .mfi;         xma.lu  f72=f34,f123,f72        };;
748 { .mfi; st8             [r33]=r25,16
749                 xma.hu  f83=f34,f124,f82
750 (p6)    add             carry1=1,carry1         }
751 { .mfi;         xma.lu  f82=f34,f124,f82        };;
752 { .mfi;         xma.hu  f93=f34,f125,f92        }
753 { .mfi;         xma.lu  f92=f34,f125,f92        };;
754 { .mfi;         xma.hu  f103=f34,f126,f102      }
755 { .mfi;         xma.lu  f102=f34,f126,f102      };;
756 { .mfi;         xma.hu  f113=f34,f127,f112      }
757 { .mfi;         xma.lu  f112=f34,f127,f112      };;//
758 //-------------------------------------------------//
759 { .mfi; getf.sig        r18=f42
760                 xma.hu  f44=f35,f120,f43
761         add             r17=r17,r16             }
762 { .mfi;         xma.lu  f43=f35,f120,f43        };;
763 { .mfi; getf.sig        r24=f70
764                 xma.hu  f54=f35,f121,f53        }
765 { .mfi; mov             carry2=0
766                 xma.lu  f53=f35,f121,f53        };;
767 { .mfi; getf.sig        r25=f61
768                 xma.hu  f64=f35,f122,f63
769         cmp.ltu         p7,p0=r17,r16           }
770 { .mfi; add             r18=r18,r17
771                 xma.lu  f63=f35,f122,f63        };;
772 { .mfi; getf.sig        r26=f52
773                 xma.hu  f74=f35,f123,f73
774 (p7)    add             carry2=1,carry2         }
775 { .mfi; cmp.ltu         p7,p0=r18,r17
776                 xma.lu  f73=f35,f123,f73
777         add             r18=r18,carry1          };;
778 { .mfi;
779                 xma.hu  f84=f35,f124,f83
780 (p7)    add             carry2=1,carry2         }
781 { .mfi; cmp.ltu         p7,p0=r18,carry1
782                 xma.lu  f83=f35,f124,f83        };;
783 { .mfi; st8             [r32]=r18,16
784                 xma.hu  f94=f35,f125,f93
785 (p7)    add             carry2=1,carry2         }
786 { .mfi;         xma.lu  f93=f35,f125,f93        };;
787 { .mfi;         xma.hu  f104=f35,f126,f103      }
788 { .mfi;         xma.lu  f103=f35,f126,f103      };;
789 { .mfi;         xma.hu  f114=f35,f127,f113      }
790 { .mfi; mov             carry1=0
791                 xma.lu  f113=f35,f127,f113
792         add             r25=r25,r24             };;//
793 //-------------------------------------------------//
794 { .mfi; getf.sig        r27=f43
795                 xma.hu  f45=f36,f120,f44
796         cmp.ltu         p6,p0=r25,r24           }
797 { .mfi;         xma.lu  f44=f36,f120,f44        
798         add             r26=r26,r25             };;
799 { .mfi; getf.sig        r16=f80
800                 xma.hu  f55=f36,f121,f54
801 (p6)    add             carry1=1,carry1         }
802 { .mfi;         xma.lu  f54=f36,f121,f54        };;
803 { .mfi; getf.sig        r17=f71
804                 xma.hu  f65=f36,f122,f64
805         cmp.ltu         p6,p0=r26,r25           }
806 { .mfi;         xma.lu  f64=f36,f122,f64
807         add             r27=r27,r26             };;
808 { .mfi; getf.sig        r18=f62
809                 xma.hu  f75=f36,f123,f74
810 (p6)    add             carry1=1,carry1         }
811 { .mfi; cmp.ltu         p6,p0=r27,r26
812                 xma.lu  f74=f36,f123,f74
813         add             r27=r27,carry2          };;
814 { .mfi; getf.sig        r19=f53
815                 xma.hu  f85=f36,f124,f84
816 (p6)    add             carry1=1,carry1         }
817 { .mfi;         xma.lu  f84=f36,f124,f84
818         cmp.ltu         p6,p0=r27,carry2        };;
819 { .mfi; st8             [r33]=r27,16
820                 xma.hu  f95=f36,f125,f94
821 (p6)    add             carry1=1,carry1         }
822 { .mfi;         xma.lu  f94=f36,f125,f94        };;
823 { .mfi;         xma.hu  f105=f36,f126,f104      }
824 { .mfi; mov             carry2=0
825                 xma.lu  f104=f36,f126,f104
826         add             r17=r17,r16             };;
827 { .mfi;         xma.hu  f115=f36,f127,f114
828         cmp.ltu         p7,p0=r17,r16           }
829 { .mfi;         xma.lu  f114=f36,f127,f114
830         add             r18=r18,r17             };;//
831 //-------------------------------------------------//
832 { .mfi; getf.sig        r20=f44
833                 xma.hu  f46=f37,f120,f45
834 (p7)    add             carry2=1,carry2         }
835 { .mfi; cmp.ltu         p7,p0=r18,r17
836                 xma.lu  f45=f37,f120,f45
837         add             r19=r19,r18             };;
838 { .mfi; getf.sig        r24=f90
839                 xma.hu  f56=f37,f121,f55        }
840 { .mfi;         xma.lu  f55=f37,f121,f55        };;
841 { .mfi; getf.sig        r25=f81
842                 xma.hu  f66=f37,f122,f65
843 (p7)    add             carry2=1,carry2         }
844 { .mfi; cmp.ltu         p7,p0=r19,r18
845                 xma.lu  f65=f37,f122,f65
846         add             r20=r20,r19             };;
847 { .mfi; getf.sig        r26=f72
848                 xma.hu  f76=f37,f123,f75
849 (p7)    add             carry2=1,carry2         }
850 { .mfi; cmp.ltu         p7,p0=r20,r19
851                 xma.lu  f75=f37,f123,f75
852         add             r20=r20,carry1          };;
853 { .mfi; getf.sig        r27=f63
854                 xma.hu  f86=f37,f124,f85
855 (p7)    add             carry2=1,carry2         }
856 { .mfi;         xma.lu  f85=f37,f124,f85
857         cmp.ltu         p7,p0=r20,carry1        };;
858 { .mfi; getf.sig        r28=f54
859                 xma.hu  f96=f37,f125,f95
860 (p7)    add             carry2=1,carry2         }
861 { .mfi; st8             [r32]=r20,16
862                 xma.lu  f95=f37,f125,f95        };;
863 { .mfi;         xma.hu  f106=f37,f126,f105      }
864 { .mfi; mov             carry1=0
865                 xma.lu  f105=f37,f126,f105
866         add             r25=r25,r24             };;
867 { .mfi;         xma.hu  f116=f37,f127,f115
868         cmp.ltu         p6,p0=r25,r24           }
869 { .mfi;         xma.lu  f115=f37,f127,f115
870         add             r26=r26,r25             };;//
871 //-------------------------------------------------//
872 { .mfi; getf.sig        r29=f45
873                 xma.hu  f47=f38,f120,f46
874 (p6)    add             carry1=1,carry1         }
875 { .mfi; cmp.ltu         p6,p0=r26,r25
876                 xma.lu  f46=f38,f120,f46
877         add             r27=r27,r26             };;
878 { .mfi; getf.sig        r16=f100
879                 xma.hu  f57=f38,f121,f56
880 (p6)    add             carry1=1,carry1         }
881 { .mfi; cmp.ltu         p6,p0=r27,r26
882                 xma.lu  f56=f38,f121,f56
883         add             r28=r28,r27             };;
884 { .mfi; getf.sig        r17=f91
885                 xma.hu  f67=f38,f122,f66
886 (p6)    add             carry1=1,carry1         }
887 { .mfi; cmp.ltu         p6,p0=r28,r27
888                 xma.lu  f66=f38,f122,f66
889         add             r29=r29,r28             };;
890 { .mfi; getf.sig        r18=f82
891                 xma.hu  f77=f38,f123,f76
892 (p6)    add             carry1=1,carry1         }
893 { .mfi; cmp.ltu         p6,p0=r29,r28
894                 xma.lu  f76=f38,f123,f76
895         add             r29=r29,carry2          };;
896 { .mfi; getf.sig        r19=f73
897                 xma.hu  f87=f38,f124,f86
898 (p6)    add             carry1=1,carry1         }
899 { .mfi;         xma.lu  f86=f38,f124,f86
900         cmp.ltu         p6,p0=r29,carry2        };;
901 { .mfi; getf.sig        r20=f64
902                 xma.hu  f97=f38,f125,f96
903 (p6)    add             carry1=1,carry1         }
904 { .mfi; st8             [r33]=r29,16
905                 xma.lu  f96=f38,f125,f96        };;
906 { .mfi; getf.sig        r21=f55
907                 xma.hu  f107=f38,f126,f106      }
908 { .mfi; mov             carry2=0
909                 xma.lu  f106=f38,f126,f106
910         add             r17=r17,r16             };;
911 { .mfi;         xma.hu  f117=f38,f127,f116
912         cmp.ltu         p7,p0=r17,r16           }
913 { .mfi;         xma.lu  f116=f38,f127,f116
914         add             r18=r18,r17             };;//
915 //-------------------------------------------------//
916 { .mfi; getf.sig        r22=f46
917                 xma.hu  f48=f39,f120,f47
918 (p7)    add             carry2=1,carry2         }
919 { .mfi; cmp.ltu         p7,p0=r18,r17
920                 xma.lu  f47=f39,f120,f47
921         add             r19=r19,r18             };;
922 { .mfi; getf.sig        r24=f110
923                 xma.hu  f58=f39,f121,f57
924 (p7)    add             carry2=1,carry2         }
925 { .mfi; cmp.ltu         p7,p0=r19,r18
926                 xma.lu  f57=f39,f121,f57
927         add             r20=r20,r19             };;
928 { .mfi; getf.sig        r25=f101
929                 xma.hu  f68=f39,f122,f67
930 (p7)    add             carry2=1,carry2         }
931 { .mfi; cmp.ltu         p7,p0=r20,r19
932                 xma.lu  f67=f39,f122,f67
933         add             r21=r21,r20             };;
934 { .mfi; getf.sig        r26=f92
935                 xma.hu  f78=f39,f123,f77
936 (p7)    add             carry2=1,carry2         }
937 { .mfi; cmp.ltu         p7,p0=r21,r20
938                 xma.lu  f77=f39,f123,f77
939         add             r22=r22,r21             };;
940 { .mfi; getf.sig        r27=f83
941                 xma.hu  f88=f39,f124,f87
942 (p7)    add             carry2=1,carry2         }
943 { .mfi; cmp.ltu         p7,p0=r22,r21
944                 xma.lu  f87=f39,f124,f87
945         add             r22=r22,carry1          };;
946 { .mfi; getf.sig        r28=f74
947                 xma.hu  f98=f39,f125,f97
948 (p7)    add             carry2=1,carry2         }
949 { .mfi;         xma.lu  f97=f39,f125,f97
950         cmp.ltu         p7,p0=r22,carry1        };;
951 { .mfi; getf.sig        r29=f65
952                 xma.hu  f108=f39,f126,f107
953 (p7)    add             carry2=1,carry2         }
954 { .mfi; st8             [r32]=r22,16
955                 xma.lu  f107=f39,f126,f107      };;
956 { .mfi; getf.sig        r30=f56
957                 xma.hu  f118=f39,f127,f117      }
958 { .mfi;         xma.lu  f117=f39,f127,f117      };;//
959 //-------------------------------------------------//
960 // Leaving muliplier's heaven... Quite a ride, huh?
961
962 { .mii; getf.sig        r31=f47
963         add             r25=r25,r24
964         mov             carry1=0                };;
965 { .mii;         getf.sig        r16=f111
966         cmp.ltu         p6,p0=r25,r24
967         add             r26=r26,r25             };;
968 { .mfb;         getf.sig        r17=f102        }
969 { .mii;
970 (p6)    add             carry1=1,carry1
971         cmp.ltu         p6,p0=r26,r25
972         add             r27=r27,r26             };;
973 { .mfb; nop.m   0x0                             }
974 { .mii;
975 (p6)    add             carry1=1,carry1
976         cmp.ltu         p6,p0=r27,r26
977         add             r28=r28,r27             };;
978 { .mii;         getf.sig        r18=f93
979                 add             r17=r17,r16
980                 mov             carry3=0        }
981 { .mii;
982 (p6)    add             carry1=1,carry1
983         cmp.ltu         p6,p0=r28,r27
984         add             r29=r29,r28             };;
985 { .mii;         getf.sig        r19=f84
986                 cmp.ltu         p7,p0=r17,r16   }
987 { .mii;
988 (p6)    add             carry1=1,carry1
989         cmp.ltu         p6,p0=r29,r28
990         add             r30=r30,r29             };;
991 { .mii;         getf.sig        r20=f75
992                 add             r18=r18,r17     }
993 { .mii;
994 (p6)    add             carry1=1,carry1
995         cmp.ltu         p6,p0=r30,r29
996         add             r31=r31,r30             };;
997 { .mfb;         getf.sig        r21=f66         }
998 { .mii; (p7)    add             carry3=1,carry3
999                 cmp.ltu         p7,p0=r18,r17
1000                 add             r19=r19,r18     }
1001 { .mfb; nop.m   0x0                             }
1002 { .mii;
1003 (p6)    add             carry1=1,carry1
1004         cmp.ltu         p6,p0=r31,r30
1005         add             r31=r31,carry2          };;
1006 { .mfb;         getf.sig        r22=f57         }
1007 { .mii; (p7)    add             carry3=1,carry3
1008                 cmp.ltu         p7,p0=r19,r18
1009                 add             r20=r20,r19     }
1010 { .mfb; nop.m   0x0                             }
1011 { .mii;
1012 (p6)    add             carry1=1,carry1
1013         cmp.ltu         p6,p0=r31,carry2        };;
1014 { .mfb;         getf.sig        r23=f48         }
1015 { .mii; (p7)    add             carry3=1,carry3
1016                 cmp.ltu         p7,p0=r20,r19
1017                 add             r21=r21,r20     }
1018 { .mii;
1019 (p6)    add             carry1=1,carry1         }
1020 { .mfb; st8             [r33]=r31,16            };;
1021
1022 { .mfb; getf.sig        r24=f112                }
1023 { .mii; (p7)    add             carry3=1,carry3
1024                 cmp.ltu         p7,p0=r21,r20
1025                 add             r22=r22,r21     };;
1026 { .mfb; getf.sig        r25=f103                }
1027 { .mii; (p7)    add             carry3=1,carry3
1028                 cmp.ltu         p7,p0=r22,r21
1029                 add             r23=r23,r22     };;
1030 { .mfb; getf.sig        r26=f94                 }
1031 { .mii; (p7)    add             carry3=1,carry3
1032                 cmp.ltu         p7,p0=r23,r22
1033                 add             r23=r23,carry1  };;
1034 { .mfb; getf.sig        r27=f85                 }
1035 { .mii; (p7)    add             carry3=1,carry3
1036                 cmp.ltu         p7,p8=r23,carry1};;
1037 { .mii; getf.sig        r28=f76
1038         add             r25=r25,r24
1039         mov             carry1=0                }
1040 { .mii;         st8             [r32]=r23,16
1041         (p7)    add             carry2=1,carry3
1042         (p8)    add             carry2=0,carry3 };;
1043
1044 { .mfb; nop.m   0x0                             }
1045 { .mii; getf.sig        r29=f67
1046         cmp.ltu         p6,p0=r25,r24
1047         add             r26=r26,r25             };;
1048 { .mfb; getf.sig        r30=f58                 }
1049 { .mii;
1050 (p6)    add             carry1=1,carry1
1051         cmp.ltu         p6,p0=r26,r25
1052         add             r27=r27,r26             };;
1053 { .mfb;         getf.sig        r16=f113        }
1054 { .mii;
1055 (p6)    add             carry1=1,carry1
1056         cmp.ltu         p6,p0=r27,r26
1057         add             r28=r28,r27             };;
1058 { .mfb;         getf.sig        r17=f104        }
1059 { .mii;
1060 (p6)    add             carry1=1,carry1
1061         cmp.ltu         p6,p0=r28,r27
1062         add             r29=r29,r28             };;
1063 { .mfb;         getf.sig        r18=f95         }
1064 { .mii;
1065 (p6)    add             carry1=1,carry1
1066         cmp.ltu         p6,p0=r29,r28
1067         add             r30=r30,r29             };;
1068 { .mii;         getf.sig        r19=f86
1069                 add             r17=r17,r16
1070                 mov             carry3=0        }
1071 { .mii;
1072 (p6)    add             carry1=1,carry1
1073         cmp.ltu         p6,p0=r30,r29
1074         add             r30=r30,carry2          };;
1075 { .mii;         getf.sig        r20=f77
1076                 cmp.ltu         p7,p0=r17,r16
1077                 add             r18=r18,r17     }
1078 { .mii;
1079 (p6)    add             carry1=1,carry1
1080         cmp.ltu         p6,p0=r30,carry2        };;
1081 { .mfb;         getf.sig        r21=f68         }
1082 { .mii; st8             [r33]=r30,16
1083 (p6)    add             carry1=1,carry1         };;
1084
1085 { .mfb; getf.sig        r24=f114                }
1086 { .mii; (p7)    add             carry3=1,carry3
1087                 cmp.ltu         p7,p0=r18,r17
1088                 add             r19=r19,r18     };;
1089 { .mfb; getf.sig        r25=f105                }
1090 { .mii; (p7)    add             carry3=1,carry3
1091                 cmp.ltu         p7,p0=r19,r18
1092                 add             r20=r20,r19     };;
1093 { .mfb; getf.sig        r26=f96                 }
1094 { .mii; (p7)    add             carry3=1,carry3
1095                 cmp.ltu         p7,p0=r20,r19
1096                 add             r21=r21,r20     };;
1097 { .mfb; getf.sig        r27=f87                 }
1098 { .mii; (p7)    add             carry3=1,carry3
1099                 cmp.ltu         p7,p0=r21,r20
1100                 add             r21=r21,carry1  };;
1101 { .mib; getf.sig        r28=f78                 
1102         add             r25=r25,r24             }
1103 { .mib; (p7)    add             carry3=1,carry3
1104                 cmp.ltu         p7,p8=r21,carry1};;
1105 { .mii;         st8             [r32]=r21,16
1106         (p7)    add             carry2=1,carry3
1107         (p8)    add             carry2=0,carry3 }
1108
1109 { .mii; mov             carry1=0
1110         cmp.ltu         p6,p0=r25,r24
1111         add             r26=r26,r25             };;
1112 { .mfb;         getf.sig        r16=f115        }
1113 { .mii;
1114 (p6)    add             carry1=1,carry1
1115         cmp.ltu         p6,p0=r26,r25
1116         add             r27=r27,r26             };;
1117 { .mfb;         getf.sig        r17=f106        }
1118 { .mii;
1119 (p6)    add             carry1=1,carry1
1120         cmp.ltu         p6,p0=r27,r26
1121         add             r28=r28,r27             };;
1122 { .mfb;         getf.sig        r18=f97         }
1123 { .mii;
1124 (p6)    add             carry1=1,carry1
1125         cmp.ltu         p6,p0=r28,r27
1126         add             r28=r28,carry2          };;
1127 { .mib;         getf.sig        r19=f88
1128                 add             r17=r17,r16     }
1129 { .mib;
1130 (p6)    add             carry1=1,carry1
1131         cmp.ltu         p6,p0=r28,carry2        };;
1132 { .mii; st8             [r33]=r28,16
1133 (p6)    add             carry1=1,carry1         }
1134
1135 { .mii;         mov             carry2=0
1136                 cmp.ltu         p7,p0=r17,r16
1137                 add             r18=r18,r17     };;
1138 { .mfb; getf.sig        r24=f116                }
1139 { .mii; (p7)    add             carry2=1,carry2
1140                 cmp.ltu         p7,p0=r18,r17
1141                 add             r19=r19,r18     };;
1142 { .mfb; getf.sig        r25=f107                }
1143 { .mii; (p7)    add             carry2=1,carry2
1144                 cmp.ltu         p7,p0=r19,r18
1145                 add             r19=r19,carry1  };;
1146 { .mfb; getf.sig        r26=f98                 }
1147 { .mii; (p7)    add             carry2=1,carry2
1148                 cmp.ltu         p7,p0=r19,carry1};;
1149 { .mii;         st8             [r32]=r19,16
1150         (p7)    add             carry2=1,carry2 }
1151
1152 { .mfb; add             r25=r25,r24             };;
1153
1154 { .mfb;         getf.sig        r16=f117        }
1155 { .mii; mov             carry1=0
1156         cmp.ltu         p6,p0=r25,r24
1157         add             r26=r26,r25             };;
1158 { .mfb;         getf.sig        r17=f108        }
1159 { .mii;
1160 (p6)    add             carry1=1,carry1
1161         cmp.ltu         p6,p0=r26,r25
1162         add             r26=r26,carry2          };;
1163 { .mfb; nop.m   0x0                             }
1164 { .mii;
1165 (p6)    add             carry1=1,carry1
1166         cmp.ltu         p6,p0=r26,carry2        };;
1167 { .mii; st8             [r33]=r26,16
1168 (p6)    add             carry1=1,carry1         }
1169
1170 { .mfb;         add             r17=r17,r16     };;
1171 { .mfb; getf.sig        r24=f118                }
1172 { .mii;         mov             carry2=0
1173                 cmp.ltu         p7,p0=r17,r16
1174                 add             r17=r17,carry1  };;
1175 { .mii; (p7)    add             carry2=1,carry2
1176                 cmp.ltu         p7,p0=r17,carry1};;
1177 { .mii;         st8             [r32]=r17
1178         (p7)    add             carry2=1,carry2 };;
1179 { .mfb; add             r24=r24,carry2          };;
1180 { .mib; st8             [r33]=r24               }
1181
1182 { .mib; rum             1<<5            // clear um.mfh
1183         br.ret.sptk.many        b0      };;
1184 .endp   bn_mul_comba8#
1185 #undef  carry3
1186 #undef  carry2
1187 #undef  carry1
1188 #endif
1189
1190 #if 1
1191 // It's possible to make it faster (see comment to bn_sqr_comba8), but
1192 // I reckon it doesn't worth the effort. Basically because the routine
1193 // (actually both of them) practically never called... So I just play
1194 // same trick as with bn_sqr_comba8.
1195 //
1196 // void bn_sqr_comba4(BN_ULONG *r, BN_ULONG *a)
1197 //
1198 .global bn_sqr_comba4#
1199 .proc   bn_sqr_comba4#
1200 .align  64
1201 bn_sqr_comba4:
1202         .prologue
1203         .fframe 0
1204         .save   ar.pfs,r2
1205 #if defined(_HPUX_SOURCE) && defined(_ILP32)
1206 { .mii; alloc   r2=ar.pfs,2,1,0,0
1207         addp4   r32=0,r32
1208         addp4   r33=0,r33               };;
1209 { .mii;
1210 #else
1211 { .mii; alloc   r2=ar.pfs,2,1,0,0
1212 #endif
1213         mov     r34=r33
1214         add     r14=8,r33               };;
1215         .body
1216 { .mii; add     r17=8,r34
1217         add     r15=16,r33
1218         add     r18=16,r34              }
1219 { .mfb; add     r16=24,r33
1220         br      .L_cheat_entry_point4   };;
1221 .endp   bn_sqr_comba4#
1222 #endif
1223
1224 #if 1
1225 // Runs in ~115 cycles and ~4.5 times faster than C. Well, whatever...
1226 //
1227 // void bn_mul_comba4(BN_ULONG *r, BN_ULONG *a, BN_ULONG *b)
1228 //
1229 #define carry1  r14
1230 #define carry2  r15
1231 .global bn_mul_comba4#
1232 .proc   bn_mul_comba4#
1233 .align  64
1234 bn_mul_comba4:
1235         .prologue
1236         .fframe 0
1237         .save   ar.pfs,r2
1238 #if defined(_HPUX_SOURCE) && defined(_ILP32)
1239 { .mii; alloc   r2=ar.pfs,3,0,0,0
1240         addp4   r33=0,r33
1241         addp4   r34=0,r34               };;
1242 { .mii; addp4   r32=0,r32
1243 #else
1244 { .mii; alloc   r2=ar.pfs,3,0,0,0
1245 #endif
1246         add     r14=8,r33
1247         add     r17=8,r34               }
1248         .body
1249 { .mii; add     r15=16,r33
1250         add     r18=16,r34
1251         add     r16=24,r33              };;
1252 .L_cheat_entry_point4:
1253 { .mmi; add     r19=24,r34
1254
1255         ldf8    f32=[r33]               }
1256
1257 { .mmi; ldf8    f120=[r34]
1258         ldf8    f121=[r17]              };;
1259 { .mmi; ldf8    f122=[r18]
1260         ldf8    f123=[r19]              }
1261
1262 { .mmi; ldf8    f33=[r14]
1263         ldf8    f34=[r15]               }
1264 { .mfi; ldf8    f35=[r16]
1265
1266                 xma.hu  f41=f32,f120,f0         }
1267 { .mfi;         xma.lu  f40=f32,f120,f0         };;
1268 { .mfi;         xma.hu  f51=f32,f121,f0         }
1269 { .mfi;         xma.lu  f50=f32,f121,f0         };;
1270 { .mfi;         xma.hu  f61=f32,f122,f0         }
1271 { .mfi;         xma.lu  f60=f32,f122,f0         };;
1272 { .mfi;         xma.hu  f71=f32,f123,f0         }
1273 { .mfi;         xma.lu  f70=f32,f123,f0         };;//
1274 // Major stall takes place here, and 3 more places below. Result from
1275 // first xma is not available for another 3 ticks.
1276 { .mfi; getf.sig        r16=f40
1277                 xma.hu  f42=f33,f120,f41
1278         add             r33=8,r32               }
1279 { .mfi;         xma.lu  f41=f33,f120,f41        };;
1280 { .mfi; getf.sig        r24=f50
1281                 xma.hu  f52=f33,f121,f51        }
1282 { .mfi;         xma.lu  f51=f33,f121,f51        };;
1283 { .mfi; st8             [r32]=r16,16
1284                 xma.hu  f62=f33,f122,f61        }
1285 { .mfi;         xma.lu  f61=f33,f122,f61        };;
1286 { .mfi;         xma.hu  f72=f33,f123,f71        }
1287 { .mfi;         xma.lu  f71=f33,f123,f71        };;//
1288 //-------------------------------------------------//
1289 { .mfi; getf.sig        r25=f41
1290                 xma.hu  f43=f34,f120,f42        }
1291 { .mfi;         xma.lu  f42=f34,f120,f42        };;
1292 { .mfi; getf.sig        r16=f60
1293                 xma.hu  f53=f34,f121,f52        }
1294 { .mfi;         xma.lu  f52=f34,f121,f52        };;
1295 { .mfi; getf.sig        r17=f51
1296                 xma.hu  f63=f34,f122,f62
1297         add             r25=r25,r24             }
1298 { .mfi; mov             carry1=0
1299                 xma.lu  f62=f34,f122,f62        };;
1300 { .mfi; st8             [r33]=r25,16
1301                 xma.hu  f73=f34,f123,f72
1302         cmp.ltu         p6,p0=r25,r24           }
1303 { .mfi;         xma.lu  f72=f34,f123,f72        };;//
1304 //-------------------------------------------------//
1305 { .mfi; getf.sig        r18=f42
1306                 xma.hu  f44=f35,f120,f43
1307 (p6)    add             carry1=1,carry1         }
1308 { .mfi; add             r17=r17,r16
1309                 xma.lu  f43=f35,f120,f43
1310         mov             carry2=0                };;
1311 { .mfi; getf.sig        r24=f70
1312                 xma.hu  f54=f35,f121,f53
1313         cmp.ltu         p7,p0=r17,r16           }
1314 { .mfi;         xma.lu  f53=f35,f121,f53        };;
1315 { .mfi; getf.sig        r25=f61
1316                 xma.hu  f64=f35,f122,f63
1317         add             r18=r18,r17             }
1318 { .mfi;         xma.lu  f63=f35,f122,f63
1319 (p7)    add             carry2=1,carry2         };;
1320 { .mfi; getf.sig        r26=f52
1321                 xma.hu  f74=f35,f123,f73
1322         cmp.ltu         p7,p0=r18,r17           }
1323 { .mfi;         xma.lu  f73=f35,f123,f73
1324         add             r18=r18,carry1          };;
1325 //-------------------------------------------------//
1326 { .mii; st8             [r32]=r18,16
1327 (p7)    add             carry2=1,carry2
1328         cmp.ltu         p7,p0=r18,carry1        };;
1329
1330 { .mfi; getf.sig        r27=f43 // last major stall
1331 (p7)    add             carry2=1,carry2         };;
1332 { .mii;         getf.sig        r16=f71
1333         add             r25=r25,r24
1334         mov             carry1=0                };;
1335 { .mii;         getf.sig        r17=f62 
1336         cmp.ltu         p6,p0=r25,r24
1337         add             r26=r26,r25             };;
1338 { .mii;
1339 (p6)    add             carry1=1,carry1
1340         cmp.ltu         p6,p0=r26,r25
1341         add             r27=r27,r26             };;
1342 { .mii;
1343 (p6)    add             carry1=1,carry1
1344         cmp.ltu         p6,p0=r27,r26
1345         add             r27=r27,carry2          };;
1346 { .mii;         getf.sig        r18=f53
1347 (p6)    add             carry1=1,carry1
1348         cmp.ltu         p6,p0=r27,carry2        };;
1349 { .mfi; st8             [r33]=r27,16
1350 (p6)    add             carry1=1,carry1         }
1351
1352 { .mii;         getf.sig        r19=f44
1353                 add             r17=r17,r16
1354                 mov             carry2=0        };;
1355 { .mii; getf.sig        r24=f72
1356                 cmp.ltu         p7,p0=r17,r16
1357                 add             r18=r18,r17     };;
1358 { .mii; (p7)    add             carry2=1,carry2
1359                 cmp.ltu         p7,p0=r18,r17
1360                 add             r19=r19,r18     };;
1361 { .mii; (p7)    add             carry2=1,carry2
1362                 cmp.ltu         p7,p0=r19,r18
1363                 add             r19=r19,carry1  };;
1364 { .mii; getf.sig        r25=f63
1365         (p7)    add             carry2=1,carry2
1366                 cmp.ltu         p7,p0=r19,carry1};;
1367 { .mii;         st8             [r32]=r19,16
1368         (p7)    add             carry2=1,carry2 }
1369
1370 { .mii; getf.sig        r26=f54
1371         add             r25=r25,r24
1372         mov             carry1=0                };;
1373 { .mii;         getf.sig        r16=f73
1374         cmp.ltu         p6,p0=r25,r24
1375         add             r26=r26,r25             };;
1376 { .mii;
1377 (p6)    add             carry1=1,carry1
1378         cmp.ltu         p6,p0=r26,r25
1379         add             r26=r26,carry2          };;
1380 { .mii;         getf.sig        r17=f64
1381 (p6)    add             carry1=1,carry1
1382         cmp.ltu         p6,p0=r26,carry2        };;
1383 { .mii; st8             [r33]=r26,16
1384 (p6)    add             carry1=1,carry1         }
1385
1386 { .mii; getf.sig        r24=f74
1387                 add             r17=r17,r16     
1388                 mov             carry2=0        };;
1389 { .mii;         cmp.ltu         p7,p0=r17,r16
1390                 add             r17=r17,carry1  };;
1391
1392 { .mii; (p7)    add             carry2=1,carry2
1393                 cmp.ltu         p7,p0=r17,carry1};;
1394 { .mii;         st8             [r32]=r17,16
1395         (p7)    add             carry2=1,carry2 };;
1396
1397 { .mii; add             r24=r24,carry2          };;
1398 { .mii; st8             [r33]=r24               }
1399
1400 { .mib; rum             1<<5            // clear um.mfh
1401         br.ret.sptk.many        b0      };;
1402 .endp   bn_mul_comba4#
1403 #undef  carry2
1404 #undef  carry1
1405 #endif
1406
1407 #if 1
1408 //
1409 // BN_ULONG bn_div_words(BN_ULONG h, BN_ULONG l, BN_ULONG d)
1410 //
1411 // In the nutshell it's a port of my MIPS III/IV implementation.
1412 //
1413 #define AT      r14
1414 #define H       r16
1415 #define HH      r20
1416 #define L       r17
1417 #define D       r18
1418 #define DH      r22
1419 #define I       r21
1420
1421 #if 0
1422 // Some preprocessors (most notably HP-UX) apper to be allergic to
1423 // macros enclosed to parenthesis as these three will be.
1424 #define cont    p16
1425 #define break   p0      // p20
1426 #define equ     p24
1427 #else
1428 cont=p16
1429 break=p0
1430 equ=p24
1431 #endif
1432
1433 .global abort#
1434 .global bn_div_words#
1435 .proc   bn_div_words#
1436 .align  64
1437 bn_div_words:
1438         .prologue
1439         .fframe 0
1440         .save   ar.pfs,r2
1441         .save   b0,r3
1442 { .mii; alloc           r2=ar.pfs,3,5,0,8
1443         mov             r3=b0
1444         mov             r10=pr          };;
1445 { .mmb; cmp.eq          p6,p0=r34,r0
1446         mov             r8=-1
1447 (p6)    br.ret.spnt.many        b0      };;
1448
1449         .body
1450 { .mii; mov             H=r32           // save h
1451         mov             ar.ec=0         // don't rotate at exit
1452         mov             pr.rot=0        }
1453 { .mii; mov             L=r33           // save l
1454         mov             r36=r0          };;
1455
1456 .L_divw_shift:  // -vv- note signed comparison
1457 { .mfi; (p0)    cmp.lt          p16,p0=r0,r34   // d
1458         (p0)    shladd          r33=r34,1,r0    }
1459 { .mfb; (p0)    add             r35=1,r36
1460         (p0)    nop.f           0x0
1461 (p16)   br.wtop.dpnt            .L_divw_shift   };;
1462
1463 { .mii; mov             D=r34
1464         shr.u           DH=r34,32
1465         sub             r35=64,r36              };;
1466 { .mii; setf.sig        f7=DH
1467         shr.u           AT=H,r35
1468         mov             I=r36                   };;
1469 { .mib; cmp.ne          p6,p0=r0,AT
1470         shl             H=H,r36
1471 (p6)    br.call.spnt.clr        b0=abort        };;     // overflow, die...
1472
1473 { .mfi; fcvt.xuf.s1     f7=f7
1474         shr.u           AT=L,r35                };;
1475 { .mii; shl             L=L,r36
1476         or              H=H,AT                  };;
1477
1478 { .mii; nop.m           0x0
1479         cmp.leu         p6,p0=D,H;;
1480 (p6)    sub             H=H,D                   }
1481
1482 { .mlx; setf.sig        f14=D
1483         movl            AT=0xffffffff           };;
1484 ///////////////////////////////////////////////////////////
1485 { .mii; setf.sig        f6=H
1486         shr.u           HH=H,32;;
1487         cmp.eq          p6,p7=HH,DH             };;
1488 { .mfb;
1489 (p6)    setf.sig        f8=AT
1490 (p7)    fcvt.xuf.s1     f6=f6
1491 (p7)    br.call.sptk    b6=.L_udiv64_32_b6      };;
1492
1493 { .mfi; getf.sig        r33=f8                          // q
1494         xmpy.lu         f9=f8,f14               }
1495 { .mfi; xmpy.hu         f10=f8,f14
1496         shrp            H=H,L,32                };;
1497
1498 { .mmi; getf.sig        r35=f9                          // tl
1499         getf.sig        r31=f10                 };;     // th
1500
1501 .L_divw_1st_iter:
1502 { .mii; (p0)    add             r32=-1,r33
1503         (p0)    cmp.eq          equ,cont=HH,r31         };;
1504 { .mii; (p0)    cmp.ltu         p8,p0=r35,D
1505         (p0)    sub             r34=r35,D
1506         (equ)   cmp.leu         break,cont=r35,H        };;
1507 { .mib; (cont)  cmp.leu         cont,break=HH,r31
1508         (p8)    add             r31=-1,r31
1509 (cont)  br.wtop.spnt            .L_divw_1st_iter        };;
1510 ///////////////////////////////////////////////////////////
1511 { .mii; sub             H=H,r35
1512         shl             r8=r33,32
1513         shl             L=L,32                  };;
1514 ///////////////////////////////////////////////////////////
1515 { .mii; setf.sig        f6=H
1516         shr.u           HH=H,32;;
1517         cmp.eq          p6,p7=HH,DH             };;
1518 { .mfb;
1519 (p6)    setf.sig        f8=AT
1520 (p7)    fcvt.xuf.s1     f6=f6
1521 (p7)    br.call.sptk    b6=.L_udiv64_32_b6      };;
1522
1523 { .mfi; getf.sig        r33=f8                          // q
1524         xmpy.lu         f9=f8,f14               }
1525 { .mfi; xmpy.hu         f10=f8,f14
1526         shrp            H=H,L,32                };;
1527
1528 { .mmi; getf.sig        r35=f9                          // tl
1529         getf.sig        r31=f10                 };;     // th
1530
1531 .L_divw_2nd_iter:
1532 { .mii; (p0)    add             r32=-1,r33
1533         (p0)    cmp.eq          equ,cont=HH,r31         };;
1534 { .mii; (p0)    cmp.ltu         p8,p0=r35,D
1535         (p0)    sub             r34=r35,D
1536         (equ)   cmp.leu         break,cont=r35,H        };;
1537 { .mib; (cont)  cmp.leu         cont,break=HH,r31
1538         (p8)    add             r31=-1,r31
1539 (cont)  br.wtop.spnt            .L_divw_2nd_iter        };;
1540 ///////////////////////////////////////////////////////////
1541 { .mii; sub     H=H,r35
1542         or      r8=r8,r33
1543         mov     ar.pfs=r2               };;
1544 { .mii; shr.u   r9=H,I                  // remainder if anybody wants it
1545         mov     pr=r10,0x1ffff          }
1546 { .mfb; br.ret.sptk.many        b0      };;
1547
1548 // Unsigned 64 by 32 (well, by 64 for the moment) bit integer division
1549 // procedure.
1550 //
1551 // inputs:      f6 = (double)a, f7 = (double)b
1552 // output:      f8 = (int)(a/b)
1553 // clobbered:   f8,f9,f10,f11,pred
1554 pred=p15
1555 // This procedure is essentially Intel code and therefore is
1556 // copyrighted to Intel Corporation (I suppose...). It's sligtly
1557 // modified for specific needs.
1558 .align  32
1559 .skip   16
1560 .L_udiv64_32_b6:
1561         frcpa.s1        f8,pred=f6,f7;;         // [0]  y0 = 1 / b
1562
1563 (pred)  fnma.s1         f9=f7,f8,f1             // [5]  e0 = 1 - b * y0
1564 (pred)  fmpy.s1         f10=f6,f8;;             // [5]  q0 = a * y0
1565 (pred)  fmpy.s1         f11=f9,f9               // [10] e1 = e0 * e0
1566 (pred)  fma.s1          f10=f9,f10,f10;;        // [10] q1 = q0 + e0 * q0
1567 (pred)  fma.s1          f8=f9,f8,f8     //;;    // [15] y1 = y0 + e0 * y0
1568 (pred)  fma.s1          f9=f11,f10,f10;;        // [15] q2 = q1 + e1 * q1
1569 (pred)  fma.s1          f8=f11,f8,f8    //;;    // [20] y2 = y1 + e1 * y1
1570 (pred)  fnma.s1         f10=f7,f9,f6;;          // [20] r2 = a - b * q2
1571 (pred)  fma.s1          f8=f10,f8,f9;;          // [25] q3 = q2 + r2 * y2
1572
1573         fcvt.fxu.trunc.s1       f8=f8           // [30] q = trunc(q3)
1574         br.ret.sptk.many        b6;;
1575 .endp   bn_div_words#
1576 #endif