3 # Specific modes implementations for SPARC Architecture 2011. There
4 # is T4 dependency though, an ASI value that is not specified in the
5 # Architecture Manual. But as SPARC universe is rather monocultural,
6 # we imply that processor capable of executing crypto instructions
7 # can handle the ASI in question as well. This means that we ought to
8 # keep eyes open when new processors emerge...
10 # As for above mentioned ASI. It's so called "block initializing
11 # store" which cancels "read" in "read-update-write" on cache lines.
12 # This is "cooperative" optimization, as it reduces overall pressure
13 # on memory interface. Benefits can't be observed/quantified with
14 # usual benchmarks, on the contrary you can notice that single-thread
15 # performance for parallelizable modes is ~1.5% worse. Special note
16 # about commented 'membar' instructions, otherwise recommended by
17 # manual. Rationale is following. Memory view is consistent from
18 # viewpoint of processor executing the code even when ASI in question
19 # is used. If thread on another processor has to access the result,
20 # its availability would have to be mediated and it can be done only
21 # through a syncronization operation which would requre ... 'membar'.
22 # All this based on suggestions from David Miller.
24 my ($inp,$out,$len,$key,$ivec,$enc)=map("%i$_",(0..5));
25 my ($ileft,$iright,$ooff,$omask,$ivoff,$blk_init)=map("%l$_",(0..7));
27 sub alg_cbc_encrypt_implement {
31 .globl ${alg}${bits}_t4_cbc_encrypt
33 ${alg}${bits}_t4_cbc_encrypt:
34 save %sp, -$::frame, %sp
35 sub $inp, $out, $blk_init ! $inp!=$out
37 $::code.=<<___ if (!$::evp);
38 andcc $ivec, 7, $ivoff
39 alignaddr $ivec, %g0, $ivec
41 ldd [$ivec + 0], %f0 ! load ivec
45 faligndata %f0, %f2, %f0
46 faligndata %f2, %f4, %f2
49 $::code.=<<___ if ($::evp);
57 prefetch [$inp + 63], 20
58 call _${alg}${bits}_load_enckey
64 sub $iright, $ileft, $iright
67 movrnz $ooff, 0, $blk_init ! if ( $out&7 ||
68 movleu $::size_t_cc, 0, $blk_init ! $len<128 ||
69 brnz,pn $blk_init, .L${bits}cbc_enc_blk ! $inp==$out)
70 srl $omask, $ooff, $omask
72 alignaddrl $out, %g0, $out
76 .L${bits}_cbc_enc_loop:
83 srlx %o1, $iright, %g1
86 srlx %o2, $iright, %o2
89 xor %g4, %o0, %o0 ! ^= rk[0]
94 fxor %f12, %f0, %f0 ! ^= ivec
96 prefetch [$out + 63], 22
97 prefetch [$inp + 16+63], 20
98 call _${alg}${bits}_encrypt_1x
106 brnz,pt $len, .L${bits}_cbc_enc_loop
109 $::code.=<<___ if ($::evp);
115 $::code.=<<___ if (!$::evp);
119 std %f0, [$ivec + 0] ! write out ivec
127 2: ldxa [$inp]0x82, %o0 ! avoid read-after-write hazard
128 ! and ~3x deterioration
130 faligndata %f0, %f0, %f4 ! handle unaligned output
131 faligndata %f0, %f2, %f6
132 faligndata %f2, %f2, %f8
134 stda %f4, [$out + $omask]0xc0 ! partial store
137 orn %g0, $omask, $omask
138 stda %f8, [$out + $omask]0xc0 ! partial store
140 brnz,pt $len, .L${bits}_cbc_enc_loop+4
141 orn %g0, $omask, $omask
143 $::code.=<<___ if ($::evp);
149 $::code.=<<___ if (!$::evp);
153 std %f0, [$ivec + 0] ! write out ivec
159 3: alignaddrl $ivec, $ivoff, %g0 ! handle unaligned ivec
161 srl $omask, $ivoff, $omask
162 faligndata %f0, %f0, %f4
163 faligndata %f0, %f2, %f6
164 faligndata %f2, %f2, %f8
165 stda %f4, [$ivec + $omask]0xc0
168 orn %g0, $omask, $omask
169 stda %f8, [$ivec + $omask]0xc0
175 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
177 .L${bits}cbc_enc_blk:
178 add $out, $len, $blk_init
179 and $blk_init, 63, $blk_init ! tail
180 sub $len, $blk_init, $len
181 add $blk_init, 15, $blk_init ! round up to 16n
183 srl $blk_init, 4, $blk_init
185 .L${bits}_cbc_enc_blk_loop:
191 sllx %o0, $ileft, %o0
192 srlx %o1, $iright, %g1
193 sllx %o1, $ileft, %o1
195 srlx %o2, $iright, %o2
198 xor %g4, %o0, %o0 ! ^= rk[0]
203 fxor %f12, %f0, %f0 ! ^= ivec
205 prefetch [$inp + 16+63], 20
206 call _${alg}${bits}_encrypt_1x
210 stda %f0, [$out]0xf2 ! ASI_BLK_INIT, T4-specific
212 stda %f2, [$out]0xf2 ! ASI_BLK_INIT, T4-specific
213 brnz,pt $len, .L${bits}_cbc_enc_blk_loop
217 brnz,pt $blk_init, .L${bits}_cbc_enc_loop
220 $::code.=<<___ if ($::evp);
226 $::code.=<<___ if (!$::evp);
230 std %f0, [$ivec + 0] ! write out ivec
236 .type ${alg}${bits}_t4_cbc_encrypt,#function
237 .size ${alg}${bits}_t4_cbc_encrypt,.-${alg}${bits}_t4_cbc_encrypt
241 sub alg_cbc_decrypt_implement {
242 my ($alg,$bits) = @_;
245 .globl ${alg}${bits}_t4_cbc_decrypt
247 ${alg}${bits}_t4_cbc_decrypt:
248 save %sp, -$::frame, %sp
249 sub $inp, $out, $blk_init ! $inp!=$out
251 $::code.=<<___ if (!$::evp);
252 andcc $ivec, 7, $ivoff
253 alignaddr $ivec, %g0, $ivec
255 ldd [$ivec + 0], %f12 ! load ivec
257 ldd [$ivec + 8], %f14
258 ldd [$ivec + 16], %f0
259 faligndata %f12, %f14, %f12
260 faligndata %f14, %f0, %f14
263 $::code.=<<___ if ($::evp);
264 ld [$ivec + 0], %f12 ! load ivec
267 ld [$ivec + 12], %f15
271 prefetch [$inp + 63], 20
272 call _${alg}${bits}_load_deckey
275 sll $ileft, 3, $ileft
278 sub $iright, $ileft, $iright
281 movrnz $ooff, 0, $blk_init ! if ( $out&7 ||
282 movleu $::size_t_cc, 0, $blk_init ! $len<128 ||
283 brnz,pn $blk_init, .L${bits}cbc_dec_blk ! $inp==$out)
284 srl $omask, $ooff, $omask
286 andcc $len, 16, %g0 ! is number of blocks even?
288 alignaddrl $out, %g0, $out
289 bz %icc, .L${bits}_cbc_dec_loop2x
291 .L${bits}_cbc_dec_loop:
297 sllx %o0, $ileft, %o0
298 srlx %o1, $iright, %g1
299 sllx %o1, $ileft, %o1
301 srlx %o2, $iright, %o2
304 xor %g4, %o0, %o2 ! ^= rk[0]
309 prefetch [$out + 63], 22
310 prefetch [$inp + 16+63], 20
311 call _${alg}${bits}_decrypt_1x
314 fxor %f12, %f0, %f0 ! ^= ivec
324 brnz,pt $len, .L${bits}_cbc_dec_loop2x
327 $::code.=<<___ if ($::evp);
331 st %f15, [$ivec + 12]
333 $::code.=<<___ if (!$::evp);
334 brnz,pn $ivoff, .L${bits}_cbc_dec_unaligned_ivec
337 std %f12, [$ivec + 0] ! write out ivec
338 std %f14, [$ivec + 8]
345 2: ldxa [$inp]0x82, %o0 ! avoid read-after-write hazard
346 ! and ~3x deterioration
348 faligndata %f0, %f0, %f4 ! handle unaligned output
349 faligndata %f0, %f2, %f6
350 faligndata %f2, %f2, %f8
352 stda %f4, [$out + $omask]0xc0 ! partial store
355 orn %g0, $omask, $omask
356 stda %f8, [$out + $omask]0xc0 ! partial store
358 brnz,pt $len, .L${bits}_cbc_dec_loop2x+4
359 orn %g0, $omask, $omask
361 $::code.=<<___ if ($::evp);
365 st %f15, [$ivec + 12]
367 $::code.=<<___ if (!$::evp);
368 brnz,pn $ivoff, .L${bits}_cbc_dec_unaligned_ivec
371 std %f12, [$ivec + 0] ! write out ivec
372 std %f14, [$ivec + 8]
378 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
380 .L${bits}_cbc_dec_loop2x:
388 sllx %o0, $ileft, %o0
389 srlx %o1, $iright, %g1
391 sllx %o1, $ileft, %o1
392 srlx %o2, $iright, %g1
394 sllx %o2, $ileft, %o2
395 srlx %o3, $iright, %g1
397 sllx %o3, $ileft, %o3
398 srlx %o4, $iright, %o4
401 xor %g4, %o0, %o4 ! ^= rk[0]
410 prefetch [$out + 63], 22
411 prefetch [$inp + 32+63], 20
412 call _${alg}${bits}_decrypt_2x
417 fxor %f12, %f0, %f0 ! ^= ivec
431 brnz,pt $len, .L${bits}_cbc_dec_loop2x
434 $::code.=<<___ if ($::evp);
438 st %f15, [$ivec + 12]
440 $::code.=<<___ if (!$::evp);
441 brnz,pn $ivoff, .L${bits}_cbc_dec_unaligned_ivec
444 std %f12, [$ivec + 0] ! write out ivec
445 std %f14, [$ivec + 8]
452 2: ldxa [$inp]0x82, %o0 ! avoid read-after-write hazard
453 ! and ~3x deterioration
455 faligndata %f0, %f0, %f8 ! handle unaligned output
456 faligndata %f0, %f2, %f0
457 faligndata %f2, %f4, %f2
458 faligndata %f4, %f6, %f4
459 faligndata %f6, %f6, %f6
460 stda %f8, [$out + $omask]0xc0 ! partial store
465 orn %g0, $omask, $omask
466 stda %f6, [$out + $omask]0xc0 ! partial store
468 brnz,pt $len, .L${bits}_cbc_dec_loop2x+4
469 orn %g0, $omask, $omask
471 $::code.=<<___ if ($::evp);
475 st %f15, [$ivec + 12]
477 $::code.=<<___ if (!$::evp);
478 brnz,pn $ivoff, .L${bits}_cbc_dec_unaligned_ivec
481 std %f12, [$ivec + 0] ! write out ivec
482 std %f14, [$ivec + 8]
487 .L${bits}_cbc_dec_unaligned_ivec:
488 alignaddrl $ivec, $ivoff, %g0 ! handle unaligned ivec
490 srl $omask, $ivoff, $omask
491 faligndata %f12, %f12, %f0
492 faligndata %f12, %f14, %f2
493 faligndata %f14, %f14, %f4
494 stda %f0, [$ivec + $omask]0xc0
497 orn %g0, $omask, $omask
498 stda %f4, [$ivec + $omask]0xc0
504 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
506 .L${bits}cbc_dec_blk:
507 add $out, $len, $blk_init
508 and $blk_init, 63, $blk_init ! tail
509 sub $len, $blk_init, $len
510 add $blk_init, 15, $blk_init ! round up to 16n
512 srl $blk_init, 4, $blk_init
514 add $blk_init, 1, $blk_init
516 .L${bits}_cbc_dec_blk_loop2x:
524 sllx %o0, $ileft, %o0
525 srlx %o1, $iright, %g1
527 sllx %o1, $ileft, %o1
528 srlx %o2, $iright, %g1
530 sllx %o2, $ileft, %o2
531 srlx %o3, $iright, %g1
533 sllx %o3, $ileft, %o3
534 srlx %o4, $iright, %o4
537 xor %g4, %o0, %o4 ! ^= rk[0]
546 prefetch [$inp + 32+63], 20
547 call _${alg}${bits}_decrypt_2x
553 fxor %f12, %f0, %f0 ! ^= ivec
560 stda %f0, [$out]0xf2 ! ASI_BLK_INIT, T4-specific
562 stda %f2, [$out]0xf2 ! ASI_BLK_INIT, T4-specific
564 stda %f4, [$out]0xf2 ! ASI_BLK_INIT, T4-specific
566 stda %f6, [$out]0xf2 ! ASI_BLK_INIT, T4-specific
567 bgu,pt $::size_t_cc, .L${bits}_cbc_dec_blk_loop2x
570 add $blk_init, $len, $len
571 andcc $len, 1, %g0 ! is number of blocks even?
573 bnz,pt %icc, .L${bits}_cbc_dec_loop
575 brnz,pn $len, .L${bits}_cbc_dec_loop2x
578 $::code.=<<___ if ($::evp);
584 $::code.=<<___ if (!$::evp);
588 std %f0, [$ivec + 0] ! write out ivec
594 .type ${alg}${bits}_t4_cbc_decrypt,#function
595 .size ${alg}${bits}_t4_cbc_decrypt,.-${alg}${bits}_t4_cbc_decrypt
599 sub alg_ctr32_implement {
600 my ($alg,$bits) = @_;
603 .globl ${alg}${bits}_t4_ctr32_encrypt
605 ${alg}${bits}_t4_ctr32_encrypt:
606 save %sp, -$::frame, %sp
609 prefetch [$inp + 63], 20
610 call _${alg}${bits}_load_enckey
613 ld [$ivec + 0], %l4 ! counter
621 xor %o5, %g4, %g4 ! ^= rk[0]
623 movxtod %g4, %f14 ! most significant 64 bits
625 sub $inp, $out, $blk_init ! $inp!=$out
628 sll $ileft, 3, $ileft
631 sub $iright, $ileft, $iright
634 movrnz $ooff, 0, $blk_init ! if ( $out&7 ||
635 movleu $::size_t_cc, 0, $blk_init ! $len<128 ||
636 brnz,pn $blk_init, .L${bits}_ctr32_blk ! $inp==$out)
637 srl $omask, $ooff, $omask
639 andcc $len, 16, %g0 ! is number of blocks even?
640 alignaddrl $out, %g0, $out
641 bz %icc, .L${bits}_ctr32_loop2x
643 .L${bits}_ctr32_loop:
649 sllx %o0, $ileft, %o0
650 srlx %o1, $iright, %g1
651 sllx %o1, $ileft, %o1
653 srlx %o2, $iright, %o2
656 xor %g5, %l7, %g1 ! ^= rk[0]
659 srl %l7, 0, %l7 ! clruw
660 prefetch [$out + 63], 22
661 prefetch [$inp + 16+63], 20
663 $::code.=<<___ if ($alg eq "aes");
664 aes_eround01 %f16, %f14, %f2, %f4
665 aes_eround23 %f18, %f14, %f2, %f2
667 $::code.=<<___ if ($alg eq "cmll");
668 camellia_f %f16, %f2, %f14, %f2
669 camellia_f %f18, %f14, %f2, %f0
672 call _${alg}${bits}_encrypt_1x+8
677 fxor %f10, %f0, %f0 ! ^= inp
685 brnz,pt $len, .L${bits}_ctr32_loop2x
692 2: ldxa [$inp]0x82, %o0 ! avoid read-after-write hazard
693 ! and ~3x deterioration
695 faligndata %f0, %f0, %f4 ! handle unaligned output
696 faligndata %f0, %f2, %f6
697 faligndata %f2, %f2, %f8
698 stda %f4, [$out + $omask]0xc0 ! partial store
701 orn %g0, $omask, $omask
702 stda %f8, [$out + $omask]0xc0 ! partial store
704 brnz,pt $len, .L${bits}_ctr32_loop2x+4
705 orn %g0, $omask, $omask
710 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
712 .L${bits}_ctr32_loop2x:
720 sllx %o0, $ileft, %o0
721 srlx %o1, $iright, %g1
723 sllx %o1, $ileft, %o1
724 srlx %o2, $iright, %g1
726 sllx %o2, $ileft, %o2
727 srlx %o3, $iright, %g1
729 sllx %o3, $ileft, %o3
730 srlx %o4, $iright, %o4
733 xor %g5, %l7, %g1 ! ^= rk[0]
736 srl %l7, 0, %l7 ! clruw
740 srl %l7, 0, %l7 ! clruw
741 prefetch [$out + 63], 22
742 prefetch [$inp + 32+63], 20
744 $::code.=<<___ if ($alg eq "aes");
745 aes_eround01 %f16, %f14, %f2, %f8
746 aes_eround23 %f18, %f14, %f2, %f2
747 aes_eround01 %f16, %f14, %f6, %f10
748 aes_eround23 %f18, %f14, %f6, %f6
750 $::code.=<<___ if ($alg eq "cmll");
751 camellia_f %f16, %f2, %f14, %f2
752 camellia_f %f16, %f6, %f14, %f6
753 camellia_f %f18, %f14, %f2, %f0
754 camellia_f %f18, %f14, %f6, %f4
757 call _${alg}${bits}_encrypt_2x+16
763 fxor %f8, %f0, %f0 ! ^= inp
776 brnz,pt $len, .L${bits}_ctr32_loop2x
783 2: ldxa [$inp]0x82, %o0 ! avoid read-after-write hazard
784 ! and ~3x deterioration
786 faligndata %f0, %f0, %f8 ! handle unaligned output
787 faligndata %f0, %f2, %f0
788 faligndata %f2, %f4, %f2
789 faligndata %f4, %f6, %f4
790 faligndata %f6, %f6, %f6
792 stda %f8, [$out + $omask]0xc0 ! partial store
797 orn %g0, $omask, $omask
798 stda %f6, [$out + $omask]0xc0 ! partial store
800 brnz,pt $len, .L${bits}_ctr32_loop2x+4
801 orn %g0, $omask, $omask
806 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
809 add $out, $len, $blk_init
810 and $blk_init, 63, $blk_init ! tail
811 sub $len, $blk_init, $len
812 add $blk_init, 15, $blk_init ! round up to 16n
814 srl $blk_init, 4, $blk_init
816 add $blk_init, 1, $blk_init
818 .L${bits}_ctr32_blk_loop2x:
826 sllx %o0, $ileft, %o0
827 srlx %o1, $iright, %g1
829 sllx %o1, $ileft, %o1
830 srlx %o2, $iright, %g1
832 sllx %o2, $ileft, %o2
833 srlx %o3, $iright, %g1
835 sllx %o3, $ileft, %o3
836 srlx %o4, $iright, %o4
839 xor %g5, %l7, %g1 ! ^= rk[0]
842 srl %l7, 0, %l7 ! clruw
846 srl %l7, 0, %l7 ! clruw
847 prefetch [$inp + 32+63], 20
849 $::code.=<<___ if ($alg eq "aes");
850 aes_eround01 %f16, %f14, %f2, %f8
851 aes_eround23 %f18, %f14, %f2, %f2
852 aes_eround01 %f16, %f14, %f6, %f10
853 aes_eround23 %f18, %f14, %f6, %f6
855 $::code.=<<___ if ($alg eq "cmll");
856 camellia_f %f16, %f2, %f14, %f2
857 camellia_f %f16, %f6, %f14, %f6
858 camellia_f %f18, %f14, %f2, %f0
859 camellia_f %f18, %f14, %f6, %f4
862 call _${alg}${bits}_encrypt_2x+16
869 fxor %f8, %f0, %f0 ! ^= inp
875 stda %f0, [$out]0xf2 ! ASI_BLK_INIT, T4-specific
877 stda %f2, [$out]0xf2 ! ASI_BLK_INIT, T4-specific
879 stda %f4, [$out]0xf2 ! ASI_BLK_INIT, T4-specific
881 stda %f6, [$out]0xf2 ! ASI_BLK_INIT, T4-specific
882 bgu,pt $::size_t_cc, .L${bits}_ctr32_blk_loop2x
885 add $blk_init, $len, $len
886 andcc $len, 1, %g0 ! is number of blocks even?
888 bnz,pt %icc, .L${bits}_ctr32_loop
890 brnz,pn $len, .L${bits}_ctr32_loop2x
895 .type ${alg}${bits}_t4_ctr32_encrypt,#function
896 .size ${alg}${bits}_t4_ctr32_encrypt,.-${alg}${bits}_t4_ctr32_encrypt
900 # Purpose of these subroutines is to explicitly encode VIS instructions,
901 # so that one can compile the module without having to specify VIS
902 # extentions on compiler command line, e.g. -xarch=v9 vs. -xarch=v9a.
903 # Idea is to reserve for option to produce "universal" binary and let
904 # programmer detect if current CPU is VIS capable at run-time.
906 my ($mnemonic,$rs1,$rs2,$rd)=@_;
908 my %visopf = ( "faligndata" => 0x048,
913 $ref = "$mnemonic\t$rs1,$rs2,$rd";
915 if ($opf=$visopf{$mnemonic}) {
916 foreach ($rs1,$rs2,$rd) {
917 return $ref if (!/%f([0-9]{1,2})/);
920 return $ref if ($1&1);
921 # re-encode for upper double register addressing
926 return sprintf ".word\t0x%08x !%s",
927 0x81b00000|$rd<<25|$rs1<<14|$opf<<5|$rs2,
934 my ($mnemonic,$rs1,$rs2,$rd)=@_;
935 my %bias = ( "g" => 0, "o" => 8, "l" => 16, "i" => 24 );
936 my $ref = "$mnemonic\t$rs1,$rs2,$rd";
937 my $opf = $mnemonic =~ /l$/ ? 0x01a :0x18;
939 foreach ($rs1,$rs2,$rd) {
940 if (/%([goli])([0-7])/) { $_=$bias{$1}+$2; }
941 else { return $ref; }
943 return sprintf ".word\t0x%08x !%s",
944 0x81b00000|$rd<<25|$rs1<<14|$opf<<5|$rs2,
948 sub unaes_round { # 4-argument instructions
949 my ($mnemonic,$rs1,$rs2,$rs3,$rd)=@_;
951 my %aesopf = ( "aes_eround01" => 0,
955 "aes_eround01_l"=> 4,
956 "aes_eround23_l"=> 5,
957 "aes_dround01_l"=> 6,
958 "aes_dround23_l"=> 7,
959 "aes_kexpand1" => 8 );
961 $ref = "$mnemonic\t$rs1,$rs2,$rs3,$rd";
963 if (defined($opf=$aesopf{$mnemonic})) {
964 $rs3 = ($rs3 =~ /%f([0-6]*[02468])/) ? (($1|$1>>5)&31) : $rs3;
965 foreach ($rs1,$rs2,$rd) {
966 return $ref if (!/%f([0-9]{1,2})/);
969 return $ref if ($1&1);
970 # re-encode for upper double register addressing
975 return sprintf ".word\t0x%08x !%s",
976 2<<30|$rd<<25|0x19<<19|$rs1<<14|$rs3<<9|$opf<<5|$rs2,
983 sub unaes_kexpand { # 3-argument instructions
984 my ($mnemonic,$rs1,$rs2,$rd)=@_;
986 my %aesopf = ( "aes_kexpand0" => 0x130,
987 "aes_kexpand2" => 0x131 );
989 $ref = "$mnemonic\t$rs1,$rs2,$rd";
991 if (defined($opf=$aesopf{$mnemonic})) {
992 foreach ($rs1,$rs2,$rd) {
993 return $ref if (!/%f([0-9]{1,2})/);
996 return $ref if ($1&1);
997 # re-encode for upper double register addressing
1002 return sprintf ".word\t0x%08x !%s",
1003 2<<30|$rd<<25|0x36<<19|$rs1<<14|$opf<<5|$rs2,
1010 sub uncamellia_f { # 4-argument instructions
1011 my ($mnemonic,$rs1,$rs2,$rs3,$rd)=@_;
1014 $ref = "$mnemonic\t$rs1,$rs2,$rs3,$rd";
1017 $rs3 = ($rs3 =~ /%f([0-6]*[02468])/) ? (($1|$1>>5)&31) : $rs3;
1018 foreach ($rs1,$rs2,$rd) {
1019 return $ref if (!/%f([0-9]{1,2})/);
1022 return $ref if ($1&1);
1023 # re-encode for upper double register addressing
1028 return sprintf ".word\t0x%08x !%s",
1029 2<<30|$rd<<25|0x19<<19|$rs1<<14|$rs3<<9|0xc<<5|$rs2,
1036 sub uncamellia3 { # 3-argument instructions
1037 my ($mnemonic,$rs1,$rs2,$rd)=@_;
1039 my %cmllopf = ( "camellia_fl" => 0x13c,
1040 "camellia_fli" => 0x13d );
1042 $ref = "$mnemonic\t$rs1,$rs2,$rd";
1044 if (defined($opf=$cmllopf{$mnemonic})) {
1045 foreach ($rs1,$rs2,$rd) {
1046 return $ref if (!/%f([0-9]{1,2})/);
1049 return $ref if ($1&1);
1050 # re-encode for upper double register addressing
1055 return sprintf ".word\t0x%08x !%s",
1056 2<<30|$rd<<25|0x36<<19|$rs1<<14|$opf<<5|$rs2,
1063 sub unmovxtox { # 2-argument instructions
1064 my ($mnemonic,$rs,$rd)=@_;
1065 my %bias = ( "g" => 0, "o" => 8, "l" => 16, "i" => 24, "f" => 0 );
1067 my %movxopf = ( "movdtox" => 0x110,
1068 "movstouw" => 0x111,
1069 "movstosw" => 0x113,
1071 "movwtos" => 0x119 );
1073 $ref = "$mnemonic\t$rs,$rd";
1075 if (defined($opf=$movxopf{$mnemonic})) {
1077 return $ref if (!/%([fgoli])([0-9]{1,2})/);
1080 return $ref if ($2&1);
1081 # re-encode for upper double register addressing
1086 return sprintf ".word\t0x%08x !%s",
1087 2<<30|$rd<<25|0x36<<19|$opf<<5|$rs,
1094 sub emit_assembler {
1095 foreach (split("\n",$::code)) {
1096 s/\`([^\`]*)\`/eval $1/ge;
1098 s/\b(f[a-z]+2[sd]*)\s+(%f[0-9]{1,2}),\s*(%f[0-9]{1,2})\s*$/$1\t%f0,$2,$3/g;
1100 s/\b(aes_[edk][^\s]*)\s+(%f[0-9]{1,2}),\s*(%f[0-9]{1,2}),\s*([%fx0-9]+),\s*(%f[0-9]{1,2})/
1101 &unaes_round($1,$2,$3,$4,$5)
1103 s/\b(aes_kexpand[02])\s+(%f[0-9]{1,2}),\s*(%f[0-9]{1,2}),\s*(%f[0-9]{1,2})/
1104 &unaes_kexpand($1,$2,$3,$4)
1106 s/\b(camellia_f)\s+(%f[0-9]{1,2}),\s*(%f[0-9]{1,2}),\s*([%fx0-9]+),\s*(%f[0-9]{1,2})/
1107 &uncamellia_f($1,$2,$3,$4,$5)
1109 s/\b(camellia_[^s]+)\s+(%f[0-9]{1,2}),\s*(%f[0-9]{1,2}),\s*(%f[0-9]{1,2})/
1110 &uncamellia3($1,$2,$3,$4)
1112 s/\b(mov[ds]to\w+)\s+(%f[0-9]{1,2}),\s*(%[goli][0-7])/
1113 &unmovxtox($1,$2,$3)
1115 s/\b(mov[xw]to[ds])\s+(%[goli][0-7]),\s*(%f[0-9]{1,2})/
1116 &unmovxtox($1,$2,$3)
1118 s/\b(f[^\s]*)\s+(%f[0-9]{1,2}),\s*(%f[0-9]{1,2}),\s*(%f[0-9]{1,2})/
1121 s/\b(alignaddr[l]*)\s+(%[goli][0-7]),\s*(%[goli][0-7]),\s*(%[goli][0-7])/
1122 &unalignaddr($1,$2,$3,$4)