3 # ====================================================================
4 # Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
5 # project. The module is, however, dual licensed under OpenSSL and
6 # CRYPTOGAMS licenses depending on where you obtain it. For further
7 # details see http://www.openssl.org/~appro/cryptogams/.
8 # ====================================================================
10 # GHASH for ARMv8 Crypto Extension, 64-bit polynomial multiplication.
14 # Initial version was developed in tight cooperation with Ard
15 # Biesheuvel <ard.biesheuvel@linaro.org> from bits-n-pieces from
16 # other assembly modules. Just like aesv8-armx.pl this module
17 # supports both AArch32 and AArch64 execution modes.
21 # Implement 2x aggregated reduction [see ghash-x86.pl for background
24 # Current performance in cycles per processed byte:
26 # PMULL[2] 32-bit NEON(*)
28 # Cortex-A53 1.01 8.39
29 # Cortex-A57 1.17 7.61
32 # (*) presented for reference/comparison purposes;
37 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
38 ( $xlate="${dir}arm-xlate.pl" and -f $xlate ) or
39 ( $xlate="${dir}../../perlasm/arm-xlate.pl" and -f $xlate) or
40 die "can't locate arm-xlate.pl";
42 open OUT,"| \"$^X\" $xlate $flavour $output";
45 $Xi="x0"; # argument block
53 my ($Xl,$Xm,$Xh,$IN)=map("q$_",(0..3));
54 my ($t0,$t1,$t2,$xC2,$H,$Hhl,$H2)=map("q$_",(8..14));
61 $code.=".arch armv8-a+crypto\n" if ($flavour =~ /64/);
62 $code.=".fpu neon\n.code 32\n" if ($flavour !~ /64/);
64 ################################################################################
65 # void gcm_init_v8(u128 Htable[16],const u64 H[2]);
67 # input: 128-bit H - secret parameter E(K,0^128)
68 # output: precomputed table filled with degrees of twisted H;
69 # H is twisted to handle reverse bitness of GHASH;
70 # only few of 16 slots of Htable[16] are used;
71 # data is opaque to outside world (which allows to
72 # optimize the code independently);
76 .type gcm_init_v8,%function
79 vld1.64 {$t1},[x1] @ load input H
81 vshl.i64 $xC2,$xC2,#57 @ 0xc2.0
85 vext.8 $t0,$t2,$xC2,#8 @ t0=0xc2....01
87 vshr.s32 $t1,$t1,#31 @ broadcast carry bit
92 vorr $IN,$IN,$t2 @ H<<<=1
93 veor $H,$IN,$t0 @ twisted H
94 vst1.64 {$H},[x0],#16 @ store Htable[0]
97 vext.8 $t0,$H,$H,#8 @ Karatsuba pre-processing
100 vpmull2.p64 $Xh,$H,$H
101 vpmull.p64 $Xm,$t0,$t0
103 vext.8 $t1,$Xl,$Xh,#8 @ Karatsuba post-processing
107 vpmull.p64 $t2,$Xl,$xC2 @ 1st phase
109 vmov $Xh#lo,$Xm#hi @ Xh|Xm - 256-bit result
110 vmov $Xm#hi,$Xl#lo @ Xm is rotated Xl
113 vext.8 $t2,$Xl,$Xl,#8 @ 2nd phase
114 vpmull.p64 $Xl,$Xl,$xC2
118 vext.8 $t1,$H2,$H2,#8 @ Karatsuba pre-processing
120 vext.8 $Hhl,$t0,$t1,#8 @ pack Karatsuba pre-processed
121 vst1.64 {$Hhl-$H2},[x0] @ store Htable[1..2]
124 .size gcm_init_v8,.-gcm_init_v8
126 ################################################################################
127 # void gcm_gmult_v8(u64 Xi[2],const u128 Htable[16]);
129 # input: Xi - current hash value;
130 # Htable - table precomputed in gcm_init_v8;
131 # output: Xi - next hash value Xi;
135 .type gcm_gmult_v8,%function
138 vld1.64 {$t1},[$Xi] @ load Xi
140 vld1.64 {$H-$Hhl},[$Htbl] @ load twisted H, ...
141 vshl.u64 $xC2,$xC2,#57
145 vext.8 $IN,$t1,$t1,#8
147 vpmull.p64 $Xl,$H,$IN @ H.lo·Xi.lo
148 veor $t1,$t1,$IN @ Karatsuba pre-processing
149 vpmull2.p64 $Xh,$H,$IN @ H.hi·Xi.hi
150 vpmull.p64 $Xm,$Hhl,$t1 @ (H.lo+H.hi)·(Xi.lo+Xi.hi)
152 vext.8 $t1,$Xl,$Xh,#8 @ Karatsuba post-processing
156 vpmull.p64 $t2,$Xl,$xC2 @ 1st phase of reduction
158 vmov $Xh#lo,$Xm#hi @ Xh|Xm - 256-bit result
159 vmov $Xm#hi,$Xl#lo @ Xm is rotated Xl
162 vext.8 $t2,$Xl,$Xl,#8 @ 2nd phase of reduction
163 vpmull.p64 $Xl,$Xl,$xC2
170 vext.8 $Xl,$Xl,$Xl,#8
171 vst1.64 {$Xl},[$Xi] @ write out Xi
174 .size gcm_gmult_v8,.-gcm_gmult_v8
176 ################################################################################
177 # void gcm_ghash_v8(u64 Xi[2],const u128 Htable[16],const u8 *inp,size_t len);
179 # input: table precomputed in gcm_init_v8;
180 # current hash value Xi;
181 # pointer to input data;
182 # length of input data in bytes, but divisible by block size;
183 # output: next hash value Xi;
187 .type gcm_ghash_v8,%function
191 $code.=<<___ if ($flavour !~ /64/);
192 vstmdb sp!,{d8-d15} @ 32-bit ABI says so
195 vld1.64 {$Xl},[$Xi] @ load [rotated] Xi
196 @ "[rotated]" means that
197 @ loaded value would have
198 @ to be rotated in order to
199 @ make it appear as in
200 @ alorithm specification
201 subs $len,$len,#32 @ see if $len is 32 or larger
202 mov $inc,#16 @ $inc is used as post-
203 @ increment for input pointer;
204 @ as loop is modulo-scheduled
205 @ $inc is zeroed just in time
206 @ to preclude oversteping
207 @ inp[len], which means that
208 @ last block[s] are actually
209 @ loaded twice, but last
210 @ copy is not processed
211 vld1.64 {$H-$Hhl},[$Htbl],#32 @ load twisted H, ..., H^2
213 vld1.64 {$H2},[$Htbl]
214 cclr $inc,eq @ is it time to zero $inc?
215 vext.8 $Xl,$Xl,$Xl,#8 @ rotate Xi
216 vld1.64 {$t0},[$inp],#16 @ load [rotated] I[0]
217 vshl.u64 $xC2,$xC2,#57 @ compose 0xc2.0 constant
222 vext.8 $IN,$t0,$t0,#8 @ rotate I[0]
223 b.lo .Lodd_tail_v8 @ $len was less than 32
225 { my ($Xln,$Xmn,$Xhn,$In) = map("q$_",(4..7));
227 # Xi+2 =[H*(Ii+1 + Xi+1)] mod P =
228 # [(H*Ii+1) + (H*Xi+1)] mod P =
229 # [(H*Ii+1) + H^2*(Ii+Xi)] mod P
232 vld1.64 {$t1},[$inp],$inc @ load [rotated] I[1]
236 vext.8 $In,$t1,$t1,#8
237 veor $IN,$IN,$Xl @ I[i]^=Xi
238 vpmull.p64 $Xln,$H,$In @ H·Ii+1
239 veor $t1,$t1,$In @ Karatsuba pre-processing
240 vpmull2.p64 $Xhn,$H,$In
245 vext.8 $t2,$IN,$IN,#8
246 subs $len,$len,#32 @ is there more data?
247 vpmull.p64 $Xl,$H2,$IN @ H^2.lo·Xi.lo
248 cclr $inc,lo @ is it time to zero $inc?
250 vpmull.p64 $Xmn,$Hhl,$t1
251 veor $t2,$t2,$IN @ Karatsuba pre-processing
252 vpmull2.p64 $Xh,$H2,$IN @ H^2.hi·Xi.hi
253 veor $Xl,$Xl,$Xln @ accumulate
254 vpmull2.p64 $Xm,$Hhl,$t2 @ (H^2.lo+H^2.hi)·(Xi.lo+Xi.hi)
255 vld1.64 {$t0},[$inp],$inc @ load [rotated] I[i+2]
258 cclr $inc,eq @ is it time to zero $inc?
261 vext.8 $t1,$Xl,$Xh,#8 @ Karatsuba post-processing
264 vld1.64 {$t1},[$inp],$inc @ load [rotated] I[i+3]
269 vpmull.p64 $t2,$Xl,$xC2 @ 1st phase of reduction
274 vmov $Xh#lo,$Xm#hi @ Xh|Xm - 256-bit result
275 vmov $Xm#hi,$Xl#lo @ Xm is rotated Xl
276 vext.8 $In,$t1,$t1,#8
277 vext.8 $IN,$t0,$t0,#8
279 vpmull.p64 $Xln,$H,$In @ H·Ii+1
280 veor $IN,$IN,$Xh @ accumulate $IN early
282 vext.8 $t2,$Xl,$Xl,#8 @ 2nd phase of reduction
283 vpmull.p64 $Xl,$Xl,$xC2
285 veor $t1,$t1,$In @ Karatsuba pre-processing
287 vpmull2.p64 $Xhn,$H,$In
288 b.hs .Loop_mod2x_v8 @ there was at least 32 more bytes
291 vext.8 $IN,$t0,$t0,#8 @ re-construct $IN
292 adds $len,$len,#32 @ re-construct $len
293 veor $Xl,$Xl,$Xh @ re-construct $Xl
294 b.eq .Ldone_v8 @ is $len zero?
299 vext.8 $t2,$Xl,$Xl,#8
300 veor $IN,$IN,$Xl @ inp^=Xi
301 veor $t1,$t0,$t2 @ $t1 is rotated inp^Xi
303 vpmull.p64 $Xl,$H,$IN @ H.lo·Xi.lo
304 veor $t1,$t1,$IN @ Karatsuba pre-processing
305 vpmull2.p64 $Xh,$H,$IN @ H.hi·Xi.hi
306 vpmull.p64 $Xm,$Hhl,$t1 @ (H.lo+H.hi)·(Xi.lo+Xi.hi)
308 vext.8 $t1,$Xl,$Xh,#8 @ Karatsuba post-processing
312 vpmull.p64 $t2,$Xl,$xC2 @ 1st phase of reduction
314 vmov $Xh#lo,$Xm#hi @ Xh|Xm - 256-bit result
315 vmov $Xm#hi,$Xl#lo @ Xm is rotated Xl
318 vext.8 $t2,$Xl,$Xl,#8 @ 2nd phase of reduction
319 vpmull.p64 $Xl,$Xl,$xC2
327 vext.8 $Xl,$Xl,$Xl,#8
328 vst1.64 {$Xl},[$Xi] @ write out Xi
331 $code.=<<___ if ($flavour !~ /64/);
332 vldmia sp!,{d8-d15} @ 32-bit ABI says so
336 .size gcm_ghash_v8,.-gcm_ghash_v8
340 .asciz "GHASH for ARMv8, CRYPTOGAMS by <appro\@openssl.org>"
344 if ($flavour =~ /64/) { ######## 64-bit code
348 $arg =~ m/q([0-9]+)#(lo|hi),\s*q([0-9]+)#(lo|hi)/o &&
349 sprintf "ins v%d.d[%d],v%d.d[%d]",$1,($2 eq "lo")?0:1,$3,($4 eq "lo")?0:1;
351 foreach(split("\n",$code)) {
352 s/cclr\s+([wx])([^,]+),\s*([a-z]+)/csel $1$2,$1zr,$1$2,$3/o or
353 s/vmov\.i8/movi/o or # fix up legacy mnemonics
354 s/vmov\s+(.*)/unvmov($1)/geo or
356 s/vshr\.s/sshr\.s/o or
358 s/^(\s+)v/$1/o or # strip off v prefix
361 s/\bq([0-9]+)\b/"v".($1<8?$1:$1+8).".16b"/geo; # old->new registers
362 s/@\s/\/\//o; # old->new style commentary
364 # fix up remainig legacy suffixes
366 s/\.[uis]?32//o and s/\.16b/\.4s/go;
367 m/\.p64/o and s/\.16b/\.1q/o; # 1st pmull argument
368 m/l\.p64/o and s/\.16b/\.1d/go; # 2nd and 3rd pmull arguments
369 s/\.[uisp]?64//o and s/\.16b/\.2d/go;
370 s/\.[42]([sd])\[([0-3])\]/\.$1\[$2\]/o;
374 } else { ######## 32-bit code
378 $arg =~ m/q([0-9]+),\s*q([0-9]+)\[([0-3])\]/o &&
379 sprintf "vdup.32 q%d,d%d[%d]",$1,2*$2+($3>>1),$3&1;
382 my ($mnemonic,$arg)=@_;
384 if ($arg =~ m/q([0-9]+),\s*q([0-9]+),\s*q([0-9]+)/o) {
385 my $word = 0xf2a00e00|(($1&7)<<13)|(($1&8)<<19)
386 |(($2&7)<<17)|(($2&8)<<4)
387 |(($3&7)<<1) |(($3&8)<<2);
388 $word |= 0x00010001 if ($mnemonic =~ "2");
389 # since ARMv7 instructions are always encoded little-endian.
390 # correct solution is to use .inst directive, but older
391 # assemblers don't implement it:-(
392 sprintf ".byte\t0x%02x,0x%02x,0x%02x,0x%02x\t@ %s %s",
393 $word&0xff,($word>>8)&0xff,
394 ($word>>16)&0xff,($word>>24)&0xff,
399 foreach(split("\n",$code)) {
400 s/\b[wx]([0-9]+)\b/r$1/go; # new->old registers
401 s/\bv([0-9])\.[12468]+[bsd]\b/q$1/go; # new->old registers
402 s/\/\/\s?/@ /o; # new->old style commentary
404 # fix up remainig new-style suffixes
407 s/cclr\s+([^,]+),\s*([a-z]+)/mov$2 $1,#0/o or
408 s/vdup\.32\s+(.*)/unvdup32($1)/geo or
409 s/v?(pmull2?)\.p64\s+(.*)/unvpmullp64($1,$2)/geo or
410 s/\bq([0-9]+)#(lo|hi)/sprintf "d%d",2*$1+($2 eq "hi")/geo or
412 s/^(\s+)ret/$1bx\tlr/o;
418 close STDOUT; # enforce flush