x86[_64]cpuid.pl: harmonize usage of reserved bits #20 and #30.

[openssl.git] / doc / crypto / OPENSSL_ia32cap.pod

diff --git a/doc/crypto/OPENSSL_ia32cap.pod b/doc/crypto/OPENSSL_ia32cap.pod
index af6b4f3a4d1d87fa4a16ef76c84c4cd8abb0b8e9..3f6458c6bd1e2cfbf6b74421de4622ce09117e36 100644 (file)
--- a/doc/crypto/OPENSSL_ia32cap.pod
+++ b/doc/crypto/OPENSSL_ia32cap.pod
@@ -37,14 +37,13 @@ moment of this writing following bits are significant:
 =item bit #28 denoting Hyperthreading, which is used to distiguish
       cores with shared cache;
 
-=item bit #30, reserved by Intel, is used to choose among RC4 code
-      paths;
+=item bit #30, reserved by Intel, denotes specifically Intel CPUs;
 
 =item bit #33 denoting availability of PCLMULQDQ instruction;
 
 =item bit #41 denoting SSSE3, Supplemental SSE3, support;
 
-=item bit #43 denoting AMD XOP support (forced to zero on Intel);
+=item bit #43 denoting AMD XOP support (forced to zero on non-AMD CPUs);
 
 =item bit #57 denoting AES-NI instruction set extension;