3 # ====================================================================
4 # Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
5 # project. The module is, however, dual licensed under OpenSSL and
6 # CRYPTOGAMS licenses depending on where you obtain it. For further
7 # details see http://www.openssl.org/~appro/cryptogams/.
8 # ====================================================================
12 # Provided that UltraSPARC VIS instructions are pipe-lined(*) and
13 # pairable(*) with IALU ones, offloading of Xupdate to the UltraSPARC
14 # Graphic Unit would make it possible to achieve higher instruction-
15 # level parallelism, ILP, and thus higher performance. It should be
16 # explicitly noted that ILP is the keyword, and it means that this
17 # code would be unsuitable for cores like UltraSPARC-Tx. The idea is
18 # not really novel, Sun had VIS-powered implementation for a while.
19 # Unlike Sun's implementation this one can process multiple unaligned
20 # input blocks, and as such works as drop-in replacement for OpenSSL
21 # sha1_block_data_order. Performance improvement was measured to be
22 # 40% over pure IALU sha1-sparcv9.pl on UltraSPARC-IIi, but 12% on
23 # UltraSPARC-III. See below for discussion...
25 # (*) "Pipe-lined" means that even if it takes several cycles to
26 # complete, next instruction using same functional unit [but not
27 # depending on the result of the current instruction] can start
28 # execution without having to wait for the unit. "Pairable"
29 # means that two [or more] independent instructions can be
30 # issued at the very same time.
33 for (@ARGV) { $bits=64 if (/\-m64/ || /\-xarch\=v9/); }
34 if ($bits==64) { $bias=2047; $frame=192; }
35 else { $bias=0; $frame=112; }
38 open STDOUT,">$output";
72 @VK=($VK_00_19,$VK_20_39,$VK_40_59,$VK_60_79);
73 @X=("%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
74 "%f8", "%f9","%f10","%f11","%f12","%f13","%f14","%f15","%f16");
76 # This is reference 2x-parallelized VIS-powered Xupdate procedure. It
77 # covers even K_NN_MM addition...
80 my $K=@VK[($i+16)/20];
83 # [ provided that GSR.alignaddr_offset is 5, $mul contains
84 # 0x100ULL<<32|0x100 value and K_NN_MM are pre-loaded to
85 # chosen registers... ]
87 fxors @X[($j+13)%16],@X[$j],@X[$j] !-1/-1/-1:X[0]^=X[13]
88 fxors @X[($j+14)%16],@X[$j+1],@X[$j+1]! 0/ 0/ 0:X[1]^=X[14]
89 fxor @X[($j+2)%16],@X[($j+8)%16],%f18! 1/ 1/ 1:Tmp=X[2,3]^X[8,9]
90 fxor %f18,@X[$j],@X[$j] ! 2/ 4/ 3:X[0,1]^=X[2,3]^X[8,9]
91 faligndata @X[$j],@X[$j],%f18 ! 3/ 7/ 5:Tmp=X[0,1]>>>24
92 fpadd32 @X[$j],@X[$j],@X[$j] ! 4/ 8/ 6:X[0,1]<<=1
93 fmul8ulx16 %f18,$fmul,%f18 ! 5/10/ 7:Tmp>>=7, Tmp&=1
95 for %f18,@X[$j],@X[$j] ! 8/14/10:X[0,1]|=Tmp
96 ![fxors %f0,%f3,%f3] !10/17/12:X[0] dependency
97 fpadd32 $K,@X[$j],%f20
98 std %f20,[$Xfer+`4*$j`]
100 # The numbers delimited with slash are the earliest possible dispatch
101 # cycles for given instruction assuming 1 cycle latency for simple VIS
102 # instructions, such as on UltraSPARC-I&II, 3 cycles latency, such as
103 # on UltraSPARC-III&IV, and 2 cycles latency, such as on SPARC64-V[?],
104 # respectively. Being 2x-parallelized the procedure is "worth" 5, 8.5
105 # or 6 ticks per SHA1 round. As FPU/VIS instructions are perfectly
106 # pairable with IALU ones, the round timing is defined by the maximum
107 # between VIS and IALU timings. The latter varies from round to round
108 # and averages out at 6.25 ticks. This means that USI&II and SPARC64-V
109 # should operate at IALU rate, while USIII&IV - at VIS rate. This
110 # explains why performance improvement varies among processors. Well,
111 # it should be noted that pure IALU sha1-sparcv9.pl module exhibits
112 # virtually uniform performance of ~9.3 cycles per SHA1 round. Timings
113 # mentioned above are theoretical lower limits. Real-life performance
114 # was measured to be 6.6 cycles per SHA1 round on USIIi and 8.3 on
115 # USIII. The latter means that processor manual must have an error in
116 # instruction latency table or there is some unmentioned shortcut...
119 # The reference Xupdate procedure is then "strained" over *pairs* of
120 # BODY_NN_MM and kind of modulo-scheduled in respect to X[n]^=X[n+13]
121 # and K_NN_MM addition. It's "running" 15 rounds ahead, which leaves
122 # plenty of room to amortize for read-after-write hazard, as well as
123 # to fetch and align input for the next spin. The VIS instructions are
124 # scheduled for latency of 2 cycles, because there are not enough IALU
125 # instructions to schedule for latency of 3, while scheduling for 1
126 # would give no gain on USI&II, but loss on SPARC64-V.
129 my ($i,$a,$b,$c,$d,$e)=@_;
131 my $k=($j+16+2)%16; # ahead reference
132 my $l=($j+16-2)%16; # behind reference
133 my $K=@VK[($j+16-2)/20];
137 $code.=<<___ if (!($i&1));
140 ld [$Xfer+`4*($i%16)`],$Xi
141 fxors @X[($j+14)%16],@X[$j+1],@X[$j+1]! 0/ 0/ 0:X[1]^=X[14]
144 fxor @X[($j+2)%16],@X[($j+8)%16],%f18! 1/ 1/ 1:Tmp=X[2,3]^X[8,9]
149 fxor %f18,@X[$j],@X[$j] ! 2/ 4/ 3:X[0,1]^=X[2,3]^X[8,9]
154 faligndata @X[$j],@X[$j],%f18 ! 3/ 7/ 5:Tmp=X[0,1]>>>24
156 $code.=<<___ if ($i&1);
159 ld [$Xfer+`4*($i%16)`],$Xi
160 fpadd32 @X[$j],@X[$j],@X[$j] ! 4/ 8/ 6:X[0,1]<<=1
163 fmul8ulx16 %f18,$fmul,%f18 ! 5/10/ 7:Tmp>>=7, Tmp&=1
166 fpadd32 $K,@X[$l],%f20 !
169 fxors @X[($k+13)%16],@X[$k],@X[$k] !-1/-1/-1:X[0]^=X[13]
172 fxor %f18,@X[$j],@X[$j] ! 8/14/10:X[0,1]|=Tmp
176 $code.=<<___ if ($i&1 && $i>=2);
177 std %f20,[$Xfer+`4*$l`] !
182 my ($i,$a,$b,$c,$d,$e)=@_;
184 my $k=($j+16+2)%16; # ahead reference
185 my $l=($j+16-2)%16; # behind reference
186 my $K=@VK[($j+16-2)/20];
190 $code.=<<___ if (!($i&1) && $i<64);
192 ld [$Xfer+`4*($i%16)`],$Xi
193 fxors @X[($j+14)%16],@X[$j+1],@X[$j+1]! 0/ 0/ 0:X[1]^=X[14]
196 fxor @X[($j+2)%16],@X[($j+8)%16],%f18! 1/ 1/ 1:Tmp=X[2,3]^X[8,9]
201 fxor %f18,@X[$j],@X[$j] ! 2/ 4/ 3:X[0,1]^=X[2,3]^X[8,9]
206 faligndata @X[$j],@X[$j],%f18 ! 3/ 7/ 5:Tmp=X[0,1]>>>24
208 $code.=<<___ if ($i&1 && $i<64);
210 ld [$Xfer+`4*($i%16)`],$Xi
211 fpadd32 @X[$j],@X[$j],@X[$j] ! 4/ 8/ 6:X[0,1]<<=1
214 fmul8ulx16 %f18,$fmul,%f18 ! 5/10/ 7:Tmp>>=7, Tmp&=1
217 fpadd32 $K,@X[$l],%f20 !
220 fxors @X[($k+13)%16],@X[$k],@X[$k] !-1/-1/-1:X[0]^=X[13]
223 fxor %f18,@X[$j],@X[$j] ! 8/14/10:X[0,1]|=Tmp
226 std %f20,[$Xfer+`4*$l`] !
228 $code.=<<___ if ($i==64);
230 ld [$Xfer+`4*($i%16)`],$Xi
231 fpadd32 $K,@X[$l],%f20
238 std %f20,[$Xfer+`4*$l`]
244 $code.=<<___ if ($i>64);
246 ld [$Xfer+`4*($i%16)`],$Xi
261 my ($i,$a,$b,$c,$d,$e)=@_;
263 my $k=($j+16+2)%16; # ahead reference
264 my $l=($j+16-2)%16; # behind reference
265 my $K=@VK[($j+16-2)/20];
269 $code.=<<___ if (!($i&1));
271 ld [$Xfer+`4*($i%16)`],$Xi
272 fxors @X[($j+14)%16],@X[$j+1],@X[$j+1]! 0/ 0/ 0:X[1]^=X[14]
275 fxor @X[($j+2)%16],@X[($j+8)%16],%f18! 1/ 1/ 1:Tmp=X[2,3]^X[8,9]
280 fxor %f18,@X[$j],@X[$j] ! 2/ 4/ 3:X[0,1]^=X[2,3]^X[8,9]
285 faligndata @X[$j],@X[$j],%f18 ! 3/ 7/ 5:Tmp=X[0,1]>>>24
288 fpadd32 @X[$j],@X[$j],@X[$j] ! 4/ 8/ 6:X[0,1]<<=1
290 $code.=<<___ if ($i&1);
292 ld [$Xfer+`4*($i%16)`],$Xi
295 fmul8ulx16 %f18,$fmul,%f18 ! 5/10/ 7:Tmp>>=7, Tmp&=1
298 fpadd32 $K,@X[$l],%f20 !
301 fxors @X[($k+13)%16],@X[$k],@X[$k] !-1/-1/-1:X[0]^=X[13]
304 fxor %f18,@X[$j],@X[$j] ! 8/14/10:X[0,1]|=Tmp
309 std %f20,[$Xfer+`4*$l`] !
313 # If there is more data to process, then we pre-fetch the data for
314 # next iteration in last ten rounds...
316 my ($i,$a,$b,$c,$d,$e)=@_;
322 $code.=<<___ if ($i==70);
324 ld [$Xfer+`4*($i%16)`],$Xi
339 and $nXfer,255,$nXfer
340 alignaddr %g0,$align,%g0
341 add $base,$nXfer,$nXfer
343 $code.=<<___ if ($i==71);
345 ld [$Xfer+`4*($i%16)`],$Xi
357 $code.=<<___ if ($i>=72);
358 faligndata @X[$m],@X[$m+2],@X[$m]
360 ld [$Xfer+`4*($i%16)`],$Xi
365 fpadd32 $VK_00_19,@X[$m],%f20
373 $code.=<<___ if ($i<77);
374 ldd [$inp+`8*($i+1-70)`],@X[2*($i+1-70)]
376 $code.=<<___ if ($i==77); # redundant if $inp was aligned
379 ldd [$inp+$tmp0],@X[16]
381 $code.=<<___ if ($i>=72);
382 std %f20,[$nXfer+`4*$m`]
387 .section ".text",#alloc,#execinstr
391 .long 0x5a827999,0x5a827999 ! K_00_19
392 .long 0x6ed9eba1,0x6ed9eba1 ! K_20_39
393 .long 0x8f1bbcdc,0x8f1bbcdc ! K_40_59
394 .long 0xca62c1d6,0xca62c1d6 ! K_60_79
395 .long 0x00000100,0x00000100
397 .type vis_const,#object
398 .size vis_const,(.-vis_const)
400 ldd [$tmp0+0],$VK_00_19
401 ldd [$tmp0+8],$VK_20_39
402 ldd [$tmp0+16],$VK_40_59
403 ldd [$tmp0+24],$VK_60_79
406 .type load_vis_const,#function
407 .size load_vis_const,(.-load_vis_const)
410 .globl sha1_block_data_order
411 sha1_block_data_order:
413 add %fp,$bias-256,$base
415 1: call load_vis_const
416 sub %o7,1b-vis_const,$tmp0
421 sub $base,$bias+$frame,%sp
428 # X[16] is maintained in FP register bank
429 alignaddr %g0,$align,%g0
437 add $base,$Xfer,$Xfer
441 brz,pt $align,.Laligned
445 faligndata @X[0],@X[2],@X[0]
446 faligndata @X[2],@X[4],@X[2]
447 faligndata @X[4],@X[6],@X[4]
448 faligndata @X[6],@X[8],@X[6]
449 faligndata @X[8],@X[10],@X[8]
450 faligndata @X[10],@X[12],@X[10]
451 faligndata @X[12],@X[14],@X[12]
452 faligndata @X[14],@X[16],@X[14]
457 alignaddr %g0,$tmp0,%g0
458 fpadd32 $VK_00_19,@X[0],%f16
459 fpadd32 $VK_00_19,@X[2],%f18
460 fpadd32 $VK_00_19,@X[4],%f20
461 fpadd32 $VK_00_19,@X[6],%f22
462 fpadd32 $VK_00_19,@X[8],%f24
463 fpadd32 $VK_00_19,@X[10],%f26
464 fpadd32 $VK_00_19,@X[12],%f28
465 fpadd32 $VK_00_19,@X[14],%f30
477 fxors @X[13],@X[0],@X[0]
484 for ($i=0;$i<20;$i++) { &BODY_00_19($i,@V); unshift(@V,pop(@V)); }
485 for (;$i<40;$i++) { &BODY_20_39($i,@V); unshift(@V,pop(@V)); }
486 for (;$i<60;$i++) { &BODY_40_59($i,@V); unshift(@V,pop(@V)); }
487 for (;$i<70;$i++) { &BODY_20_39($i,@V); unshift(@V,pop(@V)); }
492 for (;$i<80;$i++) { &BODY_70_79($i,@V); unshift(@V,pop(@V)); }
500 fxors @X[13],@X[0],@X[0]
506 alignaddr %g0,$tmp0,%g0
514 for($i=70;$i<80;$i++) { &BODY_20_39($i,@V); unshift(@V,pop(@V)); }
530 .type sha1_block_data_order,#function
531 .size sha1_block_data_order,(.-sha1_block_data_order)
532 .asciz "SHA1 block transform for SPARCv9a, CRYPTOGAMS by <appro\@openssl.org>"
535 # Purpose of these subroutines is to explicitly encode VIS instructions,
536 # so that one can compile the module without having to specify VIS
537 # extentions on compiler command line, e.g. -xarch=v9 vs. -xarch=v9a.
538 # Idea is to reserve for option to produce "universal" binary and let
539 # programmer detect if current CPU is VIS capable at run-time.
541 my ($mnemonic,$rs1,$rs2,$rd)=@_;
543 my %visopf = ( "fmul8ulx16" => 0x037,
544 "faligndata" => 0x048,
549 $ref = "$mnemonic\t$rs1,$rs2,$rd";
551 if ($opf=$visopf{$mnemonic}) {
552 foreach ($rs1,$rs2,$rd) {
553 return $ref if (!/%f([0-9]{1,2})/);
556 return $ref if ($1&1);
557 # re-encode for upper double register addressing
562 return sprintf ".word\t0x%08x !%s",
563 0x81b00000|$rd<<25|$rs1<<14|$opf<<5|$rs2,
570 my ($mnemonic,$rs1,$rs2,$rd)=@_;
571 my %bias = ( "g" => 0, "o" => 8, "l" => 16, "i" => 24 );
572 my $ref="$mnemonic\t$rs1,$rs2,$rd";
574 foreach ($rs1,$rs2,$rd) {
575 if (/%([goli])([0-7])/) { $_=$bias{$1}+$2; }
576 else { return $ref; }
578 return sprintf ".word\t0x%08x !%s",
579 0x81b00300|$rd<<25|$rs1<<14|$rs2,
583 $code =~ s/\`([^\`]*)\`/eval $1/gem;
584 $code =~ s/\b(f[^\s]*)\s+(%f[0-9]{1,2}),(%f[0-9]{1,2}),(%f[0-9]{1,2})/
587 $code =~ s/\b(alignaddr)\s+(%[goli][0-7]),(%[goli][0-7]),(%[goli][0-7])/
588 &unalignaddr($1,$2,$3,$4)