3 # ====================================================================
4 # Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
5 # project. The module is, however, dual licensed under OpenSSL and
6 # CRYPTOGAMS licenses depending on where you obtain it. For further
7 # details see http://www.openssl.org/~appro/cryptogams/.
9 # Hardware SPARC T4 support by David S. Miller <davem@davemloft.net>.
10 # ====================================================================
12 # MD5 for SPARCv9, 6.9 cycles per byte on UltraSPARC, >40% faster than
13 # code generated by Sun C 5.2.
15 # SPARC T4 MD5 hardware achieves 3.24 cycles per byte, which is 2.1x
16 # faster than software. Multi-process benchmark saturates at 12x
17 # single-process result on 8-core processor, or ~11GBps per 2.85GHz
21 for (@ARGV) { $bits=64 if (/\-m64/ || /\-xarch\=v9/); }
22 if ($bits==64) { $bias=2047; $frame=192; }
23 else { $bias=0; $frame=112; }
26 open STDOUT,">$output";
30 ($ctx,$inp,$len)=("%i0","%i1","%i2"); # input arguments
33 @X=("%o0","%o1","%o2","%o3","%o4","%o5","%o7","%g1","%g2");
35 ($AB,$CD)=("%g4","%g5");
38 @V=($A,$B,$C,$D)=map("%l$_",(0..3));
39 ($t1,$t2,$t3,$saved_asi)=map("%l$_",(4..7));
40 ($shr,$shl1,$shl2)=("%i3","%i4","%i5");
42 my @K=( 0xd76aa478,0xe8c7b756,0x242070db,0xc1bdceee,
43 0xf57c0faf,0x4787c62a,0xa8304613,0xfd469501,
44 0x698098d8,0x8b44f7af,0xffff5bb1,0x895cd7be,
45 0x6b901122,0xfd987193,0xa679438e,0x49b40821,
47 0xf61e2562,0xc040b340,0x265e5a51,0xe9b6c7aa,
48 0xd62f105d,0x02441453,0xd8a1e681,0xe7d3fbc8,
49 0x21e1cde6,0xc33707d6,0xf4d50d87,0x455a14ed,
50 0xa9e3e905,0xfcefa3f8,0x676f02d9,0x8d2a4c8a,
52 0xfffa3942,0x8771f681,0x6d9d6122,0xfde5380c,
53 0xa4beea44,0x4bdecfa9,0xf6bb4b60,0xbebfbc70,
54 0x289b7ec6,0xeaa127fa,0xd4ef3085,0x04881d05,
55 0xd9d4d039,0xe6db99e5,0x1fa27cf8,0xc4ac5665,
57 0xf4292244,0x432aff97,0xab9423a7,0xfc93a039,
58 0x655b59c3,0x8f0ccc92,0xffeff47d,0x85845dd1,
59 0x6fa87e4f,0xfe2ce6e0,0xa3014314,0x4e0811a1,
60 0xf7537e82,0xbd3af235,0x2ad7d2bb,0xeb86d391, 0 );
63 my ($i,$a,$b,$c,$d) = @_;
64 my $rot = (7,12,17,22)[$i%4];
69 srlx @X[$j],$shr,@X[$j] ! align X[`$i+1`]
70 and $b,$t1,$t1 ! round $i
71 sllx @X[$j+1],$shl1,$tx
76 sethi %hi(@K[$i+1]),$t2
78 or $t2,%lo(@K[$i+1]),$t2
80 add @X[$j],$t2,$t2 ! X[`$i+1`]+K[`$i+1`]
88 srlx @X[$j],32,$tx ! extract X[`2*$j+1`]
89 and $b,$t1,$t1 ! round $i
92 sethi %hi(@K[$i+1]),$t2
94 or $t2,%lo(@K[$i+1]),$t2
96 add $tx,$t2,$t2 ! X[`2*$j+1`]+K[`$i+1`]
106 my ($i,$a,$b,$c,$d) = @_;
107 my $rot = (7,12,17,22)[$i%4];
110 srlx @X[0],32,$tx ! extract X[1]
111 and $b,$t1,$t1 ! round $i
114 sethi %hi(@K[$i+1]),$t2
116 or $t2,%lo(@K[$i+1]),$t2
118 add $tx,$t2,$t2 ! X[1]+K[`$i+1`]
127 my ($i,$a,$b,$c,$d) = @_;
128 my $rot = (5,9,14,20)[$i%4];
129 my $j = $i<31 ? (1+5*($i+1))%16 : (5+3*($i+1))%16;
132 $code.=<<___ if ($j&1 && ($xi=$tx));
133 srlx @X[$j/2],32,$xi ! extract X[$j]
136 and $b,$d,$t3 ! round $i
139 sethi %hi(@K[$i+1]),$t2
141 or $t2,%lo(@K[$i+1]),$t2
143 add $xi,$t2,$t2 ! X[$j]+K[`$i+1`]
146 `$i<31?"andn":"xor"` $b,$c,$t1
152 my ($i,$a,$b,$c,$d) = @_;
153 my $rot = (4,11,16,23)[$i%4];
154 my $j = $i<47 ? (5+3*($i+1))%16 : (0+7*($i+1))%16;
157 $code.=<<___ if ($j&1 && ($xi=$tx));
158 srlx @X[$j/2],32,$xi ! extract X[$j]
161 add $t2,$a,$a ! round $i
163 sethi %hi(@K[$i+1]),$t2
165 or $t2,%lo(@K[$i+1]),$t2
167 add $xi,$t2,$t2 ! X[$j]+K[`$i+1`]
176 my ($i,$a,$b,$c,$d) = @_;
177 my $rot = (6,10,15,21)[$i%4];
178 my $j = (0+7*($i+1))%16;
182 add $t2,$a,$a ! round $i
184 $code.=<<___ if ($j&1 && ($xi=$tx));
185 srlx @X[$j/2],32,$xi ! extract X[$j]
189 sethi %hi(@K[$i+1]),$t2
191 or $t2,%lo(@K[$i+1]),$t2
194 add $xi,$t2,$t2 ! X[$j]+K[`$i+1`]
201 $code.=<<___ if ($bits==64);
202 .register %g2,#scratch
203 .register %g3,#scratch
206 #include "sparc_arch.h"
208 .section ".text",#alloc,#execinstr
214 .globl md5_block_asm_data_order
216 md5_block_asm_data_order:
217 SPARC_LOAD_ADDRESS_LEAF(OPENSSL_sparcv9cap_P,%g1,%g5)
218 ld [%g1+4],%g1 ! OPENSSL_sparcv9cap_P[1]
220 andcc %g1, CFR_MD5, %g0
225 wr %g0, 0x88, %asi ! ASI_PRIMARY_LITTLE
227 lda [%o0 + 0x00] %asi, %f0 ! load context
228 lda [%o0 + 0x04] %asi, %f1
230 lda [%o0 + 0x08] %asi, %f2
231 bne,pn %icc, .Lhwunaligned
232 lda [%o0 + 0x0c] %asi, %f3
235 ldd [%o1 + 0x00], %f8
236 ldd [%o1 + 0x08], %f10
237 ldd [%o1 + 0x10], %f12
238 ldd [%o1 + 0x18], %f14
239 ldd [%o1 + 0x20], %f16
240 ldd [%o1 + 0x28], %f18
241 ldd [%o1 + 0x30], %f20
242 subcc %o2, 1, %o2 ! done yet?
243 ldd [%o1 + 0x38], %f22
245 prefetch [%o1 + 63], 20
247 .word 0x81b02800 ! MD5
249 bne,pt `$bits==64?"%xcc":"%icc"`, .Lhw_loop
253 sta %f0, [%o0 + 0x00] %asi ! store context
254 sta %f1, [%o0 + 0x04] %asi
255 sta %f2, [%o0 + 0x08] %asi
256 sta %f3, [%o0 + 0x0c] %asi
258 wr %g5, 0x0, %asi ! restore %asi
262 alignaddr %o1, %g0, %o1
264 ldd [%o1 + 0x00], %f10
266 ldd [%o1 + 0x08], %f12
267 ldd [%o1 + 0x10], %f14
268 ldd [%o1 + 0x18], %f16
269 ldd [%o1 + 0x20], %f18
270 ldd [%o1 + 0x28], %f20
271 ldd [%o1 + 0x30], %f22
272 ldd [%o1 + 0x38], %f24
273 subcc %o2, 1, %o2 ! done yet?
274 ldd [%o1 + 0x40], %f26
276 prefetch [%o1 + 63], 20
278 faligndata %f10, %f12, %f8
279 faligndata %f12, %f14, %f10
280 faligndata %f14, %f16, %f12
281 faligndata %f16, %f18, %f14
282 faligndata %f18, %f20, %f16
283 faligndata %f20, %f22, %f18
284 faligndata %f22, %f24, %f20
285 faligndata %f24, %f26, %f22
287 .word 0x81b02800 ! MD5
289 bne,pt `$bits==64?"%xcc":"%icc"`, .Lhwunaligned_loop
290 for %f26, %f26, %f10 ! %f10=%f26
300 wr %g0,0x88,%asi ! ASI_PRIMARY_LITTLE
304 sll $shr,3,$shr ! *=8
312 sub $shl2,$shl1,$shl2 ! shr+shl1+shl2==64
317 cmp $shr,0 ! was inp aligned?
318 ldxa [$inp+0]%asi,@X[0] ! load little-endian input
319 ldxa [$inp+8]%asi,@X[1]
320 ldxa [$inp+16]%asi,@X[2]
321 ldxa [$inp+24]%asi,@X[3]
322 ldxa [$inp+32]%asi,@X[4]
323 sllx $A,32,$AB ! pack A,B
324 ldxa [$inp+40]%asi,@X[5]
325 sllx $C,32,$CD ! pack C,D
326 ldxa [$inp+48]%asi,@X[6]
328 ldxa [$inp+56]%asi,@X[7]
331 ldxa [$inp+64]%asi,@X[8]
333 srlx @X[0],$shr,@X[0] ! align X[0]
337 or $t2,%lo(@K[0]),$t2
340 add @X[0],$t2,$t2 ! X[0]+K[0]
342 for ($i=0;$i<15;$i++) { &R0($i,@V); unshift(@V,pop(@V)); }
343 for (;$i<16;$i++) { &R0_1($i,@V); unshift(@V,pop(@V)); }
344 for (;$i<32;$i++) { &R1($i,@V); unshift(@V,pop(@V)); }
345 for (;$i<48;$i++) { &R2($i,@V); unshift(@V,pop(@V)); }
346 for (;$i<64;$i++) { &R3($i,@V); unshift(@V,pop(@V)); }
348 srlx $AB,32,$t1 ! unpack A,B,C,D and accumulate
349 add $inp,64,$inp ! advance inp
352 subcc $len,1,$len ! done yet?
356 srl $B,0,$B ! clruw $B
357 bne `$bits==64?"%xcc":"%icc"`,.Loop
358 srl $D,0,$D ! clruw $D
360 st $A,[$ctx+0] ! write out ctx
365 wr %g0,$saved_asi,%asi
368 .type md5_block_asm_data_order,#function
369 .size md5_block_asm_data_order,(.-md5_block_asm_data_order)
371 .asciz "MD5 block transform for SPARCv9, CRYPTOGAMS by <appro\@openssl.org>"
375 # Purpose of these subroutines is to explicitly encode VIS instructions,
376 # so that one can compile the module without having to specify VIS
377 # extentions on compiler command line, e.g. -xarch=v9 vs. -xarch=v9a.
378 # Idea is to reserve for option to produce "universal" binary and let
379 # programmer detect if current CPU is VIS capable at run-time.
381 my ($mnemonic,$rs1,$rs2,$rd)=@_;
383 my %visopf = ( "faligndata" => 0x048,
386 $ref = "$mnemonic\t$rs1,$rs2,$rd";
388 if ($opf=$visopf{$mnemonic}) {
389 foreach ($rs1,$rs2,$rd) {
390 return $ref if (!/%f([0-9]{1,2})/);
393 return $ref if ($1&1);
394 # re-encode for upper double register addressing
399 return sprintf ".word\t0x%08x !%s",
400 0x81b00000|$rd<<25|$rs1<<14|$opf<<5|$rs2,
407 my ($mnemonic,$rs1,$rs2,$rd)=@_;
408 my %bias = ( "g" => 0, "o" => 8, "l" => 16, "i" => 24 );
409 my $ref="$mnemonic\t$rs1,$rs2,$rd";
411 foreach ($rs1,$rs2,$rd) {
412 if (/%([goli])([0-7])/) { $_=$bias{$1}+$2; }
413 else { return $ref; }
415 return sprintf ".word\t0x%08x !%s",
416 0x81b00300|$rd<<25|$rs1<<14|$rs2,
420 foreach (split("\n",$code)) {
421 s/\`([^\`]*)\`/eval $1/ge;
423 s/\b(f[^\s]*)\s+(%f[0-9]{1,2}),\s*(%f[0-9]{1,2}),\s*(%f[0-9]{1,2})/
426 s/\b(alignaddr)\s+(%[goli][0-7]),\s*(%[goli][0-7]),\s*(%[goli][0-7])/
427 &unalignaddr($1,$2,$3,$4)