3 # ====================================================================
4 # Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
5 # project. Rights for redistribution and usage in source and binary
6 # forms are granted according to the OpenSSL license.
7 # ====================================================================
11 # "Teaser" Montgomery multiplication module for UltraSPARC. Why FPU?
12 # Because unlike integer multiplier, which simply stalls whole CPU,
13 # FPU is fully pipelined and can effectively emit 48 bit partial
14 # product every cycle. Why not blended SPARC v9? One can argue that
15 # making this module dependent on UltraSPARC VIS extension limits its
16 # binary compatibility. Well yes, it does exclude SPARC64 prior-V(!)
17 # implementations from compatibility matrix. But the rest, whole Sun
18 # UltraSPARC family and brand new Fujitsu's SPARC64 V, all support
19 # VIS extension instructions used in this module. This is considered
20 # good enough to recommend HAL SPARC64 users [if any] to simply fall
21 # down to no-asm configuration.
23 # USI&II cores currently exhibit uniform 2x improvement [over pre-
24 # bn_mul_mont codebase] for all key lengths and benchmarks. On USIII
25 # performance improves few percents for shorter keys and worsens few
26 # percents for longer keys. This is because USIII integer multiplier
27 # is >3x faster than USI&II one, which is harder to match [but see
28 # TODO list below]. It should also be noted that SPARC64 V features
29 # out-of-order execution, which *might* mean that integer multiplier
30 # is pipelined, which in turn *might* be impossible to match... On
31 # additional note, SPARC64 V implements FP Multiply-Add instruction,
32 # which is perfectly usable in this context... In other words, as far
33 # as HAL/Fujitsu SPARC64 family goes, talk to the author:-)
35 # In 32-bit context the implementation implies following additional
36 # limitations on input arguments:
37 # - num may not be less than 4;
38 # - num has to be even;
39 # - ap, bp, rp, np has to be 64-bit aligned [which is not a problem
40 # as long as BIGNUM.d are malloc-ated];
41 # Failure to meet either condition has no fatal effects, simply
42 # doesn't give any performance gain.
45 # - modulo-schedule inner loop for better performance (on in-order
46 # execution core such as UltraSPARC this shall result in further
47 # noticeable(!) improvement);
48 # - dedicated squaring procedure[?];
53 $bits=64 if (/\-m64/ || /\-xarch\=v9/);
54 $vis=1 if (/\-mcpu=ultra/ || /\-xarch\=v[9|8plus]\S/);
59 .section ".text",#alloc,#execinstr
63 xor %o0,%o0,%o0 ! just signal "not implemented"
64 .type $fname,#function
65 .size $fname,(.-$fname)
75 $frame=128; # 96 rounded up to largest known cache-line
79 # In order to provide for 32-/64-bit ABI duality, I keep integers wider
80 # than 32 bit in %g1-%g4 and %o0-%o5. %l0-%l7 and %i0-%i5 are used
81 # exclusively for pointers, indexes and other small values...
83 $rp="%i0"; # BN_ULONG *rp,
84 $ap="%i1"; # const BN_ULONG *ap,
85 $bp="%i2"; # const BN_ULONG *bp,
86 $np="%i3"; # const BN_ULONG *np,
87 $n0="%i4"; # const BN_ULONG *n0,
88 $num="%i5"; # int num);
91 $ap_l="%l1"; # a[num],n[num] are smashed to 32-bit words and saved
92 $ap_h="%l2"; # to these four vectors as double-precision FP values.
93 $np_l="%l3"; # This way a bunch of fxtods are eliminated in second
94 $np_h="%l4"; # loop and L1-cache aliasing is minimized...
97 $mask="%l7"; # 16-bit mask, 0xffff
99 $n0="%g4"; # reassigned(!) to "64-bit" register
100 $carry="%i4"; # %i4 reused(!) for a carry bit
102 # FP register naming chart
117 $ba="%f0"; $bb="%f2"; $bc="%f4"; $bd="%f6";
118 $na="%f8"; $nb="%f10"; $nc="%f12"; $nd="%f14";
119 $alo="%f16"; $alo_="%f17"; $ahi="%f18"; $ahi_="%f19";
120 $nlo="%f20"; $nlo_="%f21"; $nhi="%f22"; $nhi_="%f23";
122 $dota="%f24"; $dotb="%f26";
124 $aloa="%f32"; $alob="%f34"; $aloc="%f36"; $alod="%f38";
125 $ahia="%f40"; $ahib="%f42"; $ahic="%f44"; $ahid="%f46";
126 $nloa="%f48"; $nlob="%f50"; $nloc="%f52"; $nlod="%f54";
127 $nhia="%f56"; $nhib="%f58"; $nhic="%f60"; $nhid="%f62";
129 $ASI_FL16_P=0xD2; # magic ASI value to engage 16-bit FP load
132 .ident "UltraSPARC Montgomery multiply by <appro\@fy.chalmers.se>"
133 .section ".text",#alloc,#execinstr
138 save %sp,-$frame-$locals,%sp
139 sethi %hi(0xffff),$mask
140 or $mask,%lo(0xffff),$mask
142 $code.=<<___ if ($bits==64);
143 ldx [%i4],$n0 ! $n0 reassigned, remember?
145 $code.=<<___ if ($bits==32);
149 andcc $num,1,%g0 ! $num has to be even...
151 clr %i0 ! signal "unsupported input value"
156 andcc %l0,7,%g0 ! ...and pointers has to be 8-byte aligned
158 clr %i0 ! signal "unsupported input value"
159 ld [%i4+0],$n0 ! $n0 reassigned, remember?
162 or %o0,$n0,$n0 ! $n0=n0[1].n0[0]
165 sll $num,3,$num ! num*=8
167 add %sp,$bias,%o0 ! real top of stack
169 add %o1,$num,%o1 ! %o1=num*5
171 and %o0,-2048,%o0 ! optimize TLB utilization
172 sub %o0,$bias,%sp ! alloca(5*num*8)
174 rd %asi,%o7 ! save %asi
175 add %sp,$bias+$frame+$locals,$tp
177 add $ap_l,$num,$ap_l ! [an]p_[lh] point at the vectors' ends !
182 wr %g0,$ASI_FL16_P,%asi ! setup %asi for 16-bit FP loads
184 add $rp,$num,$rp ! readjust input pointers to point
185 add $ap,$num,$ap ! at the ends too...
189 stx %o7,[%sp+$bias+$frame+48] ! save %asi
197 $code.=<<___ if ($bits==64);
198 ldx [$bp+$i],%o0 ! bp[0]
199 ldx [$ap+$j],%o1 ! ap[0]
201 $code.=<<___ if ($bits==32);
202 ldd [$bp+$i],%o0 ! bp[0]
203 ldd [$ap+$j],%g2 ! ap[0]
212 mulx %o1,%o0,%o0 ! ap[0]*bp[0]
213 mulx $n0,%o0,%o0 ! ap[0]*bp[0]*n0
214 stx %o0,[%sp+$bias+$frame+0]
216 ld [%o3+`$bits==32 ? 0 : 4`],$alo_ ! load a[j] as pair of 32-bit words
218 ld [%o3+`$bits==32 ? 4 : 0`],$ahi_
220 ld [%o5+`$bits==32 ? 0 : 4`],$nlo_ ! load n[j] as pair of 32-bit words
222 ld [%o5+`$bits==32 ? 4 : 0`],$nhi_
225 ! transfer b[i] to FPU as 4x16-bit values
226 ldda [%o4+`$bits==32 ? 2 : 6`]%asi,$ba
228 ldda [%o4+`$bits==32 ? 0 : 4`]%asi,$bb
230 ldda [%o4+`$bits==32 ? 6 : 2`]%asi,$bc
232 ldda [%o4+`$bits==32 ? 4 : 0`]%asi,$bd
235 ! transfer ap[0]*b[0]*n0 to FPU as 4x16-bit values
236 ldda [%sp+$bias+$frame+6]%asi,$na
238 ldda [%sp+$bias+$frame+4]%asi,$nb
240 ldda [%sp+$bias+$frame+2]%asi,$nc
242 ldda [%sp+$bias+$frame+0]%asi,$nd
245 std $alo,[$ap_l+$j] ! save smashed ap[j] in double format
249 std $nlo,[$np_l+$j] ! save smashed np[j] in double format
260 faddd $aloa,$nloa,$nloa
263 faddd $alob,$nlob,$nlob
266 faddd $aloc,$nloc,$nloc
269 faddd $alod,$nlod,$nlod
272 faddd $ahia,$nhia,$nhia
276 faddd $ahib,$nhib,$nhib
277 faddd $ahic,$nhic,$dota ! $nhic
278 faddd $ahid,$nhid,$dotb ! $nhid
280 faddd $nloc,$nhia,$nloc
281 faddd $nlod,$nhib,$nlod
288 std $nloa,[%sp+$bias+$frame+0]
289 std $nlob,[%sp+$bias+$frame+8]
290 std $nloc,[%sp+$bias+$frame+16]
291 std $nlod,[%sp+$bias+$frame+24]
292 ldx [%sp+$bias+$frame+0],%o0
293 ldx [%sp+$bias+$frame+8],%o1
294 ldx [%sp+$bias+$frame+16],%o2
295 ldx [%sp+$bias+$frame+24],%o3
302 add %o7,%o3,%o3 ! %o3.%o2[0..15].%o1[0..15].%o0[0..15]
311 !or %o7,%o0,%o0 ! 64-bit result
312 srlx %o3,16,%g1 ! 34-bit carry
320 ld [%o3+`$bits==32 ? 0 : 4`],$alo_ ! load a[j] as pair of 32-bit words
322 ld [%o3+`$bits==32 ? 4 : 0`],$ahi_
324 ld [%o4+`$bits==32 ? 0 : 4`],$nlo_ ! load n[j] as pair of 32-bit words
326 ld [%o4+`$bits==32 ? 4 : 0`],$nhi_
334 std $alo,[$ap_l+$j] ! save smashed ap[j] in double format
338 std $nlo,[$np_l+$j] ! save smashed np[j] in double format
344 faddd $aloa,$nloa,$nloa
347 faddd $alob,$nlob,$nlob
350 faddd $aloc,$nloc,$nloc
353 faddd $alod,$nlod,$nlod
356 faddd $ahia,$nhia,$nhia
359 faddd $ahib,$nhib,$nhib
361 faddd $dota,$nloa,$nloa
362 faddd $dotb,$nlob,$nlob
363 faddd $ahic,$nhic,$dota ! $nhic
364 faddd $ahid,$nhid,$dotb ! $nhid
366 faddd $nloc,$nhia,$nloc
367 faddd $nlod,$nhib,$nlod
374 std $nloa,[%sp+$bias+$frame+0]
375 std $nlob,[%sp+$bias+$frame+8]
376 std $nloc,[%sp+$bias+$frame+16]
377 std $nlod,[%sp+$bias+$frame+24]
378 ldx [%sp+$bias+$frame+0],%o0
379 ldx [%sp+$bias+$frame+8],%o1
380 ldx [%sp+$bias+$frame+16],%o2
381 ldx [%sp+$bias+$frame+24],%o3
388 add %o7,%o3,%o3 ! %o3.%o2[0..15].%o1[0..15].%o0[0..15]
397 or %o7,%o0,%o0 ! 64-bit result
399 srlx %o3,16,%g1 ! 34-bit carry
403 stx %o0,[$tp] ! tp[j-1]=
410 std $dota,[%sp+$bias+$frame+32]
411 std $dotb,[%sp+$bias+$frame+40]
412 ldx [%sp+$bias+$frame+32],%o0
413 ldx [%sp+$bias+$frame+40],%o1
426 stx %o0,[$tp] ! tp[num-1]=
433 add %sp,$bias+$frame+$locals,$tp
437 $code.=<<___ if ($bits==64);
438 ldx [$bp+$i],%o0 ! bp[i]
439 ldx [$ap+$j],%o1 ! ap[0]
441 $code.=<<___ if ($bits==32);
442 ldd [$bp+$i],%o0 ! bp[i]
443 ldd [$ap+$j],%g2 ! ap[0]
450 ldx [$tp],%o2 ! tp[0]
453 mulx $n0,%o0,%o0 ! (ap[0]*bp[i]+t[0])*n0
454 stx %o0,[%sp+$bias+$frame+0]
457 ! transfer b[i] to FPU as 4x16-bit values
458 ldda [%o4+`$bits==32 ? 2 : 6`]%asi,$ba
459 ldda [%o4+`$bits==32 ? 0 : 4`]%asi,$bb
460 ldda [%o4+`$bits==32 ? 6 : 2`]%asi,$bc
461 ldda [%o4+`$bits==32 ? 4 : 0`]%asi,$bd
463 ! transfer (ap[0]*b[i]+t[0])*n0 to FPU as 4x16-bit values
464 ldda [%sp+$bias+$frame+6]%asi,$na
466 ldda [%sp+$bias+$frame+4]%asi,$nb
468 ldda [%sp+$bias+$frame+2]%asi,$nc
470 ldda [%sp+$bias+$frame+0]%asi,$nd
472 ldd [$ap_l+$j],$alo ! load a[j] in double format
476 ldd [$np_l+$j],$nlo ! load n[j] in double format
487 faddd $aloa,$nloa,$nloa
490 faddd $alob,$nlob,$nlob
493 faddd $aloc,$nloc,$nloc
496 faddd $alod,$nlod,$nlod
499 faddd $ahia,$nhia,$nhia
503 faddd $ahib,$nhib,$nhib
504 faddd $ahic,$nhic,$dota ! $nhic
505 faddd $ahid,$nhid,$dotb ! $nhid
507 faddd $nloc,$nhia,$nloc
508 faddd $nlod,$nhib,$nlod
515 std $nloa,[%sp+$bias+$frame+0]
516 std $nlob,[%sp+$bias+$frame+8]
517 std $nloc,[%sp+$bias+$frame+16]
518 std $nlod,[%sp+$bias+$frame+24]
519 ldx [%sp+$bias+$frame+0],%o0
520 ldx [%sp+$bias+$frame+8],%o1
521 ldx [%sp+$bias+$frame+16],%o2
522 ldx [%sp+$bias+$frame+24],%o3
529 add %o7,%o3,%o3 ! %o3.%o2[0..15].%o1[0..15].%o0[0..15]
539 or %o7,%o0,%o0 ! 64-bit result
543 srlx %o3,16,%g1 ! 34-bit carry
551 ldd [$ap_l+$j],$alo ! load a[j] in double format
553 ldd [$np_l+$j],$nlo ! load n[j] in double format
562 faddd $aloa,$nloa,$nloa
565 faddd $alob,$nlob,$nlob
568 faddd $aloc,$nloc,$nloc
571 faddd $alod,$nlod,$nlod
574 faddd $ahia,$nhia,$nhia
578 faddd $ahib,$nhib,$nhib
579 faddd $dota,$nloa,$nloa
580 faddd $dotb,$nlob,$nlob
581 faddd $ahic,$nhic,$dota ! $nhic
582 faddd $ahid,$nhid,$dotb ! $nhid
584 faddd $nloc,$nhia,$nloc
585 faddd $nlod,$nhib,$nlod
592 std $nloa,[%sp+$bias+$frame+0]
593 std $nlob,[%sp+$bias+$frame+8]
594 std $nloc,[%sp+$bias+$frame+16]
595 std $nlod,[%sp+$bias+$frame+24]
596 ldx [%sp+$bias+$frame+0],%o0
597 ldx [%sp+$bias+$frame+8],%o1
598 ldx [%sp+$bias+$frame+16],%o2
599 ldx [%sp+$bias+$frame+24],%o3
606 add %o7,%o3,%o3 ! %o3.%o2[0..15].%o1[0..15].%o0[0..15]
615 or %o7,%o0,%o0 ! 64-bit result
617 srlx %o3,16,%g1 ! 34-bit carry
621 ldx [$tp+8],%o7 ! tp[j]
626 stx %o0,[$tp] ! tp[j-1]
633 std $dota,[%sp+$bias+$frame+32]
634 std $dotb,[%sp+$bias+$frame+40]
635 ldx [%sp+$bias+$frame+32],%o0
636 ldx [%sp+$bias+$frame+40],%o1
649 stx %o0,[$tp] ! tp[num-1]
658 sub %g0,$num,%o7 ! n=-num
659 cmp $carry,0 ! clears %icc.c
661 add $tp,8,$tp ! adjust tp to point at the end
664 ld [$np-`$bits==32 ? 4 : 8`],%o1
665 cmp %o0,%o1 ! compare topmost words
666 bcs,pt %icc,.Lcopy ! %icc.c is clean if not taken
674 $code.=<<___ if ($bits==64);
678 $code.=<<___ if ($bits==32);
687 subccc $carry,0,$carry
695 $code.=<<___ if ($bits==64);
698 $code.=<<___ if ($bits==32);
720 ldx [%sp+$bias+$frame+48],%o7
721 wr %g0,%o7,%asi ! restore %asi
727 .type $fname,#function
728 .size $fname,(.-$fname)
731 $code =~ s/\`([^\`]*)\`/eval($1)/gem;