3 # ====================================================================
4 # Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
5 # project. The module is, however, dual licensed under OpenSSL and
6 # CRYPTOGAMS licenses depending on where you obtain it. For further
7 # details see http://www.openssl.org/~appro/cryptogams/.
8 # ====================================================================
12 # "Teaser" Montgomery multiplication module for UltraSPARC. Why FPU?
13 # Because unlike integer multiplier, which simply stalls whole CPU,
14 # FPU is fully pipelined and can effectively emit 48 bit partial
15 # product every cycle. Why not blended SPARC v9? One can argue that
16 # making this module dependent on UltraSPARC VIS extension limits its
17 # binary compatibility. Well yes, it does exclude SPARC64 prior-V(!)
18 # implementations from compatibility matrix. But the rest, whole Sun
19 # UltraSPARC family and brand new Fujitsu's SPARC64 V, all support
20 # VIS extension instructions used in this module. This is considered
21 # good enough to not care about HAL SPARC64 users [if any] who have
22 # integer-only pure SPARCv9 module to "fall down" to.
24 # USI&II cores currently exhibit uniform 2x improvement [over pre-
25 # bn_mul_mont codebase] for all key lengths and benchmarks. On USIII
26 # performance improves few percents for shorter keys and worsens few
27 # percents for longer keys. This is because USIII integer multiplier
28 # is >3x faster than USI&II one, which is harder to match [but see
29 # TODO list below]. It should also be noted that SPARC64 V features
30 # out-of-order execution, which *might* mean that integer multiplier
31 # is pipelined, which in turn *might* be impossible to match... On
32 # additional note, SPARC64 V implements FP Multiply-Add instruction,
33 # which is perfectly usable in this context... In other words, as far
34 # as Fujitsu SPARC64 V goes, talk to the author:-)
36 # The implementation implies following "non-natural" limitations on
38 # - num may not be less than 4;
39 # - num has to be even;
40 # Failure to meet either condition has no fatal effects, simply
41 # doesn't give any performance gain.
44 # - modulo-schedule inner loop for better performance (on in-order
45 # execution core such as UltraSPARC this shall result in further
46 # noticeable(!) improvement);
47 # - dedicated squaring procedure[?];
49 ######################################################################
52 # Modulo-scheduled inner loops allow to interleave floating point and
53 # integer instructions and minimize Read-After-Write penalties. This
54 # results in *further* 20-50% perfromance improvement [depending on
55 # key length, more for longer keys] on USI&II cores and 30-80% - on
58 $fname="bn_mul_mont_fpu";
60 for (@ARGV) { $bits=64 if (/\-m64/ || /\-xarch\=v9/); }
67 $frame=128; # 96 rounded up to largest known cache-line
71 # In order to provide for 32-/64-bit ABI duality, I keep integers wider
72 # than 32 bit in %g1-%g4 and %o0-%o5. %l0-%l7 and %i0-%i5 are used
73 # exclusively for pointers, indexes and other small values...
75 $rp="%i0"; # BN_ULONG *rp,
76 $ap="%i1"; # const BN_ULONG *ap,
77 $bp="%i2"; # const BN_ULONG *bp,
78 $np="%i3"; # const BN_ULONG *np,
79 $n0="%i4"; # const BN_ULONG *n0,
80 $num="%i5"; # int num);
83 $ap_l="%l1"; # a[num],n[num] are smashed to 32-bit words and saved
84 $ap_h="%l2"; # to these four vectors as double-precision FP values.
85 $np_l="%l3"; # This way a bunch of fxtods are eliminated in second
86 $np_h="%l4"; # loop and L1-cache aliasing is minimized...
89 $mask="%l7"; # 16-bit mask, 0xffff
91 $n0="%g4"; # reassigned(!) to "64-bit" register
92 $carry="%i4"; # %i4 reused(!) for a carry bit
94 # FP register naming chart
109 $ba="%f0"; $bb="%f2"; $bc="%f4"; $bd="%f6";
110 $na="%f8"; $nb="%f10"; $nc="%f12"; $nd="%f14";
111 $alo="%f16"; $alo_="%f17"; $ahi="%f18"; $ahi_="%f19";
112 $nlo="%f20"; $nlo_="%f21"; $nhi="%f22"; $nhi_="%f23";
114 $dota="%f24"; $dotb="%f26";
116 $aloa="%f32"; $alob="%f34"; $aloc="%f36"; $alod="%f38";
117 $ahia="%f40"; $ahib="%f42"; $ahic="%f44"; $ahid="%f46";
118 $nloa="%f48"; $nlob="%f50"; $nloc="%f52"; $nlod="%f54";
119 $nhia="%f56"; $nhib="%f58"; $nhic="%f60"; $nhid="%f62";
121 $ASI_FL16_P=0xD2; # magic ASI value to engage 16-bit FP load
124 .ident "UltraSPARC Montgomery multiply by <appro\@fy.chalmers.se>"
125 .section ".text",#alloc,#execinstr
130 save %sp,-$frame-$locals,%sp
135 andcc $num,1,%g0 ! $num has to be even...
137 clr %i0 ! signal "unsupported input value"
140 sethi %hi(0xffff),$mask
141 ld [%i4+0],$n0 ! $n0 reassigned, remember?
142 or $mask,%lo(0xffff),$mask
145 or %o0,$n0,$n0 ! $n0=n0[1].n0[0]
147 sll $num,3,$num ! num*=8
149 add %sp,$bias,%o0 ! real top of stack
151 add %o1,$num,%o1 ! %o1=num*5
153 and %o0,-2048,%o0 ! optimize TLB utilization
154 sub %o0,$bias,%sp ! alloca(5*num*8)
156 rd %asi,%o7 ! save %asi
157 add %sp,$bias+$frame+$locals,$tp
159 add $ap_l,$num,$ap_l ! [an]p_[lh] point at the vectors' ends !
164 wr %g0,$ASI_FL16_P,%asi ! setup %asi for 16-bit FP loads
166 add $rp,$num,$rp ! readjust input pointers to point
167 add $ap,$num,$ap ! at the ends too...
171 stx %o7,[%sp+$bias+$frame+48] ! save %asi
173 sub %g0,$num,$i ! i=-num
174 sub %g0,$num,$j ! j=-num
179 ld [%o3+4],%g1 ! bp[0]
181 ld [%o4+4],%g5 ! ap[0]
190 mulx %o1,%o0,%o0 ! ap[0]*bp[0]
191 mulx $n0,%o0,%o0 ! ap[0]*bp[0]*n0
192 stx %o0,[%sp+$bias+$frame+0]
194 ld [%o3+0],$alo_ ! load a[j] as pair of 32-bit words
198 ld [%o5+0],$nlo_ ! load n[j] as pair of 32-bit words
203 ! transfer b[i] to FPU as 4x16-bit values
213 ! transfer ap[0]*b[0]*n0 to FPU as 4x16-bit values
214 ldda [%sp+$bias+$frame+6]%asi,$na
216 ldda [%sp+$bias+$frame+4]%asi,$nb
218 ldda [%sp+$bias+$frame+2]%asi,$nc
220 ldda [%sp+$bias+$frame+0]%asi,$nd
223 std $alo,[$ap_l+$j] ! save smashed ap[j] in double format
227 std $nlo,[$np_l+$j] ! save smashed np[j] in double format
237 faddd $aloa,$nloa,$nloa
240 faddd $alob,$nlob,$nlob
243 faddd $aloc,$nloc,$nloc
246 faddd $alod,$nlod,$nlod
249 faddd $ahia,$nhia,$nhia
252 faddd $ahib,$nhib,$nhib
255 faddd $ahic,$nhic,$dota ! $nhic
256 faddd $ahid,$nhid,$dotb ! $nhid
258 faddd $nloc,$nhia,$nloc
259 faddd $nlod,$nhib,$nlod
266 std $nloa,[%sp+$bias+$frame+0]
268 std $nlob,[%sp+$bias+$frame+8]
270 std $nloc,[%sp+$bias+$frame+16]
272 std $nlod,[%sp+$bias+$frame+24]
274 ld [%o4+0],$alo_ ! load a[j] as pair of 32-bit words
278 ld [%o5+0],$nlo_ ! load n[j] as pair of 32-bit words
288 ldx [%sp+$bias+$frame+0],%o0
290 ldx [%sp+$bias+$frame+8],%o1
292 ldx [%sp+$bias+$frame+16],%o2
294 ldx [%sp+$bias+$frame+24],%o3
298 std $alo,[$ap_l+$j] ! save smashed ap[j] in double format
302 faddd $aloa,$nloa,$nloa
305 std $nlo,[$np_l+$j] ! save smashed np[j] in double format
309 faddd $alob,$nlob,$nlob
313 add %o7,%o3,%o3 ! %o3.%o2[0..15].%o1[0..15].%o0[0..15]
314 faddd $aloc,$nloc,$nloc
324 !or %o7,%o0,%o0 ! 64-bit result
325 srlx %o3,16,%g1 ! 34-bit carry
328 faddd $alod,$nlod,$nlod
331 faddd $ahia,$nhia,$nhia
334 faddd $ahib,$nhib,$nhib
337 faddd $dota,$nloa,$nloa
338 faddd $dotb,$nlob,$nlob
339 faddd $ahic,$nhic,$dota ! $nhic
340 faddd $ahid,$nhid,$dotb ! $nhid
342 faddd $nloc,$nhia,$nloc
343 faddd $nlod,$nhib,$nlod
350 std $nloa,[%sp+$bias+$frame+0]
351 std $nlob,[%sp+$bias+$frame+8]
353 std $nloc,[%sp+$bias+$frame+16]
355 std $nlod,[%sp+$bias+$frame+24]
361 ld [%o4+0],$alo_ ! load a[j] as pair of 32-bit words
365 ld [%o5+0],$nlo_ ! load n[j] as pair of 32-bit words
375 ldx [%sp+$bias+$frame+0],%o0
377 ldx [%sp+$bias+$frame+8],%o1
379 ldx [%sp+$bias+$frame+16],%o2
381 ldx [%sp+$bias+$frame+24],%o3
385 std $alo,[$ap_l+$j] ! save smashed ap[j] in double format
389 faddd $aloa,$nloa,$nloa
392 std $nlo,[$np_l+$j] ! save smashed np[j] in double format
396 faddd $alob,$nlob,$nlob
400 add %o7,%o3,%o3 ! %o3.%o2[0..15].%o1[0..15].%o0[0..15]
402 faddd $aloc,$nloc,$nloc
408 faddd $alod,$nlod,$nlod
414 faddd $ahia,$nhia,$nhia
418 or %o7,%o0,%o0 ! 64-bit result
419 faddd $ahib,$nhib,$nhib
422 faddd $dota,$nloa,$nloa
423 srlx %o3,16,%g1 ! 34-bit carry
424 faddd $dotb,$nlob,$nlob
428 stx %o0,[$tp] ! tp[j-1]=
430 faddd $ahic,$nhic,$dota ! $nhic
431 faddd $ahid,$nhid,$dotb ! $nhid
433 faddd $nloc,$nhia,$nloc
434 faddd $nlod,$nhib,$nlod
441 std $nloa,[%sp+$bias+$frame+0]
442 std $nlob,[%sp+$bias+$frame+8]
443 std $nloc,[%sp+$bias+$frame+16]
444 std $nlod,[%sp+$bias+$frame+24]
454 ldx [%sp+$bias+$frame+0],%o0
455 ldx [%sp+$bias+$frame+8],%o1
456 ldx [%sp+$bias+$frame+16],%o2
457 ldx [%sp+$bias+$frame+24],%o3
460 std $dota,[%sp+$bias+$frame+32]
462 std $dotb,[%sp+$bias+$frame+40]
466 add %o7,%o3,%o3 ! %o3.%o2[0..15].%o1[0..15].%o0[0..15]
475 or %o7,%o0,%o0 ! 64-bit result
476 ldx [%sp+$bias+$frame+32],%o4
478 ldx [%sp+$bias+$frame+40],%o5
479 srlx %o3,16,%g1 ! 34-bit carry
483 stx %o0,[$tp] ! tp[j-1]=
497 stx %o4,[$tp] ! tp[num-1]=
503 sub %g0,$num,$j ! j=-num
504 add %sp,$bias+$frame+$locals,$tp
509 ld [%o3+4],%g1 ! bp[i]
511 ld [%o4+4],%g5 ! ap[0]
518 ldx [$tp],%o2 ! tp[0]
521 mulx $n0,%o0,%o0 ! (ap[0]*bp[i]+t[0])*n0
522 stx %o0,[%sp+$bias+$frame+0]
524 ! transfer b[i] to FPU as 4x16-bit values
530 ! transfer (ap[0]*b[i]+t[0])*n0 to FPU as 4x16-bit values
531 ldda [%sp+$bias+$frame+6]%asi,$na
533 ldda [%sp+$bias+$frame+4]%asi,$nb
535 ldda [%sp+$bias+$frame+2]%asi,$nc
537 ldda [%sp+$bias+$frame+0]%asi,$nd
539 ldd [$ap_l+$j],$alo ! load a[j] in double format
543 ldd [$np_l+$j],$nlo ! load n[j] in double format
553 faddd $aloa,$nloa,$nloa
556 faddd $alob,$nlob,$nlob
559 faddd $aloc,$nloc,$nloc
562 faddd $alod,$nlod,$nlod
565 faddd $ahia,$nhia,$nhia
568 faddd $ahib,$nhib,$nhib
571 faddd $ahic,$nhic,$dota ! $nhic
572 faddd $ahid,$nhid,$dotb ! $nhid
574 faddd $nloc,$nhia,$nloc
575 faddd $nlod,$nhib,$nlod
582 std $nloa,[%sp+$bias+$frame+0]
583 std $nlob,[%sp+$bias+$frame+8]
584 std $nloc,[%sp+$bias+$frame+16]
586 std $nlod,[%sp+$bias+$frame+24]
588 ldd [$ap_l+$j],$alo ! load a[j] in double format
590 ldd [$np_l+$j],$nlo ! load n[j] in double format
598 ldx [%sp+$bias+$frame+0],%o0
599 faddd $aloa,$nloa,$nloa
601 ldx [%sp+$bias+$frame+8],%o1
603 ldx [%sp+$bias+$frame+16],%o2
604 faddd $alob,$nlob,$nlob
606 ldx [%sp+$bias+$frame+24],%o3
610 faddd $aloc,$nloc,$nloc
615 faddd $alod,$nlod,$nlod
620 faddd $ahia,$nhia,$nhia
622 add %o7,%o3,%o3 ! %o3.%o2[0..15].%o1[0..15].%o0[0..15]
628 faddd $ahib,$nhib,$nhib
631 faddd $dota,$nloa,$nloa
633 faddd $dotb,$nlob,$nlob
636 faddd $ahic,$nhic,$dota ! $nhic
638 faddd $ahid,$nhid,$dotb ! $nhid
639 or %o7,%o0,%o0 ! 64-bit result
641 faddd $nloc,$nhia,$nloc
644 faddd $nlod,$nhib,$nlod
645 srlx %o3,16,%g1 ! 34-bit carry
654 std $nloa,[%sp+$bias+$frame+0]
655 std $nlob,[%sp+$bias+$frame+8]
657 std $nloc,[%sp+$bias+$frame+16]
658 bz,pn %icc,.Linnerskip
659 std $nlod,[%sp+$bias+$frame+24]
665 ldd [$ap_l+$j],$alo ! load a[j] in double format
667 ldd [$np_l+$j],$nlo ! load n[j] in double format
675 ldx [%sp+$bias+$frame+0],%o0
676 faddd $aloa,$nloa,$nloa
678 ldx [%sp+$bias+$frame+8],%o1
680 ldx [%sp+$bias+$frame+16],%o2
681 faddd $alob,$nlob,$nlob
683 ldx [%sp+$bias+$frame+24],%o3
687 faddd $aloc,$nloc,$nloc
692 faddd $alod,$nlod,$nlod
697 faddd $ahia,$nhia,$nhia
699 add %o7,%o3,%o3 ! %o3.%o2[0..15].%o1[0..15].%o0[0..15]
704 faddd $ahib,$nhib,$nhib
707 faddd $dota,$nloa,$nloa
709 faddd $dotb,$nlob,$nlob
712 faddd $ahic,$nhic,$dota ! $nhic
714 faddd $ahid,$nhid,$dotb ! $nhid
715 or %o7,%o0,%o0 ! 64-bit result
716 faddd $nloc,$nhia,$nloc
718 ldx [$tp+8],%o7 ! tp[j]
719 faddd $nlod,$nhib,$nlod
720 srlx %o3,16,%g1 ! 34-bit carry
730 stx %o0,[$tp] ! tp[j-1]
733 std $nloa,[%sp+$bias+$frame+0]
734 std $nlob,[%sp+$bias+$frame+8]
735 std $nloc,[%sp+$bias+$frame+16]
737 std $nlod,[%sp+$bias+$frame+24]
745 ldx [%sp+$bias+$frame+0],%o0
746 ldx [%sp+$bias+$frame+8],%o1
747 ldx [%sp+$bias+$frame+16],%o2
748 ldx [%sp+$bias+$frame+24],%o3
751 std $dota,[%sp+$bias+$frame+32]
753 std $dotb,[%sp+$bias+$frame+40]
757 add %o7,%o3,%o3 ! %o3.%o2[0..15].%o1[0..15].%o0[0..15]
766 ldx [%sp+$bias+$frame+32],%o4
767 or %o7,%o0,%o0 ! 64-bit result
768 ldx [%sp+$bias+$frame+40],%o5
770 ldx [$tp+8],%o7 ! tp[j]
771 srlx %o3,16,%g1 ! 34-bit carry
779 stx %o0,[$tp] ! tp[j-1]
793 stx %o4,[$tp] ! tp[num-1]
802 sub %g0,$num,%o7 ! n=-num
803 cmp $carry,0 ! clears %icc.c
805 add $tp,8,$tp ! adjust tp to point at the end
809 cmp %o0,%o1 ! compare topmost words
810 bcs,pt %icc,.Lcopy ! %icc.c is clean if not taken
827 subccc $carry,0,$carry
829 sub %g0,$num,%o7 ! n=-num
840 sub %g0,$num,%o7 ! n=-num
853 ldx [%sp+$bias+$frame+48],%o7
854 wr %g0,%o7,%asi ! restore %asi
860 .type $fname,#function
861 .size $fname,(.-$fname)
862 .asciz "Montgomery Multipltication for UltraSPARC, CRYPTOGAMS by <appro\@openssl.org>"
865 $code =~ s/\`([^\`]*)\`/eval($1)/gem;
867 # Below substitution makes it possible to compile without demanding
868 # VIS extentions on command line, e.g. -xarch=v9 vs. -xarch=v9a. I
869 # dare to do this, because VIS capability is detected at run-time now
870 # and this routine is not called on CPU not capable to execute it. Do
871 # note that fzeros is not the only VIS dependency! Another dependency
872 # is implicit and is just _a_ numerical value loaded to %asi register,
873 # which assembler can't recognize as VIS specific...
874 $code =~ s/fzeros\s+%f([0-9]+)/
875 sprintf(".word\t0x%x\t! fzeros %%f%d",0x81b00c20|($1<<25),$1)