Fix aarch64 signed bit shift issue found by UBSAN

Also fix conditional branch out of range when using sanitisers.

Fixes #18813

Signed-off-by: Tom Cosgrove <tom.cosgrove@arm.com>
Change-Id: Ic543885091ed3ef2ddcbe21de0a4ac0bca1e2494

Reviewed-by: Paul Dale <pauli@openssl.org>
Reviewed-by: Matt Caswell <matt@openssl.org>
Reviewed-by: Tomas Mraz <tomas@openssl.org>
(Merged from https://github.com/openssl/openssl/pull/18816)

diff --git a/crypto/aes/asm/bsaes-armv8.pl b/crypto/aes/asm/bsaes-armv8.pl
index 1d1e886f0329d72b62e3251711ea9f1733e2da17..b3058e38faea0ef2a659de036811949b873fbd08 100644 (file)
--- a/crypto/aes/asm/bsaes-armv8.pl
+++ b/crypto/aes/asm/bsaes-armv8.pl
@@ -1019,13 +1019,9 @@ _bsaes_key_convert:
 //   No output registers, usual AAPCS64 register preservation
 ossl_bsaes_cbc_encrypt:
         cmp     x2, #128
-#ifdef __APPLE__
         bhs     .Lcbc_do_bsaes
         b       AES_cbc_encrypt
 .Lcbc_do_bsaes:
-#else
-        blo     AES_cbc_encrypt
-#endif
 
         // it is up to the caller to make sure we are called with enc == 0
 

diff --git a/crypto/arm_arch.h b/crypto/arm_arch.h
index 5d8788877f7f1f49713c167370ab779258d63f10..da8fb5eeb3f3dc0dc059a785496fe0697a9cf4fd 100644 (file)
--- a/crypto/arm_arch.h
+++ b/crypto/arm_arch.h
@@ -104,17 +104,17 @@ extern unsigned int OPENSSL_armv8_rsa_neonized;
 # define ARM_CPU_PART_N2           0xD49
 
 # define MIDR_PARTNUM_SHIFT       4
-# define MIDR_PARTNUM_MASK        (0xfff << MIDR_PARTNUM_SHIFT)
+# define MIDR_PARTNUM_MASK        (0xfffU << MIDR_PARTNUM_SHIFT)
 # define MIDR_PARTNUM(midr)       \
            (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
 
 # define MIDR_IMPLEMENTER_SHIFT   24
-# define MIDR_IMPLEMENTER_MASK    (0xff << MIDR_IMPLEMENTER_SHIFT)
+# define MIDR_IMPLEMENTER_MASK    (0xffU << MIDR_IMPLEMENTER_SHIFT)
 # define MIDR_IMPLEMENTER(midr)   \
            (((midr) & MIDR_IMPLEMENTER_MASK) >> MIDR_IMPLEMENTER_SHIFT)
 
 # define MIDR_ARCHITECTURE_SHIFT  16
-# define MIDR_ARCHITECTURE_MASK   (0xf << MIDR_ARCHITECTURE_SHIFT)
+# define MIDR_ARCHITECTURE_MASK   (0xfU << MIDR_ARCHITECTURE_SHIFT)
 # define MIDR_ARCHITECTURE(midr)  \
            (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
 
@@ -125,7 +125,7 @@ extern unsigned int OPENSSL_armv8_rsa_neonized;
 
 # define MIDR_CPU_MODEL(imp, partnum) \
            (((imp)     << MIDR_IMPLEMENTER_SHIFT)  | \
-            (0xf       << MIDR_ARCHITECTURE_SHIFT) | \
+            (0xfU      << MIDR_ARCHITECTURE_SHIFT) | \
             ((partnum) << MIDR_PARTNUM_SHIFT))
 
 # define MIDR_IS_CPU_MODEL(midr, imp, partnum) \