riscv: Provide a vector only implementation of Chacha20 cipher
authorYangyu Chen <cyy@cyyself.name>
Fri, 19 Apr 2024 03:49:59 +0000 (11:49 +0800)
committerTomas Mraz <tomas@openssl.org>
Wed, 8 May 2024 09:10:45 +0000 (11:10 +0200)
commit03ce37e11729bbe9964bd613c0eed6156b920208
treee49069293deb308f282cd89e522ea0686cb728fc
parent7cbca5a6d6e792c75c414e1f3fb22e2afae67988
riscv: Provide a vector only implementation of Chacha20 cipher

Although we have a Zvkb version of Chacha20, the Zvkb from the RISC-V
Vector Cryptography Bit-manipulation extension was ratified in late 2023
and does not come to the RVA23 Profile. Many CPUs in 2024 currently do not
support Zvkb but may have Vector and Bit-manipulation, which are already in
the RVA22 Profile. This commit provides a vector-only implementation that
replaced the vror with vsll+vsrl+vor and can provide enough speed for
Chacha20 for new CPUs this year.

Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Reviewed-by: Paul Dale <ppzgs1@gmail.com>
Reviewed-by: Tomas Mraz <tomas@openssl.org>
(Merged from https://github.com/openssl/openssl/pull/24069)
crypto/chacha/asm/chacha-riscv64-v-zbb.pl [moved from crypto/chacha/asm/chacha-riscv64-zbb-zvkb.pl with 71% similarity, mode: 0755]
crypto/chacha/build.info
crypto/chacha/chacha_riscv.c
crypto/perlasm/riscv.pm